From d9ed2db42a09f56bd458a1ab3c428a8ed4b37cac Mon Sep 17 00:00:00 2001
From: Th3S <46804083+the-soloist@users.noreply.github.com>
Date: Thu, 9 Jan 2025 20:56:45 +0800
Subject: [PATCH 1/2] Add arm64 regs

---
 qiling/arch/arm64.py           | 3 ++-
 qiling/arch/arm64_const.py     | 8 +++++++-
 qiling/debugger/gdb/xmlregs.py | 5 +++--
 3 files changed, 12 insertions(+), 4 deletions(-)

diff --git a/qiling/arch/arm64.py b/qiling/arch/arm64.py
index ba9f69b35..e4ca6cb36 100644
--- a/qiling/arch/arm64.py
+++ b/qiling/arch/arm64.py
@@ -44,7 +44,8 @@ def regs(self) -> QlRegisterManager:
             **arm64_const.reg_map_q,
             **arm64_const.reg_map_s,
             **arm64_const.reg_map_w,
-            **arm64_const.reg_map_v
+            **arm64_const.reg_map_v,
+            **arm64_const.reg_map_fp
         )
 
         pc_reg = 'pc'
diff --git a/qiling/arch/arm64_const.py b/qiling/arch/arm64_const.py
index 0845df59a..599562731 100644
--- a/qiling/arch/arm64_const.py
+++ b/qiling/arch/arm64_const.py
@@ -42,7 +42,8 @@
     "lr": UC_ARM64_REG_LR,
     "cpacr_el1": UC_ARM64_REG_CPACR_EL1,
     "tpidr_el0": UC_ARM64_REG_TPIDR_EL0,
-    "pstate": UC_ARM64_REG_PSTATE
+    "pstate": UC_ARM64_REG_PSTATE,
+    "cpsr": UC_ARM64_REG_PSTATE # alias for `pstate`
 }
 
 reg_map_b = {
@@ -288,3 +289,8 @@
     "v30": UC_ARM64_REG_V30,
     "v31": UC_ARM64_REG_V31
 }
+
+reg_map_fp = {
+    "fpcr": UC_ARM64_REG_FPCR,
+    "fpsr": UC_ARM64_REG_FPSR
+}
diff --git a/qiling/debugger/gdb/xmlregs.py b/qiling/debugger/gdb/xmlregs.py
index 89b68964b..a9e423b14 100644
--- a/qiling/debugger/gdb/xmlregs.py
+++ b/qiling/debugger/gdb/xmlregs.py
@@ -15,7 +15,8 @@
 )
 from qiling.arch.arm64_const import (
     reg_map as arm64_regs,
-    reg_map_v as arm64_regs_v
+    reg_map_v as arm64_regs_v,
+    reg_map_fp as arm64_reg_map_fp
 )
 from qiling.arch.mips_const import (
     reg_map as mips_regs_gpr,
@@ -134,7 +135,7 @@ def __load_regsmap(archtype: QL_ARCH, xmltree: ElementTree.ElementTree) -> Seque
             QL_ARCH.X8664:    dict(**x86_regs_64, **x86_regs_misc, **x86_regs_cr, **x86_regs_st, **x86_regs_xmm, **x86_regs_ymm),
             QL_ARCH.ARM:      dict(**arm_regs, **arm_regs_vfp, **arm_regs_q, **arm_regs_s),
             QL_ARCH.CORTEX_M: arm_regs,
-            QL_ARCH.ARM64:    dict(**arm64_regs, **arm64_regs_v),
+            QL_ARCH.ARM64:    dict(**arm64_regs, **arm64_regs_v, **arm64_reg_map_fp),
             QL_ARCH.MIPS:     dict(**mips_regs_gpr, **mips_regs_fpu)
         }[archtype]
 

From eac5591e356caf126e327326a97afee20bb92813 Mon Sep 17 00:00:00 2001
From: Th3S <46804083+the-soloist@users.noreply.github.com>
Date: Thu, 13 Mar 2025 16:28:33 +0800
Subject: [PATCH 2/2] Remove `tpidr_el0` and `cpsr`

---
 qiling/arch/arm64_const.py | 2 --
 1 file changed, 2 deletions(-)

diff --git a/qiling/arch/arm64_const.py b/qiling/arch/arm64_const.py
index cd10f8026..c254ca37f 100644
--- a/qiling/arch/arm64_const.py
+++ b/qiling/arch/arm64_const.py
@@ -68,9 +68,7 @@
     "pc": UC_ARM64_REG_PC,
     "lr": UC_ARM64_REG_LR,
     "cpacr_el1": UC_ARM64_REG_CPACR_EL1,
-    "tpidr_el0": UC_ARM64_REG_TPIDR_EL0,
     "pstate": UC_ARM64_REG_PSTATE,
-    "cpsr": UC_ARM64_REG_PSTATE,  # alias for `pstate`
 }
 
 reg_map_b = {