From e6a46c6ee7e9c7df10beef0413cc8758d9ff3af3 Mon Sep 17 00:00:00 2001 From: Bjoern Kerler Date: Thu, 12 Nov 2020 22:44:33 +0100 Subject: [PATCH] Gimme more registers --- qiling/arch/arm.py | 11 +++- qiling/arch/arm64.py | 11 +++- qiling/arch/arm64_const.py | 75 ------------------------ qiling/arch/arm_const.py | 29 --------- qiling/arch/mips.py | 14 ++++- qiling/arch/mips_const.py | 52 ---------------- qiling/debugger/gdb/gdb.py | 11 ++-- qiling/extensions/idaplugin/qilingida.py | 17 ++++-- 8 files changed, 51 insertions(+), 169 deletions(-) delete mode 100644 qiling/arch/arm64_const.py delete mode 100644 qiling/arch/arm_const.py delete mode 100644 qiling/arch/mips_const.py diff --git a/qiling/arch/arm.py b/qiling/arch/arm.py index 33ff8ebfa..61cabd882 100644 --- a/qiling/arch/arm.py +++ b/qiling/arch/arm.py @@ -8,11 +8,20 @@ from qiling.const import * from .arch import QlArch -from .arm_const import * + +class ARMConst(): + @property + def reg_map(self): + reg_map={} + for x in dir(arm_const): + if "UC_ARM_REG_" in x: + reg_map[x.replace("UC_ARM_REG_","").lower()]=eval(x) + return reg_map class QlArchARM(QlArch): def __init__(self, ql): super(QlArchARM, self).__init__(ql) + reg_map = ARMConst().reg_map register_mappings = [ reg_map ] diff --git a/qiling/arch/arm64.py b/qiling/arch/arm64.py index 0c10bc7e0..ba7aa9f66 100644 --- a/qiling/arch/arm64.py +++ b/qiling/arch/arm64.py @@ -8,11 +8,20 @@ from qiling.const import * from .arch import QlArch -from .arm64_const import * + +class ARM64Const(): + @property + def reg_map(self): + reg_map={} + for x in dir(unicorn.arm64_const): + if "UC_ARM64_REG_" in x: + reg_map[x.replace("UC_ARM64_REG_","").lower()]=eval(x) + return reg_map class QlArchARM64(QlArch): def __init__(self, ql): super(QlArchARM64, self).__init__(ql) + reg_map=ARM64Const().reg_map register_mappings = [ reg_map diff --git a/qiling/arch/arm64_const.py b/qiling/arch/arm64_const.py deleted file mode 100644 index 79b380d79..000000000 --- a/qiling/arch/arm64_const.py +++ /dev/null @@ -1,75 +0,0 @@ -#!/usr/bin/env python3 -# -# Cross Platform and Multi Architecture Advanced Binary Emulation Framework -# Built on top of Unicorn emulator (www.unicorn-engine.org) - -from unicorn.arm64_const import * - -reg_map = { - "x0": UC_ARM64_REG_X0, - "x1": UC_ARM64_REG_X1, - "x2": UC_ARM64_REG_X2, - "x3": UC_ARM64_REG_X3, - "x4": UC_ARM64_REG_X4, - "x5": UC_ARM64_REG_X5, - "x6": UC_ARM64_REG_X6, - "x7": UC_ARM64_REG_X7, - "x8": UC_ARM64_REG_X8, - "x9": UC_ARM64_REG_X9, - "x10": UC_ARM64_REG_X10, - "x11": UC_ARM64_REG_X11, - "x12": UC_ARM64_REG_X12, - "x13": UC_ARM64_REG_X13, - "x14": UC_ARM64_REG_X14, - "x15": UC_ARM64_REG_X15, - "x16": UC_ARM64_REG_X16, - "x17": UC_ARM64_REG_X17, - "x18": UC_ARM64_REG_X18, - "x19": UC_ARM64_REG_X19, - "x20": UC_ARM64_REG_X20, - "x21": UC_ARM64_REG_X21, - "x22": UC_ARM64_REG_X22, - "x23": UC_ARM64_REG_X23, - "x24": UC_ARM64_REG_X24, - "x25": UC_ARM64_REG_X25, - "x26": UC_ARM64_REG_X26, - "x27": UC_ARM64_REG_X27, - "x28": UC_ARM64_REG_X28, - "x29": UC_ARM64_REG_X29, - "x30": UC_ARM64_REG_X30, - "w0" : UC_ARM64_REG_W0, - "w1" : UC_ARM64_REG_W1, - "w2" : UC_ARM64_REG_W2, - "w3" : UC_ARM64_REG_W3, - "w4" : UC_ARM64_REG_W4, - "w5" : UC_ARM64_REG_W5, - "w6" : UC_ARM64_REG_W6, - "w7" : UC_ARM64_REG_W7, - "w8" : UC_ARM64_REG_W8, - "w9" : UC_ARM64_REG_W9, - "w10" : UC_ARM64_REG_W10, - "w11" : UC_ARM64_REG_W11, - "w12" : UC_ARM64_REG_W12, - "w13" : UC_ARM64_REG_W13, - "w14" : UC_ARM64_REG_W14, - "w15" : UC_ARM64_REG_W15, - "w16" : UC_ARM64_REG_W16, - "w17" : UC_ARM64_REG_W17, - "w18" : UC_ARM64_REG_W18, - "w19" : UC_ARM64_REG_W19, - "w20" : UC_ARM64_REG_W20, - "w21" : UC_ARM64_REG_W21, - "w22" : UC_ARM64_REG_W22, - "w23" : UC_ARM64_REG_W23, - "w24" : UC_ARM64_REG_W24, - "w25" : UC_ARM64_REG_W25, - "w26" : UC_ARM64_REG_W26, - "w27" : UC_ARM64_REG_W27, - "w28" : UC_ARM64_REG_W28, - "w29" : UC_ARM64_REG_W29, - "w30" : UC_ARM64_REG_W30, - "sp": UC_ARM64_REG_SP, - "pc": UC_ARM64_REG_PC, - "cpacr_el1": UC_ARM64_REG_CPACR_EL1, - "tpidr_el0": UC_ARM64_REG_TPIDR_EL0, -} \ No newline at end of file diff --git a/qiling/arch/arm_const.py b/qiling/arch/arm_const.py deleted file mode 100644 index 45d7ebf28..000000000 --- a/qiling/arch/arm_const.py +++ /dev/null @@ -1,29 +0,0 @@ -#!/usr/bin/env python3 -# -# Cross Platform and Multi Architecture Advanced Binary Emulation Framework -# Built on top of Unicorn emulator (www.unicorn-engine.org) - -from unicorn.arm_const import * - -reg_map = { - "r0": UC_ARM_REG_R0, - "r1": UC_ARM_REG_R1, - "r2": UC_ARM_REG_R2, - "r3": UC_ARM_REG_R3, - "r4": UC_ARM_REG_R4, - "r5": UC_ARM_REG_R5, - "r6": UC_ARM_REG_R6, - "r7": UC_ARM_REG_R7, - "r8": UC_ARM_REG_R8, - "r9": UC_ARM_REG_R9, - "r10": UC_ARM_REG_R10, - "r11": UC_ARM_REG_R11, - "r12": UC_ARM_REG_R12, - "sp": UC_ARM_REG_SP, - "lr": UC_ARM_REG_LR, - "pc": UC_ARM_REG_PC, - "cpsr": UC_ARM_REG_CPSR, - "c1_c0_2": UC_ARM_REG_C1_C0_2, - "c13_c0_3": UC_ARM_REG_C13_C0_3, - "fpexc": UC_ARM_REG_FPEXC, -} \ No newline at end of file diff --git a/qiling/arch/mips.py b/qiling/arch/mips.py index 9cdf848d1..7eab6a5c4 100644 --- a/qiling/arch/mips.py +++ b/qiling/arch/mips.py @@ -8,15 +8,23 @@ from qiling.const import * from .arch import QlArch -from .mips_const import * + +class MIPSConst(): + @property + def reg_map(self): + reg_map={} + for x in dir(mips_const): + if "UC_MIPS_REG_" in x: + reg_map[x.replace("UC_MIPS_REG_","").lower()]=eval(x) + return reg_map class QlArchMIPS(QlArch): def __init__(self, ql): super(QlArchMIPS, self).__init__(ql) - + reg_map=MIPSConst().reg_map register_mappings = [ - reg_map, reg_map_afpr128 + reg_map ] for reg_maper in register_mappings: diff --git a/qiling/arch/mips_const.py b/qiling/arch/mips_const.py deleted file mode 100644 index 9bb4445ef..000000000 --- a/qiling/arch/mips_const.py +++ /dev/null @@ -1,52 +0,0 @@ -#!/usr/bin/env python3 -# -# Cross Platform and Multi Architecture Advanced Binary Emulation Framework -# Built on top of Unicorn emulator (www.unicorn-engine.org) - -from unicorn.mips_const import * - -reg_map = { - "zero": UC_MIPS_REG_ZERO, - "at": UC_MIPS_REG_AT, - "v0": UC_MIPS_REG_V0, - "v1": UC_MIPS_REG_V1, - "a0": UC_MIPS_REG_A0, - "a1": UC_MIPS_REG_A1, - "a2": UC_MIPS_REG_A2, - "a3": UC_MIPS_REG_A3, - "t0": UC_MIPS_REG_T0, - "t1": UC_MIPS_REG_T1, - "t2": UC_MIPS_REG_T2, - "t3": UC_MIPS_REG_T3, - "t4": UC_MIPS_REG_T4, - "t5": UC_MIPS_REG_T5, - "t6": UC_MIPS_REG_T6, - "t7": UC_MIPS_REG_T7, - "s0": UC_MIPS_REG_S0, - "s1": UC_MIPS_REG_S1, - "s2": UC_MIPS_REG_S2, - "s3": UC_MIPS_REG_S3, - "s4": UC_MIPS_REG_S4, - "s5": UC_MIPS_REG_S5, - "s6": UC_MIPS_REG_S6, - "s7": UC_MIPS_REG_S7, - "t8": UC_MIPS_REG_T8, - "t9": UC_MIPS_REG_T9, - "k0": UC_MIPS_REG_K0, - "k1": UC_MIPS_REG_K1, - "gp": UC_MIPS_REG_GP, - "sp": UC_MIPS_REG_SP, - "s8": UC_MIPS_REG_S8, - "ra": UC_MIPS_REG_RA, - "status": UC_MIPS_REG_INVALID, - "lo": UC_MIPS_REG_LO, - "hi": UC_MIPS_REG_HI, - "badvaddr": UC_MIPS_REG_INVALID, - "cause":UC_MIPS_REG_INVALID, - "pc": UC_MIPS_REG_PC, -} - -reg_map_afpr128 = { - "cp0_config3" : UC_MIPS_REG_CP0_CONFIG3, - "cp0_userlocal": UC_MIPS_REG_CP0_USERLOCAL, -} \ No newline at end of file diff --git a/qiling/debugger/gdb/gdb.py b/qiling/debugger/gdb/gdb.py index 0a65b6023..7d2b9f084 100644 --- a/qiling/debugger/gdb/gdb.py +++ b/qiling/debugger/gdb/gdb.py @@ -20,9 +20,12 @@ from qiling.arch.x86_const import reg_map_64 as x86_reg_map_64 from qiling.arch.x86_const import reg_map_misc as x86_reg_map_misc from qiling.arch.x86_const import reg_map_st as x86_reg_map_st -from qiling.arch.arm_const import reg_map as arm_reg_map -from qiling.arch.arm64_const import reg_map as arm64_reg_map -from qiling.arch.mips_const import reg_map as mips_reg_map +from qiling.arch.arm import ARMConst +from qiling.arch.arm64 import ARM64Const +from qiling.arch.mips import MIPSConst +arm64_reg_map=ARM64Const().reg_map +arm_reg_map=ARMConst().reg_map +mips_reg_map=MIPSConst().reg_map GDB_SIGNAL_INT = 2 GDB_SIGNAL_SEGV = 11 @@ -85,7 +88,7 @@ def __init__(self, ql, ip, port): self.gdb.bp_insert(self.entry_point) - + #Setup register tables, order of tables is important self.tables = { diff --git a/qiling/extensions/idaplugin/qilingida.py b/qiling/extensions/idaplugin/qilingida.py index 591a641c2..3d0a0a502 100644 --- a/qiling/extensions/idaplugin/qilingida.py +++ b/qiling/extensions/idaplugin/qilingida.py @@ -16,13 +16,18 @@ # Qiling from qiling import * from qiling.const import * +from qiling.arch.x86_const import reg_map_16 as x86_reg_map_16 from qiling.arch.x86_const import reg_map_32 as x86_reg_map_32 from qiling.arch.x86_const import reg_map_64 as x86_reg_map_64 from qiling.arch.x86_const import reg_map_misc as x86_reg_map_misc from qiling.arch.x86_const import reg_map_st as x86_reg_map_st -from qiling.arch.arm_const import reg_map as arm_reg_map -from qiling.arch.arm64_const import reg_map as arm64_reg_map -from qiling.arch.mips_const import reg_map as mips_reg_map +from qiling.arch.arm import ARMConst +from qiling.arch.arm64 import ARM64Const +from qiling.arch.mips import MIPSConst +arm_reg_map=ARMConst().reg_map +arm64_reg_map=ARM64Const().reg_map +mips_reg_map=MIPSConst().reg_map + from qiling.utils import ql_get_arch_bits from qiling import __version__ as QLVERSION from qiling.os.filestruct import ql_file @@ -55,6 +60,7 @@ from PyQt5 import QtCore, QtWidgets from PyQt5.QtWidgets import (QPushButton, QHBoxLayout) + QilingHomePage = 'https://www.qiling.io' QilingStableVersionURL = 'https://raw.githubusercontent.com/qilingframework/qiling/master/qiling/__version__.py' logging.basicConfig(level=logging.INFO, format='[%(levelname)s][%(module)s:%(lineno)d] %(message)s') @@ -819,6 +825,7 @@ def update(self, ctx): @staticmethod def get_reg_map(ql:Qiling): tables = { + QL_ARCH.A8086: list({**x86_reg_map_16, **x86_reg_map_misc}.keys()), QL_ARCH.X86 : list({**x86_reg_map_32, **x86_reg_map_misc, **x86_reg_map_st}.keys()), QL_ARCH.X8664 : list({**x86_reg_map_64, **x86_reg_map_misc, **x86_reg_map_st}.keys()), QL_ARCH.ARM : list({**arm_reg_map}.keys()), @@ -826,7 +833,9 @@ def get_reg_map(ql:Qiling): QL_ARCH.MIPS : list({**mips_reg_map}.keys()), } - if ql.archtype == QL_ARCH.X86: + if ql.archtype == QL_ARCH.A8086: + return tables[QL_ARCH.A8086] + elif ql.archtype == QL_ARCH.X86: return tables[QL_ARCH.X86] elif ql.archtype == QL_ARCH.X8664: return tables[QL_ARCH.X8664]