diff --git a/aarch32-cpu/Cargo.toml b/aarch32-cpu/Cargo.toml
index f519306..76903a9 100644
--- a/aarch32-cpu/Cargo.toml
+++ b/aarch32-cpu/Cargo.toml
@@ -51,4 +51,11 @@ serde = ["dep:serde", "arbitrary-int/serde"]
 check-asm = []
 
 [package.metadata.docs.rs]
-targets = ["armv7r-none-eabihf", "armv7r-none-eabi", "armv7a-none-eabihf"]
+# This is a list of supported Tier 2 targets, as of latest stable
+targets = [
+    "armv7r-none-eabihf",
+    "armv7r-none-eabi",
+    "armv7a-none-eabihf",
+    "armv7a-none-eabi",
+    "armv8r-none-eabihf"
+]
diff --git a/aarch32-rt/Cargo.toml b/aarch32-rt/Cargo.toml
index adc057f..8e9f25a 100644
--- a/aarch32-rt/Cargo.toml
+++ b/aarch32-rt/Cargo.toml
@@ -40,4 +40,11 @@ fpu-d32 = []
 arm-targets = { version = "0.4.0", path = "../arm-targets" }
 
 [package.metadata.docs.rs]
-targets = ["armv7r-none-eabihf", "armv7r-none-eabihf", "armv7a-none-eabi"]
+# This is a list of supported Tier 2 targets, as of latest stable
+targets = [
+    "armv7r-none-eabihf",
+    "armv7r-none-eabi",
+    "armv7a-none-eabihf",
+    "armv7a-none-eabi",
+    "armv8r-none-eabihf"
+]