From 35341ba98d7a69072fa12f8b9bd3f889447bfa3a Mon Sep 17 00:00:00 2001 From: "M. J. Fromberger" Date: Mon, 27 Jan 2020 13:18:03 -0800 Subject: [PATCH 1/4] shared: add file extension mappings for Pascal --- shared/src/languages.ts | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/shared/src/languages.ts b/shared/src/languages.ts index 88ae27371247..05f246c15814 100644 --- a/shared/src/languages.ts +++ b/shared/src/languages.ts @@ -277,6 +277,11 @@ function getModeFromExtension(ext: string): string | undefined { case 're': // reason has the same language server as ocaml return 'ocaml' + // Pascal + case 'p': + case 'pas': + return 'pascal' + // Perl case 'pl': case 'al': From 7286301809281982453da26601924d30a66d1b80 Mon Sep 17 00:00:00 2001 From: "M. J. Fromberger" Date: Mon, 27 Jan 2020 13:20:31 -0800 Subject: [PATCH 2/4] shared: include SystemVerilog file extensions for Verilog --- shared/src/languages.ts | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/shared/src/languages.ts b/shared/src/languages.ts index 05f246c15814..9ceac500aa26 100644 --- a/shared/src/languages.ts +++ b/shared/src/languages.ts @@ -414,9 +414,12 @@ function getModeFromExtension(ext: string): string | undefined { case 'vbs': return 'vbscrip' - // Verilog + // Verilog, including SystemVerilog case 'v': case 'veo': + case 'sv': + case 'svh': + case 'svi': return 'verilog' // VIM From 5c09467e61f57901e687d67ff966e02356642a4f Mon Sep 17 00:00:00 2001 From: "M. J. Fromberger" Date: Mon, 27 Jan 2020 13:20:55 -0800 Subject: [PATCH 3/4] shared: add file extension mappings for VHDL --- shared/src/languages.ts | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/shared/src/languages.ts b/shared/src/languages.ts index 9ceac500aa26..b4ccfc18fc2f 100644 --- a/shared/src/languages.ts +++ b/shared/src/languages.ts @@ -280,6 +280,7 @@ function getModeFromExtension(ext: string): string | undefined { // Pascal case 'p': case 'pas': + case 'pp': return 'pascal' // Perl @@ -422,6 +423,11 @@ function getModeFromExtension(ext: string): string | undefined { case 'svi': return 'verilog' + // VHDL + case 'vhd': + case 'vhdl': + return 'vhdl' + // VIM case 'vim': return 'vim' From 17638d33887a55275f096775e039c8613437b639 Mon Sep 17 00:00:00 2001 From: "M. J. Fromberger" Date: Mon, 27 Jan 2020 14:46:27 -0800 Subject: [PATCH 4/4] ctags: add Pascal, SystemVerilog, and VHDL --- cmd/symbols/internal/pkg/ctags/parser.go | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/cmd/symbols/internal/pkg/ctags/parser.go b/cmd/symbols/internal/pkg/ctags/parser.go index ef7b52392aef..dc614fd4c4e9 100644 --- a/cmd/symbols/internal/pkg/ctags/parser.go +++ b/cmd/symbols/internal/pkg/ctags/parser.go @@ -68,7 +68,7 @@ func NewParser(ctagsCommand string) (Parser, error) { // } cmd := exec.Command(ctagsCommand, "--_interactive="+opt, "--fields=*", - "--languages=Basic,C,C#,C++,Clojure,Cobol,CSS,CUDA,D,Elixir,elm,Erlang,Go,haskell,Java,JavaScript,kotlin,Lisp,Lua,MatLab,ObjectiveC,OCaml,Perl,Perl6,PHP,Protobuf,Python,R,Ruby,Rust,scala,Scheme,Sh,swift,Tcl,typescript,tsx,Verilog,Vim", + "--languages=Basic,C,C#,C++,Clojure,Cobol,CSS,CUDA,D,Elixir,elm,Erlang,Go,haskell,Java,JavaScript,kotlin,Lisp,Lua,MatLab,ObjectiveC,OCaml,Pascal,Perl,Perl6,PHP,Protobuf,Python,R,Ruby,Rust,scala,Scheme,Sh,swift,SystemVerilog,Tcl,typescript,tsx,Verilog,VHDL,Vim", "--map-CSS=+.scss", "--map-CSS=+.less", "--map-CSS=+.sass", ) in, err := cmd.StdinPipe()