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lgirdwoodlgirdwood
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Merge pull request #623 from lbetlej/move_stack_to_pg_sram
Power up only subset of HP SRAM banks on FW init (CannonLake)
2 parents 2521751 + bb26636 commit 443233c

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3 files changed

+80
-13
lines changed

3 files changed

+80
-13
lines changed

‎src/arch/xtensa/boot_loader.c‎

Lines changed: 61 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -35,6 +35,7 @@
3535
#include <uapi/user/manifest.h>
3636
#include <platform/platform.h>
3737
#include <platform/memory.h>
38+
#include <platform/platcfg.h>
3839

3940
#if defined CONFIG_SUECREEK
4041
#define MANIFEST_BASE BOOT_LDR_MANIFEST_BASE
@@ -133,12 +134,71 @@ static int32_t hp_sram_init(void)
133134
{
134135
int delay_count = 256;
135136
uint32_t status;
137+
#if defined(CONFIG_CANNONLAKE)
138+
uint32_t ebb_in_use;
139+
uint32_t ebb_mask0, ebb_mask1, ebb_avail_mask0, ebb_avail_mask1;
140+
#endif
136141

137142
shim_write(SHIM_LDOCTL, SHIM_LDOCTL_HPSRAM_LDO_ON);
138143

139144
/* add some delay before touch power register */
140145
idelay(delay_count);
141146

147+
#if defined(CONFIG_CANNONLAKE)
148+
/* calculate total number of used SRAM banks (EBB)
149+
* to power up only ncecesary banks
150+
*/
151+
ebb_in_use = ((SOF_MEMORY_SIZE % SRAM_BANK_SIZE) == 0) ?
152+
(SOF_MEMORY_SIZE / SRAM_BANK_SIZE) :
153+
(SOF_MEMORY_SIZE / SRAM_BANK_SIZE) + 1;
154+
155+
/* bit masks reflect total number of available EBB (banks) in each
156+
* segment; current implementation supports 2 segments 0,1
157+
*/
158+
if (PLATFORM_HPSRAM_EBB_COUNT > EBB_SEGMENT_SIZE) {
159+
ebb_avail_mask0 = (uint32_t)MASK(EBB_SEGMENT_SIZE - 1, 0);
160+
ebb_avail_mask1 = (uint32_t)MASK(PLATFORM_HPSRAM_EBB_COUNT -
161+
EBB_SEGMENT_SIZE - 1, 0);
162+
} else{
163+
ebb_avail_mask0 = (uint32_t)MASK(PLATFORM_HPSRAM_EBB_COUNT - 1,
164+
0);
165+
ebb_avail_mask1 = 0;
166+
}
167+
168+
/* bit masks of banks that have to be powered up in each segment */
169+
if (ebb_in_use > EBB_SEGMENT_SIZE) {
170+
ebb_mask0 = (uint32_t)MASK(EBB_SEGMENT_SIZE - 1, 0);
171+
ebb_mask1 = (uint32_t)MASK(ebb_in_use - EBB_SEGMENT_SIZE - 1,
172+
0);
173+
} else{
174+
/* assumption that ebb_in_use is > 0 */
175+
ebb_mask0 = (uint32_t)MASK(ebb_in_use - 1, 0);
176+
ebb_mask1 = 0;
177+
}
178+
179+
/* HSPGCTL, HSRMCTL use reverse logic - 0 means EBB is power gated */
180+
io_reg_write(HSPGCTL0, (~ebb_mask0) & ebb_avail_mask0);
181+
io_reg_write(HSRMCTL0, (~ebb_mask0) & ebb_avail_mask0);
182+
io_reg_write(HSPGCTL1, (~ebb_mask1) & ebb_avail_mask1);
183+
io_reg_write(HSRMCTL1, (~ebb_mask1) & ebb_avail_mask1);
184+
185+
/* query the power status of first part of HP memory */
186+
/* to check whether it has been powered up. A few */
187+
/* cycles are needed for it to be powered up */
188+
status = io_reg_read(HSPGISTS0);
189+
while (status != ((~ebb_mask0) & ebb_avail_mask0)) {
190+
idelay(delay_count);
191+
status = io_reg_read(HSPGISTS0);
192+
}
193+
/* query the power status of second part of HP memory */
194+
/* and do as above code */
195+
196+
status = io_reg_read(HSPGISTS1);
197+
while (status != ((~ebb_mask1) & ebb_avail_mask1)) {
198+
idelay(delay_count);
199+
status = io_reg_read(HSPGISTS1);
200+
}
201+
#else
142202
/* now all the memory bank has been powered up */
143203
io_reg_write(HSPGCTL0, 0);
144204
io_reg_write(HSRMCTL0, 0);
@@ -161,7 +221,7 @@ static int32_t hp_sram_init(void)
161221
idelay(delay_count);
162222
status = io_reg_read(HSPGISTS1);
163223
}
164-
224+
#endif
165225
/* add some delay before touch power register */
166226
idelay(delay_count);
167227

‎src/platform/cannonlake/include/platform/memory.h‎

Lines changed: 14 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -163,9 +163,9 @@
163163
* +---------------------+----------------+-----------------------------------+
164164
* | HEAP_BUFFER_BASE | Module Buffers | HEAP_BUFFER_SIZE |
165165
* +---------------------+----------------+-----------------------------------+
166-
* | SOF_STACK_END | Stack | SOF_STACK_SIZE |
166+
* | SOF_STACK_END | Stack | SOF_STACK_SIZE |
167167
* +---------------------+----------------+-----------------------------------+
168-
* | SOF_STACK_BASE | | |
168+
* | SOF_STACK_BASE | | |
169169
* +---------------------+----------------+-----------------------------------+
170170
*/
171171

@@ -279,34 +279,38 @@
279279
/* Stack configuration */
280280
#define SOF_STACK_SIZE ARCH_STACK_SIZE
281281
#define SOF_STACK_TOTAL_SIZE ARCH_STACK_TOTAL_SIZE
282-
#define SOF_STACK_BASE (HP_SRAM_BASE + HP_SRAM_SIZE)
283-
#define SOF_STACK_END (SOF_STACK_BASE - SOF_STACK_TOTAL_SIZE)
282+
/* SOF_STACK_OFFSET defines how much memory can be power gated */
283+
#define SOF_STACK_OFFSET 0x150000
284+
/* SOF_STACK_BASE is moved from end of physical memory by offset */
285+
#define SOF_STACK_BASE (HP_SRAM_BASE + HP_SRAM_SIZE - SOF_STACK_OFFSET)
286+
#define SOF_STACK_END (SOF_STACK_BASE - SOF_STACK_TOTAL_SIZE)
284287

285288
#define HEAP_BUFFER_BASE (HEAP_RUNTIME_BASE + HEAP_RUNTIME_SIZE)
286289
#define HEAP_BUFFER_SIZE \
287290
(SOF_STACK_END - HEAP_BUFFER_BASE)
288291
#define HEAP_BUFFER_BLOCK_SIZE 0x180
289292
#define HEAP_BUFFER_COUNT (HEAP_BUFFER_SIZE / HEAP_BUFFER_BLOCK_SIZE)
290293

294+
#define SOF_MEMORY_SIZE (SOF_STACK_BASE - HP_SRAM_BASE)
291295
/*
292296
* The LP SRAM Heap and Stack on Cannonlake are organised like this :-
293297
*
294298
* +--------------------------------------------------------------------------+
295299
* | Offset | Region | Size |
296300
* +---------------------+----------------+-----------------------------------+
297-
* | LP_SRAM_BASE | RO Data | SOF_LP_DATA_SIZE |
301+
* | LP_SRAM_BASE | RO Data | SOF_LP_DATA_SIZE |
298302
* | | Data | |
299303
* | | BSS | |
300304
* +---------------------+----------------+-----------------------------------+
301-
* | HEAP_LP_SYSTEM_BASE | System Heap | HEAP_LP_SYSTEM_SIZE |
305+
* | HEAP_LP_SYSTEM_BASE | System Heap | HEAP_LP_SYSTEM_SIZE |
302306
* +---------------------+----------------+-----------------------------------+
303-
* | HEAP_LP_RUNTIME_BASE| Runtime Heap | HEAP_LP_RUNTIME_SIZE |
307+
* | HEAP_LP_RUNTIME_BASE| Runtime Heap | HEAP_LP_RUNTIME_SIZE |
304308
* +---------------------+----------------+-----------------------------------+
305-
* | HEAP_LP_BUFFER_BASE | Module Buffers | HEAP_LP_BUFFER_SIZE |
309+
* | HEAP_LP_BUFFER_BASE | Module Buffers | HEAP_LP_BUFFER_SIZE |
306310
* +---------------------+----------------+-----------------------------------+
307-
* | SOF_LP_STACK_END | Stack | SOF_LP_STACK_SIZE |
311+
* | SOF_LP_STACK_END | Stack | SOF_LP_STACK_SIZE |
308312
* +---------------------+----------------+-----------------------------------+
309-
* | SOF_STACK_BASE | | |
313+
* | SOF_STACK_BASE | | |
310314
* +---------------------+----------------+-----------------------------------+
311315
*/
312316

@@ -367,8 +371,6 @@
367371
#define SOF_MEM_RESET_LIT_SIZE 0x8
368372
#define SOF_MEM_VECBASE_LIT_SIZE 0x178
369373

370-
#define SOF_MEM_RO_SIZE 0x8
371-
372374
/* boot loader in IMR */
373375
#define IMR_BOOT_LDR_MANIFEST_BASE 0xB0032000
374376
#define IMR_BOOT_LDR_MANIFEST_SIZE 0x6000

‎src/platform/cannonlake/include/platform/platcfg.h‎

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -43,4 +43,9 @@
4343

4444
#define PLATFORM_MASTER_CORE_ID 0
4545

46+
//TODO: move cAVS memory specific definitions to cavs/memory driver
47+
#define SRAM_BANK_SIZE 0x10000
48+
49+
#define EBB_SEGMENT_SIZE 32
50+
4651
#endif

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