pm_runtime: prepare secondary cores for power down in d0->d0ix flow

Primary core during going to D0i3 state disables all another cores
in platform_pg_int_handler() function. Before it secondary cores
should be prepared (disable interrupts, perform writeback) in order
to make proper restore flow after D0i3->D0 transition.

This commit adds cpu_secondary_cores_prepare_d0ix() function in
ipc_pm_gate() handler, which sends idc to secondary cores
with information that they should perform preparation for power down
in the next platform_wait_for_interrupt() invocation. In
platform_wait_for_interrupt() there is cpu_power_down_core()
invocation with CPU_POWER_DOWN_MEMORY_ON (performs writeback/invalidate,
disables interrupts), when proper flag is set.

Signed-off-by: Bartosz Kokoszko <bartoszx.kokoszko@linux.intel.com>

Author: bkokoszx

src/arch/host/include/arch/lib/cpu.h

@@ -39,6 +39,11 @@ static inline int arch_cpu_restore_secondary_cores(void)
 	return 0;
 }
 
+static inline int arch_cpu_secondary_cores_prepare_d0ix(void)
+{
+	return 0;
+}
+
 static inline void cpu_write_threadptr(int threadptr)
 {
 }

src/arch/xtensa/include/arch/lib/cpu.h

@@ -11,10 +11,17 @@
 #define __ARCH_LIB_CPU_H__
 
 #include <xtensa/config/core-isa.h>
+#include <stdint.h>
 
 #if CONFIG_MULTICORE
 
-void cpu_power_down_core(void);
+/** \brief CPU power down available flags */
+#define CPU_POWER_DOWN_MEMORY_ON	BIT(0) /**< Power down core with memory
+						 *  enabled (required in d0ix
+						 *  flow)
+						 */
+
+void cpu_power_down_core(uint32_t flags);
 
 void cpu_alloc_core_context(int id);
 
@@ -28,6 +35,8 @@ int arch_cpu_enabled_cores(void);
 
 int arch_cpu_restore_secondary_cores(void);
 
+int arch_cpu_secondary_cores_prepare_d0ix(void);
+
 #else
 
 static inline int arch_cpu_enable_core(int id) { return 0; }
@@ -40,6 +49,8 @@ static inline int arch_cpu_enabled_cores(void) { return 1; }
 
 static inline int arch_cpu_restore_secondary_cores(void) {return 0; }
 
+static inline int arch_cpu_secondary_cores_prepare_d0ix(void) {return 0; }
+
 #endif
 
 static inline int arch_cpu_get_id(void)

src/arch/xtensa/lib/cpu.c

@@ -160,25 +160,44 @@ void cpu_alloc_core_context(int core)
 	dcache_writeback_region(sof_get(), sizeof(*sof_get()));
 }
 
-void cpu_power_down_core(void)
+void cpu_power_down_core(uint32_t flags)
 {
 	arch_interrupt_global_disable();
 
-	idc_free(0);
+	/* Power down with memory on is performed by secondary cores during
+	 * d0 -> d0ix before they are disabled by primary core.
+	 */
+	if (flags & CPU_POWER_DOWN_MEMORY_ON) {
+		/* disable idc interrupts */
+		idc_free(IDC_FREE_IRQ_ONLY);
+
+		/* disable scheduler interrupts */
+		schedule_free(SOF_SCHEDULER_FREE_IRQ_ONLY);
+
+		/* data writeback/invalidate */
+		dcache_writeback_invalidate_all();
 
-	schedule_free(0);
+		/* after writeback/invalidate secondary core is prepared for
+		 * powered off - prepare_d0ix_core_mask flag can be disabled
+		 */
+		platform_pm_runtime_prepare_d0ix_dis(cpu_get_id());
+	} else {
+		idc_free(0);
 
-	free_system_notify();
+		schedule_free(0);
 
-	/* free entire sys heap, an instance dedicated for this core */
-	free_heap(SOF_MEM_ZONE_SYS);
+		free_system_notify();
 
-	dcache_writeback_invalidate_all();
+		/* free entire sys heap, an instance dedicated for this core */
+		free_heap(SOF_MEM_ZONE_SYS);
 
-	/* Turn off stack memory for core */
-	pm_runtime_put(CORE_MEMORY_POW, cpu_get_id());
+		dcache_writeback_invalidate_all();
 
-	pm_runtime_put(PM_RUNTIME_DSP, PWRD_BY_TPLG | cpu_get_id());
+		/* Turn off stack memory for core */
+		pm_runtime_put(CORE_MEMORY_POW, cpu_get_id());
+
+		pm_runtime_put(PM_RUNTIME_DSP, PWRD_BY_TPLG | cpu_get_id());
+	}
 
 	trace_point(0);
 
@@ -214,3 +233,25 @@ int arch_cpu_restore_secondary_cores(void)
 
 	return 0;
 }
+
+int arch_cpu_secondary_cores_prepare_d0ix(void)
+{
+	struct idc_msg prepare_msg = { IDC_MSG_PREPARE_D0ix,
+				       IDC_MSG_PREPARE_D0ix_EXT };
+	int ret, id;
+
+	for (id = 0; id < CONFIG_CORE_COUNT; id++) {
+		if (arch_cpu_is_core_enabled(id) && id != PLATFORM_PRIMARY_CORE_ID) {
+			prepare_msg.core = id;
+
+			/* send IDC prepare message to all enabled secondary
+			 * cores.
+			 */
+			ret = idc_send_msg(&prepare_msg, IDC_BLOCKING);
+			if (ret < 0)
+				return ret;
+		}
+	}
+
+	return 0;
+}

src/idc/idc.c

@@ -17,6 +17,7 @@
 #include <sof/lib/cpu.h>
 #include <sof/lib/memory.h>
 #include <sof/lib/notifier.h>
+#include <sof/lib/pm_runtime.h>
 #include <sof/lib/uuid.h>
 #include <sof/platform.h>
 #include <arch/lib/wait.h>
@@ -268,6 +269,16 @@ static int idc_reset(uint32_t comp_id)
 	return ret;
 }
 
+static void idc_prepare_d0ix(void)
+{
+	/* set prepare_d0ix flag, which indicates that in the next
+	 * platform_wait_for_interrupt invocation(), core should get ready for
+	 * d0ix power down - it is required by D0->D0ix flow, when primary
+	 * core disables all secondary cores.
+	 */
+	platform_pm_runtime_prepare_d0ix_en(cpu_get_id());
+}
+
 /**
  * \brief Executes IDC message based on type.
  * \param[in,out] msg Pointer to IDC message.
@@ -279,7 +290,7 @@ void idc_cmd(struct idc_msg *msg)
 
 	switch (type) {
 	case iTS(IDC_MSG_POWER_DOWN):
-		cpu_power_down_core();
+		cpu_power_down_core(0);
 		break;
 	case iTS(IDC_MSG_NOTIFY):
 		notifier_notify_remote();
@@ -299,6 +310,9 @@ void idc_cmd(struct idc_msg *msg)
 	case iTS(IDC_MSG_RESET):
 		ret = idc_reset(msg->extension);
 		break;
+	case iTS(IDC_MSG_PREPARE_D0ix):
+		idc_prepare_d0ix();
+		break;
 	default:
 		tr_err(&idc_tr, "idc_cmd(): invalid msg->header = %u",
 		       msg->header);

src/include/sof/drivers/idc.h

@@ -88,6 +88,10 @@
 #define IDC_MSG_RESET		IDC_TYPE(0x8)
 #define IDC_MSG_RESET_EXT(x)	IDC_EXTENSION(x)
 
+/** \brief IDC prepare D0ix message. */
+#define IDC_MSG_PREPARE_D0ix		IDC_TYPE(0x9)
+#define IDC_MSG_PREPARE_D0ix_EXT	IDC_EXTENSION(0x0)
+
 /** \brief Decodes IDC message type. */
 #define iTS(x)	(((x) >> IDC_TYPE_SHIFT) & IDC_TYPE_MASK)
 

src/include/sof/lib/cpu.h

@@ -61,6 +61,11 @@ static inline int cpu_restore_secondary_cores(void)
 	return arch_cpu_restore_secondary_cores();
 }
 
+static inline int cpu_secondary_cores_prepare_d0ix(void)
+{
+	return arch_cpu_secondary_cores_prepare_d0ix();
+}
+
 #endif
 
 #endif /* __SOF_LIB_CPU_H__ */

src/ipc/ipc3/handler.c

@@ -707,6 +707,15 @@ static int ipc_pm_gate(uint32_t header)
 		cpu_restore_secondary_cores();
 #endif
 	} else {
+		/* before we enable pm runtime and perform D0->D0ix flow
+		 * (primary core powers off secondary cores in
+		 * platform_pg_int_handler) we have to prepare all secondary
+		 * cores data for powering off (disable interrupt, perform
+		 * cache writeback).
+		 */
+#if (CONFIG_CAVS_LPS)
+		cpu_secondary_cores_prepare_d0ix();
+#endif
 		pm_runtime_enable(PM_RUNTIME_DSP, PLATFORM_PRIMARY_CORE_ID);
 	}
 

src/platform/apollolake/include/platform/lib/pm_runtime.h

@@ -48,6 +48,12 @@ void platform_pm_runtime_enable(uint32_t context, uint32_t index);
 
 void platform_pm_runtime_disable(uint32_t context, uint32_t index);
 
+void platform_pm_runtime_prepare_d0ix_en(uint32_t index);
+
+void platform_pm_runtime_prepare_d0ix_dis(uint32_t index);
+
+int platform_pm_runtime_prepare_d0ix_is_req(uint32_t index);
+
 bool platform_pm_runtime_is_active(uint32_t context, uint32_t index);
 
 /**

src/platform/cannonlake/include/platform/lib/pm_runtime.h

@@ -47,6 +47,12 @@ void platform_pm_runtime_enable(uint32_t context, uint32_t index);
 
 void platform_pm_runtime_disable(uint32_t context, uint32_t index);
 
+void platform_pm_runtime_prepare_d0ix_en(uint32_t index);
+
+void platform_pm_runtime_prepare_d0ix_dis(uint32_t index);
+
+int platform_pm_runtime_prepare_d0ix_is_req(uint32_t index);
+
 bool platform_pm_runtime_is_active(uint32_t context, uint32_t index);
 
 /**

src/platform/icelake/include/platform/lib/pm_runtime.h

@@ -47,6 +47,12 @@ void platform_pm_runtime_enable(uint32_t context, uint32_t index);
 
 void platform_pm_runtime_disable(uint32_t context, uint32_t index);
 
+void platform_pm_runtime_prepare_d0ix_en(uint32_t index);
+
+void platform_pm_runtime_prepare_d0ix_dis(uint32_t index);
+
+int platform_pm_runtime_prepare_d0ix_is_req(uint32_t index);
+
 bool platform_pm_runtime_is_active(uint32_t context, uint32_t index);
 
 /**