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Merge pull request #589 from lbetlej/ldo_ctrl_on_D3_entry
LDO control on D0->D3 transtion for CannonLake
2 parents 557a82d + 03fb10f commit 98f0b36

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7 files changed

+185
-12
lines changed

7 files changed

+185
-12
lines changed

‎src/arch/xtensa/boot_loader.c‎

Lines changed: 11 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -134,7 +134,12 @@ static int32_t hp_sram_init(void)
134134
int delay_count = 256;
135135
uint32_t status;
136136

137+
#if defined(CONFIG_CANNONLAKE)
138+
shim_write(SHIM_LDOCTL, SHIM_LDOCTL_HPSRAM_LDO_ON);
139+
#else
140+
//TODO: clean up sequence same as for CANNONLAKE
137141
shim_write(SHIM_LDOCTL, SHIM_HPMEM_POWER_ON);
142+
#endif
138143

139144
/* add some delay before touch power register */
140145
idelay(delay_count);
@@ -164,7 +169,13 @@ static int32_t hp_sram_init(void)
164169

165170
/* add some delay before touch power register */
166171
idelay(delay_count);
172+
173+
#if defined(CONFIG_CANNONLAKE)
174+
shim_write(SHIM_LDOCTL, SHIM_LDOCTL_HPSRAM_LDO_BYPASS);
175+
#else
176+
//TODO: clean up sequence same as for CANNONLAKE
167177
shim_write(SHIM_LDOCTL, SHIM_LPMEM_POWER_BYPASS);
178+
#endif
168179

169180
return 0;
170181
}

‎src/platform/cannonlake/Makefile.am‎

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -21,7 +21,8 @@ libplatform_la_CCASFLAGS = \
2121
$(ARCH_INCDIR) \
2222
$(ASFLAGS) \
2323
$(ARCH_ASFLAGS) \
24-
$(PLATFORM_INCDIR)
24+
$(PLATFORM_INCDIR) \
25+
$(SOF_INCDIR)
2526

2627
noinst_PROGRAMS = module boot_module
2728

‎src/platform/cannonlake/include/platform/Makefile.am‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -12,4 +12,5 @@ noinst_HEADERS = \
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shim.h \
1313
timer.h \
1414
asm_memory_management.h \
15+
asm_ldo_management.h \
1516
power_down.h

‎src/platform/cannonlake/include/platform/asm_ldo_management.h‎

Lines changed: 131 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,131 @@
1+
/*
2+
* Copyright (c) 2018, Intel Corporation
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* All rights reserved.
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*
5+
* Redistribution and use in source and binary forms, with or without
6+
* modification, are permitted provided that the following conditions are met:
7+
* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
9+
* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
11+
* documentation and/or other materials provided with the distribution.
12+
* * Neither the name of the Intel Corporation nor the
13+
* names of its contributors may be used to endorse or promote products
14+
* derived from this software without specific prior written permission.
15+
*
16+
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18+
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19+
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
20+
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
21+
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
22+
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
23+
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
24+
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
25+
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
26+
* POSSIBILITY OF SUCH DAMAGE.
27+
*
28+
* Author: Lech Betlej <lech.betlej@linux.intel.com>
29+
*/
30+
31+
/**
32+
* \file platform/apollolake/include/platform/asm_ldo_management.h
33+
* \brief Macros for controlling LDO state specific for cAVS 1.5
34+
* \author Lech Betlej <lech.betlej@linux.intel.com>
35+
*/
36+
#ifndef ASM_LDO_MANAGEMENT_H
37+
#define ASM_LDO_MANAGEMENT_H
38+
39+
#ifndef ASSEMBLY
40+
#warning "Header can only be used by assembly sources."
41+
#endif
42+
43+
#include <platform/shim.h>
44+
45+
.macro m_cavs_set_ldo_state state, ax
46+
movi \ax, (SHIM_BASE + SHIM_LDOCTL)
47+
s32i \state, \ax, 0
48+
memw
49+
// wait loop > 300ns (min 100ns required)
50+
movi \ax, 128
51+
1 :
52+
addi \ax, \ax, -1
53+
nop
54+
bnez \ax, 1b
55+
.endm
56+
57+
.macro m_cavs_set_hpldo_state state, ax, ay
58+
movi \ax, (SHIM_BASE + SHIM_LDOCTL)
59+
l32i \ay, \ax, 0
60+
61+
movi \ax, ~(SHIM_LDOCTL_HPSRAM_MASK)
62+
and \ay, \ax, \ay
63+
or \state, \ay, \state
64+
65+
m_cavs_set_ldo_state \state, \ax
66+
.endm
67+
68+
.macro m_cavs_set_lpldo_state state, ax, ay
69+
movi \ax, (SHIM_BASE + SHIM_LDOCTL)
70+
l32i \ay, \ax, 0
71+
// LP SRAM mask
72+
movi \ax, ~(SHIM_LDOCTL_LPSRAM_MASK)
73+
and \ay, \ax, \ay
74+
or \state, \ay, \state
75+
76+
m_cavs_set_ldo_state \state, \ax
77+
.endm
78+
79+
.macro m_cavs_set_ldo_on_state ax, ay, az
80+
movi \ay, (SHIM_BASE + SHIM_LDOCTL)
81+
l32i \az, \ay, 0
82+
83+
movi \ax, ~(SHIM_LDOCTL_HPSRAM_MASK | SHIM_LDOCTL_LPSRAM_MASK)
84+
and \az, \ax, \az
85+
movi \ax, (SHIM_LDOCTL_HPSRAM_LDO_ON | SHIM_LDOCTL_LPSRAM_LDO_ON)
86+
or \ax, \az, \ax
87+
88+
m_cavs_set_ldo_state \ax, \ay
89+
.endm
90+
91+
.macro m_cavs_set_ldo_off_state ax, ay, az
92+
// wait loop > 300ns (min 100ns required)
93+
movi \ax, 128
94+
1 :
95+
addi \ax, \ax, -1
96+
nop
97+
bnez \ax, 1b
98+
movi \ay, (SHIM_BASE + SHIM_LDOCTL)
99+
l32i \az, \ay, 0
100+
101+
movi \ax, ~(SHIM_LDOCTL_HPSRAM_MASK | SHIM_LDOCTL_LPSRAM_MASK)
102+
and \az, \az, \ax
103+
104+
movi \ax, (SHIM_LDOCTL_HPSRAM_LDO_OFF | SHIM_LDOCTL_LPSRAM_LDO_OFF)
105+
or \ax, \ax, \az
106+
107+
s32i \ax, \ay, 0
108+
l32i \ax, \ay, 0
109+
.endm
110+
111+
.macro m_cavs_set_ldo_bypass_state ax, ay, az
112+
// wait loop > 300ns (min 100ns required)
113+
movi \ax, 128
114+
1 :
115+
addi \ax, \ax, -1
116+
nop
117+
bnez \ax, 1b
118+
movi \ay, (SHIM_BASE + SHIM_LDOCTL)
119+
l32i \az, \ay, 0
120+
121+
movi \ax, ~(SHIM_LDOCTL_HPSRAM_MASK | SHIM_LDOCTL_LPSRAM_MASK)
122+
and \az, \az, \ax
123+
124+
movi \ax, (SHIM_LDOCTL_HPSRAM_LDO_BYPASS | SHIM_LDOCTL_LPSRAM_LDO_BYPASS)
125+
or \ax, \ax, \az
126+
127+
s32i \ax, \ay, 0
128+
l32i \ax, \ay, 0
129+
.endm
130+
131+
#endif /* ASM_LDO_MANAGEMENT_H */

‎src/platform/cannonlake/include/platform/asm_memory_management.h‎

Lines changed: 0 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -60,7 +60,6 @@
6060
* L1 SRAM)
6161
*/
6262
.macro m_cavs_hpsram_power_down_entire ax, ay, az
63-
//TODO: add LDO control
6463
// SEGMENT #0
6564
movi \az, SHIM_HSPGCTL(0)
6665
movi \ax, SHIM_HSPGISTS(0)
@@ -80,11 +79,9 @@
8079
1 :
8180
l32i \ax, \az, 0
8281
bne \ax, \ay, 1b
83-
// TODO: Add LDO control
8482
.endm
8583

8684
.macro m_cavs_hpsram_power_change segment_index, mask, ax, ay, az
87-
// TODO: Add LDO Control
8885
movi \ax, SHIM_HSPGCTL(\segment_index)
8986
movi \ay, SHIM_HSPGISTS(\segment_index)
9087
s32i \mask, \ax, 0
@@ -93,7 +90,6 @@
9390
1 :
9491
l32i \ax, \ay, 0
9592
bne \ax, \mask, 1b
96-
// TODO: Add LDO Control
9793
.endm
9894

9995
.macro m_cavs_lpsram_power_down_entire ax, ay, az

‎src/platform/cannonlake/include/platform/shim.h‎

Lines changed: 9 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -206,8 +206,15 @@
206206
#define SHIM_L2_MECS (SHIM_BASE + 0xd0)
207207

208208
#define SHIM_LDOCTL 0xA4
209-
#define SHIM_HPMEM_POWER_ON (0x3 << 0)
210-
#define SHIM_LPMEM_POWER_BYPASS (0x1 << 0)
209+
#define SHIM_LDOCTL_HPSRAM_MASK (3 << 0)
210+
#define SHIM_LDOCTL_LPSRAM_MASK (3 << 2)
211+
#define SHIM_LDOCTL_HPSRAM_LDO_ON (3 << 0)
212+
#define SHIM_LDOCTL_LPSRAM_LDO_ON (3 << 2)
213+
#define SHIM_LDOCTL_HPSRAM_LDO_BYPASS BIT(0)
214+
#define SHIM_LDOCTL_LPSRAM_LDO_BYPASS BIT(2)
215+
#define SHIM_LDOCTL_HPSRAM_LDO_OFF (0 << 0)
216+
#define SHIM_LDOCTL_LPSRAM_LDO_OFF (0 << 2)
217+
211218

212219
#define DSP_INIT_LPGPDMA(x) (0x71A60 + (2*x))
213220
#define LPGPDMA_CTLOSEL_FLAG (1 << 15)

‎src/platform/cannonlake/power_down.S‎

Lines changed: 31 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -33,7 +33,9 @@
3333
* \brief Power gating memory banks - implementation specific for Apollolake
3434
* \author Lech Betlej <lech.betlej@linux.intel.com>
3535
*/
36+
#include <platform/shim.h>
3637
#include <platform/asm_memory_management.h>
38+
#include <platform/asm_ldo_management.h>
3739

3840
.section .text, "ax"
3941
.align 64
@@ -96,6 +98,18 @@ _PD_DISABLE_HPSRAM:
9698
(hpsram_pwrgating_mask) - do not disable hpsram. */
9799
beqz pu32_hpsram_mask, _PD_SLEEP
98100

101+
/* mandatory sequence for LDO ON - effectively executes:
102+
* m_cavs_s_set_ldo_hpsram_on_state();
103+
* WAIT_300NS();
104+
*/
105+
movi temp_reg0, SHIM_LDOCTL_HPSRAM_LDO_ON
106+
m_cavs_set_hpldo_state temp_reg0, temp_reg1, temp_reg2
107+
movi temp_reg0, 128
108+
1 :
109+
addi temp_reg0, temp_reg0, -1
110+
bnez temp_reg0, 1b
111+
112+
99113
/* effectively executes:
100114
* for (size_t seg_index = (MAX_MEMORY_SEGMENTS - 1); seg_index >= 0;
101115
* --seg_index) {
@@ -117,7 +131,18 @@ beqz pu32_hpsram_mask, _PD_SLEEP
117131
.endr
118132

119133

120-
//TODO: add LDO Control
134+
/* mandatory sequence for LDO OFF - effectively executes:
135+
* WAIT_300NS();
136+
* m_cavs_set_ldo_hpsram_on_state()
137+
*/
138+
movi temp_reg0, 128
139+
1 :
140+
addi temp_reg0, temp_reg0, -1
141+
bnez temp_reg0, 1b
142+
143+
movi temp_reg0, SHIM_LDOCTL_HPSRAM_LDO_OFF
144+
m_cavs_set_hpldo_state temp_reg0, temp_reg1, temp_reg2
145+
121146
//TODO: add sending IPC reply from L1$ locked code
122147

123148
_PD_SLEEP:
@@ -130,10 +155,11 @@ loop:
130155
addi temp_reg0, temp_reg0, -1
131156
bnez temp_reg0, loop
132157

133-
extw
134-
extw
135-
waiti 5
136-
j _PD_SLEEP
158+
extw
159+
extw
160+
waiti 5
161+
1:
162+
j 1b
137163

138164
.size power_down , . - power_down
139165

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