topology: sof-glk-cs42l42: enable bclk control

Enable the bclk clock contrl for SSP2. The 10ms bclk delay is no
longer needed since bclk is enabled eariler on hw_params.

Signed-off-by: Brent Lu <brent.lu@intel.com>

(cherry picked from commit 69e6e4e6cbae25c68cf597237663fd06706fa030)
Signed-off-by: Brent Lu <brent.lu@intel.com>

Author: brentlu

tools/topology/sof-glk-da7219.m4

@@ -163,7 +163,7 @@ DAI_CONFIG(SSP, 2, 1, SSP2-Codec,
 		SSP_CLOCK(bclk, 3072000, codec_slave),
 		SSP_CLOCK(fsync, 48000, codec_slave),
 		SSP_TDM(2, 32, 3, 3),
-		SSP_CONFIG_DATA(SSP, 2, 16, 1)))
+		SSP_CONFIG_DATA(SSP, 2, 16, 1, 0, SSP_CC_BCLK_ES)))
 ', )
 
 # dmic01 (id: 2)