diff --git a/src/drivers/intel/ssp/ssp.c b/src/drivers/intel/ssp/ssp.c
index 7af11b4274d8..acb992e8b9d9 100644
--- a/src/drivers/intel/ssp/ssp.c
+++ b/src/drivers/intel/ssp/ssp.c
@@ -125,6 +125,112 @@ static int ssp_context_restore(struct dai *dai)
 	return 0;
 }
 
+static int ssp_mclk_prepare_enable(struct dai *dai)
+{
+	struct ssp_pdata *ssp = dai_get_drvdata(dai);
+	struct sof_ipc_dai_config *config = &ssp->config;
+	int ret;
+
+	if (ssp->clk_active & SSP_CLK_MCLK_ACTIVE)
+		return 0;
+
+	/* MCLK config */
+	ret = mn_set_mclk(config->ssp.mclk_id, config->ssp.mclk_rate);
+	if (ret < 0)
+		dai_err(dai, "ssp_mclk_prepare_enable(): invalid mclk_rate = %d for mclk_id = %d",
+			config->ssp.mclk_rate, config->ssp.mclk_id);
+	else
+		ssp->clk_active |= SSP_CLK_MCLK_ACTIVE;
+
+	return ret;
+}
+
+static void ssp_mclk_disable_unprepare(struct dai *dai)
+{
+	struct ssp_pdata *ssp = dai_get_drvdata(dai);
+
+	if (!(ssp->clk_active & SSP_CLK_MCLK_ACTIVE))
+		return;
+
+	mn_release_mclk(ssp->config.ssp.mclk_id);
+
+	ssp->clk_active &= ~SSP_CLK_MCLK_ACTIVE;
+}
+
+static int ssp_bclk_prepare_enable(struct dai *dai)
+{
+	struct ssp_pdata *ssp = dai_get_drvdata(dai);
+	struct sof_ipc_dai_config *config = &ssp->config;
+	uint32_t sscr0;
+	uint32_t mdiv;
+	bool need_ecs = false;
+	int ret = 0;
+
+	if (ssp->clk_active & SSP_CLK_BCLK_ACTIVE)
+		return 0;
+
+	sscr0 = ssp_read(dai, SSCR0);
+
+#if CONFIG_INTEL_MN
+	/* BCLK config */
+	ret = mn_set_bclk(config->dai_index, config->ssp.bclk_rate,
+			  &mdiv, &need_ecs);
+	if (ret < 0) {
+		dai_err(dai, "ssp_bclk_prepare_enable(): invalid bclk_rate = %d for dai_index = %d",
+			config->ssp.bclk_rate, config->dai_index);
+		goto out;
+	}
+#else
+	if (ssp_freq[SSP_DEFAULT_IDX].freq % config->ssp.bclk_rate != 0) {
+		dai_err(dai, "ssp_bclk_prepare_enable(): invalid bclk_rate = %d for dai_index = %d",
+			config->ssp.bclk_rate, config->dai_index);
+		ret = -EINVAL;
+		goto out;
+	}
+
+	mdiv = ssp_freq[SSP_DEFAULT_IDX].freq / config->ssp.bclk_rate;
+#endif
+
+	if (need_ecs)
+		sscr0 |= SSCR0_ECS;
+
+	/* clock divisor is SCR + 1 */
+	mdiv -= 1;
+
+	/* divisor must be within SCR range */
+	if (mdiv > (SSCR0_SCR_MASK >> 8)) {
+		dai_err(dai, "ssp_bclk_prepare_enable(): divisor %d is not within SCR range",
+			mdiv);
+		ret = -EINVAL;
+		goto out;
+	}
+
+	/* set the SCR divisor */
+	sscr0 &= ~SSCR0_SCR_MASK;
+	sscr0 |= SSCR0_SCR(mdiv);
+
+	ssp_write(dai, SSCR0, sscr0);
+
+	dai_info(dai, "ssp_bclk_prepare_enable(): sscr0 = 0x%08x", sscr0);
+out:
+	if (!ret)
+		ssp->clk_active |= SSP_CLK_BCLK_ACTIVE;
+
+	return ret;
+}
+
+static void ssp_bclk_disable_unprepare(struct dai *dai)
+{
+	struct ssp_pdata *ssp = dai_get_drvdata(dai);
+
+	if (!(ssp->clk_active & SSP_CLK_BCLK_ACTIVE))
+		return;
+#if CONFIG_INTEL_MN
+	mn_release_bclk(dai->index);
+#endif
+	ssp->clk_active &= ~SSP_CLK_BCLK_ACTIVE;
+}
+
 /* Digital Audio interface formatting */
 static int ssp_set_config(struct dai *dai, struct ipc_config_dai *common_config,
 			  void *spec_config)
@@ -180,8 +286,8 @@ static int ssp_set_config(struct dai *dai, struct ipc_config_dai *common_config,
 	 */
 	sscr0 = SSCR0_PSP | SSCR0_RIM | SSCR0_TIM;
 
-	/* sscr1 dynamic settings are SFRMDIR, SCLKDIR, SCFR */
-	sscr1 = SSCR1_TTE | SSCR1_TTELP | SSCR1_TRAIL | SSCR1_RSRE | SSCR1_TSRE;
+	/* sscr1 dynamic settings are SFRMDIR, SCLKDIR, SCFR, RSRE, TSRE */
+	sscr1 = SSCR1_TTE | SSCR1_TTELP | SSCR1_TRAIL;
 
 	/* sscr2 dynamic setting is LJDFD */
 	sscr2 = SSCR2_SDFD | SSCR2_TURM1;
@@ -606,6 +712,74 @@ static int ssp_set_config(struct dai *dai, struct ipc_config_dai *common_config,
 	ssp->state[DAI_DIR_PLAYBACK] = COMP_STATE_PREPARE;
 	ssp->state[DAI_DIR_CAPTURE] = COMP_STATE_PREPARE;
 
+	switch (config->flags & SOF_DAI_CONFIG_FLAGS_MASK) {
+	case SOF_DAI_CONFIG_FLAGS_HW_PARAMS:
+		if (ssp->params.clks_control & SOF_DAI_INTEL_SSP_CLKCTRL_MCLK_ES) {
+			ret = ssp_mclk_prepare_enable(dai);
+			if (ret < 0)
+				goto out;
+
+			ssp->clk_active |= SSP_CLK_MCLK_ES_REQ;
+
+			dai_info(dai, "ssp_set_config(): hw_params stage: enabled MCLK clocks for SSP%d...",
+				 dai->index);
+		}
+
+		if (ssp->params.clks_control & SOF_DAI_INTEL_SSP_CLKCTRL_BCLK_ES) {
+			bool enable_sse = false;
+
+			if (!(ssp->clk_active & SSP_CLK_BCLK_ACTIVE))
+				enable_sse = true;
+
+			ret = ssp_bclk_prepare_enable(dai);
+			if (ret < 0)
+				goto out;
+
+			ssp->clk_active |= SSP_CLK_BCLK_ES_REQ;
+
+			if (enable_sse) {
+
+				/* enable TRSE/RSRE before SSE */
+				ssp_update_bits(dai, SSCR1,
+						SSCR1_TSRE | SSCR1_RSRE,
+						SSCR1_TSRE | SSCR1_RSRE);
+
+				/* enable port */
+				ssp_update_bits(dai, SSCR0, SSCR0_SSE, SSCR0_SSE);
+
+				dai_info(dai, "ssp_set_config(): SSE set for SSP%d", dai->index);
+			}
+
+			dai_info(dai, "ssp_set_config(): hw_params stage: enabled BCLK clocks for SSP%d...",
+				 dai->index);
+		}
+		break;
+	case SOF_DAI_CONFIG_FLAGS_HW_FREE:
+		if (ssp->params.clks_control & SOF_DAI_INTEL_SSP_CLKCTRL_BCLK_ES) {
+			dai_info(dai, "ssp_set_config(): hw_free stage: releasing BCLK clocks for SSP%d...",
+				 dai->index);
+			if (ssp->clk_active & SSP_CLK_BCLK_ACTIVE) {
+				/* clear TRSE/RSRE before SSE */
+				ssp_update_bits(dai, SSCR1,
+						SSCR1_TSRE | SSCR1_RSRE,
+						0);
+
+				ssp_update_bits(dai, SSCR0, SSCR0_SSE, 0);
+				dai_info(dai, "ssp_set_config(): SSE clear for SSP%d", dai->index);
+			}
+			ssp_bclk_disable_unprepare(dai);
+			ssp->clk_active &= ~SSP_CLK_BCLK_ES_REQ;
+		}
+		if (ssp->params.clks_control & SOF_DAI_INTEL_SSP_CLKCTRL_MCLK_ES) {
+			dai_info(dai, "ssp_set_config: hw_free stage: releasing MCLK clocks for SSP%d...",
+				 dai->index);
+			ssp_mclk_disable_unprepare(dai);
+			ssp->clk_active &= ~SSP_CLK_MCLK_ES_REQ;
+		}
+		break;
+	default:
+		break;
+	}
 out:
 
 	spin_unlock(&dai->lock);
@@ -621,71 +795,23 @@ static int ssp_set_config(struct dai *dai, struct ipc_config_dai *common_config,
 static int ssp_pre_start(struct dai *dai)
 {
 	struct ssp_pdata *ssp = dai_get_drvdata(dai);
-	struct sof_ipc_dai_config *config = &ssp->config;
-	uint32_t sscr0;
-	uint32_t mdiv;
-	bool need_ecs = false;
-
 	int ret = 0;
 
 	dai_info(dai, "ssp_pre_start()");
 
-	/* SSP active means bclk already configured. */
-	if (ssp->state[SOF_IPC_STREAM_PLAYBACK] == COMP_STATE_ACTIVE ||
-	    ssp->state[SOF_IPC_STREAM_CAPTURE] == COMP_STATE_ACTIVE)
-		return 0;
-
-	/* MCLK config */
-	ret = mn_set_mclk(config->ssp.mclk_id, config->ssp.mclk_rate);
-	if (ret < 0) {
-		dai_err(dai, "invalid mclk_rate = %d for mclk_id = %d",
-			config->ssp.mclk_rate, config->ssp.mclk_id);
-		goto out;
-	}
-
-	sscr0 = ssp_read(dai, SSCR0);
-
-#if CONFIG_INTEL_MN
-	/* BCLK config */
-	ret = mn_set_bclk(config->dai_index, config->ssp.bclk_rate,
-			  &mdiv, &need_ecs);
-	if (ret < 0) {
-		dai_err(dai, "invalid bclk_rate = %d for dai_index = %d",
-			config->ssp.bclk_rate, config->dai_index);
-		goto out;
-	}
-#else
-	if (ssp_freq[SSP_DEFAULT_IDX].freq % config->ssp.bclk_rate != 0) {
-		dai_err(dai, "invalid bclk_rate = %d for dai_index = %d",
-			config->ssp.bclk_rate, config->dai_index);
-		goto out;
-	}
-
-	mdiv = ssp_freq[SSP_DEFAULT_IDX].freq / config->ssp.bclk_rate;
-#endif
-
-	if (need_ecs)
-		sscr0 |= SSCR0_ECS;
-
-	/* clock divisor is SCR + 1 */
-	mdiv -= 1;
-
-	/* divisor must be within SCR range */
-	if (mdiv > (SSCR0_SCR_MASK >> 8)) {
-		dai_err(dai, "ssp_pre_start(): divisor %d is not within SCR range",
-			mdiv);
-		ret = -EINVAL;
-		goto out;
+	/*
+	 * We will test if mclk/bclk is configured in
+	 * ssp_mclk/bclk_prepare_enable/disable functions
+	 */
+	if (!(ssp->clk_active & SSP_CLK_MCLK_ES_REQ)) {
+		/* MCLK config */
+		ret = ssp_mclk_prepare_enable(dai);
+		if (ret < 0)
+			return ret;
 	}
 
-	/* set the SCR divisor */
-	sscr0 &= ~SSCR0_SCR_MASK;
-	sscr0 |= SSCR0_SCR(mdiv);
-
-	ssp_write(dai, SSCR0, sscr0);
-
-	dai_info(dai, "ssp_set_config(), sscr0 = 0x%08x", sscr0);
-out:
+	if (!(ssp->clk_active & SSP_CLK_BCLK_ES_REQ))
+		ret = ssp_bclk_prepare_enable(dai);
 
 	return ret;
 }
@@ -702,11 +828,16 @@ static void ssp_post_stop(struct dai *dai)
 	/* release clocks if SSP is inactive */
 	if (ssp->state[SOF_IPC_STREAM_PLAYBACK] != COMP_STATE_ACTIVE &&
 	    ssp->state[SOF_IPC_STREAM_CAPTURE] != COMP_STATE_ACTIVE) {
-		dai_info(dai, "releasing BCLK/MCLK clocks for SSP%d...", dai->index);
-#if CONFIG_INTEL_MN
-		mn_release_bclk(dai->index);
-#endif
-		mn_release_mclk(ssp->config.ssp.mclk_id);
+		if (!(ssp->clk_active & SSP_CLK_BCLK_ES_REQ)) {
+			dai_info(dai, "ssp_post_stop releasing BCLK clocks for SSP%d...",
+				 dai->index);
+			ssp_bclk_disable_unprepare(dai);
+		}
+		if (!(ssp->clk_active & SSP_CLK_MCLK_ES_REQ)) {
+			dai_info(dai, "ssp_post_stop releasing MCLK clocks for SSP%d...",
+				 dai->index);
+			ssp_mclk_disable_unprepare(dai);
+		}
 	}
 }
 
@@ -752,8 +883,16 @@ static void ssp_start(struct dai *dai, int direction)
 	/* request mclk/bclk */
 	ssp_pre_start(dai);
 
-	/* enable port */
-	ssp_update_bits(dai, SSCR0, SSCR0_SSE, SSCR0_SSE);
+	if (!(ssp->clk_active & SSP_CLK_BCLK_ES_REQ)) {
+		/* enable TRSE/RSRE before SSE */
+		ssp_update_bits(dai, SSCR1,
+				SSCR1_TSRE | SSCR1_RSRE,
+				SSCR1_TSRE | SSCR1_RSRE);
+
+		/* enable port */
+		ssp_update_bits(dai, SSCR0, SSCR0_SSE, SSCR0_SSE);
+		dai_info(dai, "ssp_start(): SSE set for SSP%d", dai->index);
+	}
 	ssp->state[direction] = COMP_STATE_ACTIVE;
 
 	dai_info(dai, "ssp_start()");
@@ -767,13 +906,10 @@ static void ssp_start(struct dai *dai, int direction)
 	}
 
 	/* enable DMA */
-	if (direction == DAI_DIR_PLAYBACK) {
-		ssp_update_bits(dai, SSCR1, SSCR1_TSRE, SSCR1_TSRE);
+	if (direction == DAI_DIR_PLAYBACK)
 		ssp_update_bits(dai, SSTSA, SSTSA_TXEN, SSTSA_TXEN);
-	} else {
-		ssp_update_bits(dai, SSCR1, SSCR1_RSRE, SSCR1_RSRE);
+	else
 		ssp_update_bits(dai, SSRSA, SSRSA_RXEN, SSRSA_RXEN);
-	}
 
 	/* wait to get valid fifo status */
 	wait_delay(PLATFORM_SSP_DELAY);
@@ -794,7 +930,6 @@ static void ssp_stop(struct dai *dai, int direction)
 	/* stop Rx if neeed */
 	if (direction == DAI_DIR_CAPTURE &&
 	    ssp->state[SOF_IPC_STREAM_CAPTURE] != COMP_STATE_PREPARE) {
-		ssp_update_bits(dai, SSCR1, SSCR1_RSRE, 0);
 		ssp_update_bits(dai, SSRSA, SSRSA_RXEN, 0);
 		ssp_empty_rx_fifo(dai);
 		ssp->state[SOF_IPC_STREAM_CAPTURE] = COMP_STATE_PREPARE;
@@ -805,7 +940,6 @@ static void ssp_stop(struct dai *dai, int direction)
 	if (direction == DAI_DIR_PLAYBACK &&
 	    ssp->state[SOF_IPC_STREAM_PLAYBACK] != COMP_STATE_PREPARE) {
 		ssp_empty_tx_fifo(dai);
-		ssp_update_bits(dai, SSCR1, SSCR1_TSRE, 0);
 		ssp_update_bits(dai, SSTSA, SSTSA_TXEN, 0);
 		ssp->state[SOF_IPC_STREAM_PLAYBACK] = COMP_STATE_PREPARE;
 		dai_info(dai, "ssp_stop(), TX stop");
@@ -814,8 +948,15 @@ static void ssp_stop(struct dai *dai, int direction)
 	/* disable SSP port if no users */
 	if (ssp->state[SOF_IPC_STREAM_CAPTURE] == COMP_STATE_PREPARE &&
 	    ssp->state[SOF_IPC_STREAM_PLAYBACK] == COMP_STATE_PREPARE) {
-		ssp_update_bits(dai, SSCR0, SSCR0_SSE, 0);
-		dai_info(dai, "ssp_stop(), SSP port disabled");
+		if (!(ssp->clk_active & SSP_CLK_BCLK_ES_REQ)) {
+			/* clear TRSE/RSRE before SSE */
+			ssp_update_bits(dai, SSCR1,
+					SSCR1_TSRE | SSCR1_RSRE,
+					0);
+
+			ssp_update_bits(dai, SSCR0, SSCR0_SSE, 0);
+			dai_info(dai, "ssp_stop(): SSE clear SSP%d", dai->index);
+		}
 	}
 
 	ssp_post_stop(dai);
@@ -907,14 +1048,10 @@ static int ssp_probe(struct dai *dai)
 
 static int ssp_remove(struct dai *dai)
 {
-	struct ssp_pdata *ssp = dai_get_drvdata(dai);
-
 	pm_runtime_put_sync(SSP_CLK, dai->index);
 
-	mn_release_mclk(ssp->config.ssp.mclk_id);
-#if CONFIG_INTEL_MN
-	mn_release_bclk(dai->index);
-#endif
+	ssp_mclk_disable_unprepare(dai);
+	ssp_bclk_disable_unprepare(dai);
 
 	/* Disable SSP power */
 	pm_runtime_put_sync(SSP_POW, dai->index);
diff --git a/src/include/ipc/dai-intel.h b/src/include/ipc/dai-intel.h
index 5dd7a00744c3..41e39a47db1f 100644
--- a/src/include/ipc/dai-intel.h
+++ b/src/include/ipc/dai-intel.h
@@ -56,6 +56,10 @@
 #define SOF_DAI_INTEL_SSP_CLKCTRL_FS_KA			BIT(4)
 /* bclk idle */
 #define SOF_DAI_INTEL_SSP_CLKCTRL_BCLK_IDLE_HIGH	BIT(5)
+/* mclk early start */
+#define SOF_DAI_INTEL_SSP_CLKCTRL_MCLK_ES		BIT(6)
+/* bclk early start */
+#define SOF_DAI_INTEL_SSP_CLKCTRL_BCLK_ES		BIT(7)
 
 /* DMIC max. four controllers for eight microphone channels */
 #define SOF_DAI_INTEL_DMIC_NUM_CTRL			4
diff --git a/src/include/ipc/dai.h b/src/include/ipc/dai.h
index 71be41dc2b2c..543b9e386721 100644
--- a/src/include/ipc/dai.h
+++ b/src/include/ipc/dai.h
@@ -52,6 +52,13 @@
 #define SOF_DAI_FMT_INV_MASK		0x0f00
 #define SOF_DAI_FMT_CLOCK_PROVIDER_MASK	0xf000
 
+/* DAI_CONFIG flags */
+#define SOF_DAI_CONFIG_FLAGS_MASK	0x3
+#define SOF_DAI_CONFIG_FLAGS_NONE	(0 << 0) /**< DAI_CONFIG sent without stage information */
+#define SOF_DAI_CONFIG_FLAGS_HW_PARAMS	(1 << 0) /**< DAI_CONFIG sent during hw_params stage */
+#define SOF_DAI_CONFIG_FLAGS_HW_FREE	(2 << 0) /**< DAI_CONFIG sent during hw_free stage */
+#define SOF_DAI_CONFIG_FLAGS_RFU	(3 << 0) /**< not used, reserved for future use */
+
 /** \brief Types of DAI */
 enum sof_ipc_dai_type {
 	SOF_DAI_INTEL_NONE = 0,		/**< None */
@@ -72,7 +79,7 @@ struct sof_ipc_dai_config {
 	/* physical protocol and clocking */
 	uint16_t format;	/**< SOF_DAI_FMT_ */
 	uint8_t group_id;	/**< group ID, 0 means no group (ABI 3.17) */
-	uint8_t reserved8;	/**< alignment */
+	uint8_t flags;		/**< SOF_DAI_CONFIG_FLAGS_ (ABI 3.19) */
 
 	/* reserved for future use */
 	uint32_t reserved[8];
diff --git a/src/include/sof/drivers/ssp.h b/src/include/sof/drivers/ssp.h
index 051d404e28b6..94787fe25a3f 100644
--- a/src/include/sof/drivers/ssp.h
+++ b/src/include/sof/drivers/ssp.h
@@ -224,12 +224,18 @@ extern const struct dai_driver ssp_driver;
 #define ssp_irq(ssp) \
 	ssp->plat_data.irq
 
+#define SSP_CLK_MCLK_ES_REQ	BIT(0)
+#define SSP_CLK_MCLK_ACTIVE	BIT(1)
+#define SSP_CLK_BCLK_ES_REQ	BIT(2)
+#define SSP_CLK_BCLK_ACTIVE	BIT(3)
+
 /* SSP private data */
 struct ssp_pdata {
 	uint32_t sscr0;
 	uint32_t sscr1;
 	uint32_t psp;
 	uint32_t state[2];		/* SSP_STATE_ for each direction */
+	uint32_t clk_active;
 	struct sof_ipc_dai_config config;
 	struct sof_ipc_dai_ssp_params params;
 };
diff --git a/tools/topology/topology1/platform/common/ssp.m4 b/tools/topology/topology1/platform/common/ssp.m4
index ce1f2c35b876..39a5ba185b0f 100644
--- a/tools/topology/topology1/platform/common/ssp.m4
+++ b/tools/topology/topology1/platform/common/ssp.m4
@@ -30,6 +30,11 @@ $6
 dnl SSP_QUIRK_LBM 64 = (1 << 6)
 define(`SSP_QUIRK_LBM', 64)
 
+dnl SSP_CC_MCLK_ES 64 = (1 << 6)
+define(`SSP_CC_MCLK_ES', 64)
+dnl SSP_CC_BCLK_ES 128 = (1 << 7)
+define(`SSP_CC_BCLK_ES', 128)
+
 dnl SSP_CONFIG_DATA(type, idx, valid bits, mclk_id, quirks, bclk_delay,
 dnl clks_control, pulse_width, padding)
 dnl mclk_id, quirks, bclk_delay clks_control, pulse_width and padding are optional
diff --git a/tools/topology/topology1/sof-cavs-nocodec.m4 b/tools/topology/topology1/sof-cavs-nocodec.m4
index 94c20e86d3e4..70850fb26fc0 100644
--- a/tools/topology/topology1/sof-cavs-nocodec.m4
+++ b/tools/topology/topology1/sof-cavs-nocodec.m4
@@ -231,22 +231,26 @@ DAI_CONFIG(SSP, SSP0_IDX, 0, NoCodec-0,
 		      SSP_CLOCK(bclk, 3072000, codec_slave),
 		      SSP_CLOCK(fsync, 48000, codec_slave),
 		      SSP_TDM(2, 32, 3, 3),
-		      dnl SSP_CONFIG_DATA(type, dai_index, valid bits, mclk_id, quirks)
-		      SSP_CONFIG_DATA(SSP, SSP0_IDX, 32, 0, SSP_QUIRK_LBM)))
+		      dnl SSP_CONFIG_DATA(type, idx, valid bits, mclk_id, quirks, bclk_delay,
+		      dnl clks_control, pulse_width, padding)
+		      SSP_CONFIG_DATA(SSP, SSP0_IDX, 32, 0, SSP_QUIRK_LBM, 0,
+				      eval(SSP_CC_MCLK_ES | SSP_CC_BCLK_ES))))
 
 DAI_CONFIG(SSP, SSP1_IDX, 1, NoCodec-1,
 	   SSP_CONFIG(I2S, SSP_CLOCK(mclk, 24576000, codec_mclk_in),
 		      SSP_CLOCK(bclk, 3072000, codec_slave),
 		      SSP_CLOCK(fsync, 48000, codec_slave),
 		      SSP_TDM(2, 32, 3, 3),
-		      SSP_CONFIG_DATA(SSP, SSP1_IDX, 32, 0, SSP_QUIRK_LBM)))
+		      SSP_CONFIG_DATA(SSP, SSP1_IDX, 32, 0, SSP_QUIRK_LBM, 0,
+				      eval(SSP_CC_MCLK_ES | SSP_CC_BCLK_ES))))
 
 DAI_CONFIG(SSP, SSP2_IDX, 2, NoCodec-2,
 	   SSP_CONFIG(I2S, SSP_CLOCK(mclk, 24576000, codec_mclk_in),
 		      SSP_CLOCK(bclk, 3072000, codec_slave),
 		      SSP_CLOCK(fsync, 48000, codec_slave),
 		      SSP_TDM(2, 32, 3, 3),
-		      SSP_CONFIG_DATA(SSP, SSP2_IDX, 32, 0, SSP_QUIRK_LBM)))
+		      SSP_CONFIG_DATA(SSP, SSP2_IDX, 32, 0, SSP_QUIRK_LBM, 0,
+				      eval(SSP_CC_MCLK_ES | SSP_CC_BCLK_ES))))
 ')
 
 ifelse(ROOT_CLK, `24',
@@ -257,22 +261,24 @@ DAI_CONFIG(SSP, SSP0_IDX, 0, NoCodec-0,
 		      SSP_CLOCK(bclk, 4800000, codec_slave),
 		      SSP_CLOCK(fsync, 48000, codec_slave),
 		      SSP_TDM(2, 25, 3, 3),
-		      dnl SSP_CONFIG_DATA(type, dai_index, valid bits, mclk_id, quirks)
-		      SSP_CONFIG_DATA(SSP, SSP0_IDX, 24, 0, SSP_QUIRK_LBM)))
+		      SSP_CONFIG_DATA(SSP, SSP0_IDX, 24, 0, SSP_QUIRK_LBM, 0,
+				      eval(SSP_CC_MCLK_ES | SSP_CC_BCLK_ES))))
 
 DAI_CONFIG(SSP, SSP1_IDX, 1, NoCodec-1,
 	   SSP_CONFIG(I2S, SSP_CLOCK(mclk, 24000000, codec_mclk_in),
 		      SSP_CLOCK(bclk, 4800000, codec_slave),
 		      SSP_CLOCK(fsync, 48000, codec_slave),
 		      SSP_TDM(2, 25, 3, 3),
-		      SSP_CONFIG_DATA(SSP, SSP1_IDX, 24, 0, SSP_QUIRK_LBM)))
+		      SSP_CONFIG_DATA(SSP, SSP1_IDX, 24, 0, SSP_QUIRK_LBM, 0,
+				      eval(SSP_CC_MCLK_ES | SSP_CC_BCLK_ES))))
 
 DAI_CONFIG(SSP, SSP2_IDX, 2, NoCodec-2,
 	   SSP_CONFIG(I2S, SSP_CLOCK(mclk, 24000000, codec_mclk_in),
 		      SSP_CLOCK(bclk, 4800000, codec_slave),
 		      SSP_CLOCK(fsync, 48000, codec_slave),
 		      SSP_TDM(2, 25, 3, 3),
-		      SSP_CONFIG_DATA(SSP, SSP2_IDX, 24, 0, SSP_QUIRK_LBM)))
+		      SSP_CONFIG_DATA(SSP, SSP2_IDX, 24, 0, SSP_QUIRK_LBM, 0,
+				      eval(SSP_CC_MCLK_ES | SSP_CC_BCLK_ES))))
 ')
 
 ifelse(ROOT_CLK, `38_4',
@@ -282,19 +288,22 @@ DAI_CONFIG(SSP, SSP0_IDX, 0, NoCodec-0,
 		      SSP_CLOCK(bclk, 2400000, codec_slave),
 		      SSP_CLOCK(fsync, 48000, codec_slave),
 		      SSP_TDM(2, 25, 3, 3),
-		      SSP_CONFIG_DATA(SSP, SSP0_IDX, 24, 0, SSP_QUIRK_LBM)))
+		      SSP_CONFIG_DATA(SSP, SSP0_IDX, 24, 0, SSP_QUIRK_LBM, 0,
+				      eval(SSP_CC_MCLK_ES | SSP_CC_BCLK_ES))))
 
 DAI_CONFIG(SSP, SSP1_IDX, 1, NoCodec-1,
 	   SSP_CONFIG(I2S, SSP_CLOCK(mclk, 38400000, codec_mclk_in),
 		      SSP_CLOCK(bclk, 2400000, codec_slave),
 		      SSP_CLOCK(fsync, 48000, codec_slave),
 		      SSP_TDM(2, 25, 3, 3),
-		      SSP_CONFIG_DATA(SSP, SSP1_IDX, 24, 0, SSP_QUIRK_LBM)))
+		      SSP_CONFIG_DATA(SSP, SSP1_IDX, 24, 0, SSP_QUIRK_LBM, 0,
+				      eval(SSP_CC_MCLK_ES | SSP_CC_BCLK_ES))))
 
 DAI_CONFIG(SSP, SSP2_IDX, 2, NoCodec-2,
 	   SSP_CONFIG(I2S, SSP_CLOCK(mclk, 38400000, codec_mclk_in),
 		      SSP_CLOCK(bclk, 2400000, codec_slave),
 		      SSP_CLOCK(fsync, 48000, codec_slave),
 		      SSP_TDM(2, 25, 3, 3),
-		      SSP_CONFIG_DATA(SSP, SSP2_IDX, 24, 0, SSP_QUIRK_LBM)))
+		      SSP_CONFIG_DATA(SSP, SSP2_IDX, 24, 0, SSP_QUIRK_LBM, 0,
+				      eval(SSP_CC_MCLK_ES | SSP_CC_BCLK_ES))))
 ')
diff --git a/tools/topology/topology1/sof-glk-da7219.m4 b/tools/topology/topology1/sof-glk-da7219.m4
index 226d9fda3578..61be17c92928 100644
--- a/tools/topology/topology1/sof-glk-da7219.m4
+++ b/tools/topology/topology1/sof-glk-da7219.m4
@@ -201,7 +201,7 @@ DAI_CONFIG(SSP, 2, 1, SSP2-Codec,
 		SSP_CLOCK(bclk, 2400000, codec_slave),
 		SSP_CLOCK(fsync, 48000, codec_slave),
 		SSP_TDM(2, 25, 3, 3),
-		SSP_CONFIG_DATA(SSP, 2, 24, 1, 0, 10)))
+		SSP_CONFIG_DATA(SSP, 2, 24, 1, 0, 0, SSP_CC_BCLK_ES)))
 ', )
 
 # dmic01 (id: 2)