From cc92bb149e6d6127eb3c16bb2d0cccf00dccdaaf Mon Sep 17 00:00:00 2001 From: Allen-KH Cheng Date: Fri, 27 Aug 2021 14:19:57 +0800 Subject: [PATCH 01/15] platform: mtk: add xtensa headers for mt8195 Add xtensa headers for mtk mt8195 platform. Signed-off-by: YC Hung Signed-off-by: Allen-KH Cheng --- .../include/arch/xtensa/config/core-isa.h | 697 ++++++++++++++++++ .../include/arch/xtensa/config/core-matmap.h | 105 +++ .../mt8195/include/arch/xtensa/config/defs.h | 38 + .../include/arch/xtensa/config/specreg.h | 104 +++ .../include/arch/xtensa/config/system.h | 249 +++++++ .../include/arch/xtensa/config/tie-asm.h | 314 ++++++++ .../mt8195/include/arch/xtensa/config/tie.h | 191 +++++ 7 files changed, 1698 insertions(+) create mode 100644 src/platform/mt8195/include/arch/xtensa/config/core-isa.h create mode 100644 src/platform/mt8195/include/arch/xtensa/config/core-matmap.h create mode 100644 src/platform/mt8195/include/arch/xtensa/config/defs.h create mode 100644 src/platform/mt8195/include/arch/xtensa/config/specreg.h create mode 100644 src/platform/mt8195/include/arch/xtensa/config/system.h create mode 100644 src/platform/mt8195/include/arch/xtensa/config/tie-asm.h create mode 100644 src/platform/mt8195/include/arch/xtensa/config/tie.h diff --git a/src/platform/mt8195/include/arch/xtensa/config/core-isa.h b/src/platform/mt8195/include/arch/xtensa/config/core-isa.h new file mode 100644 index 000000000000..0c5a5fd59fe5 --- /dev/null +++ b/src/platform/mt8195/include/arch/xtensa/config/core-isa.h @@ -0,0 +1,697 @@ +/* +* xtensa/config/core-isa.h -- HAL definitions that are dependent on Xtensa +* processor CORE configuration +* +* See , which includes this file, for more details. +*/ +/* Xtensa processor core configuration information. + + Customer ID=16233; Build=0x89932; Copyright (c) 1999-2020 Tensilica Inc. + + Permission is hereby granted, free of charge, to any person obtaining + a copy of this software and associated documentation files (the + "Software"), to deal in the Software without restriction, including + without limitation the rights to use, copy, modify, merge, publish, + distribute, sublicense, and/or sell copies of the Software, and to + permit persons to whom the Software is furnished to do so, subject to + the following conditions: + + The above copyright notice and this permission notice shall be included + in all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ + +#ifndef _XTENSA_CORE_CONFIGURATION_H +#define _XTENSA_CORE_CONFIGURATION_H + +/* depot/dev/Homewood/Xtensa/SWConfig/hal/core-common.h.tph#24 - edit change 444323 (text+ko) */ + +/**************************************************************************** + Parameters Useful for Any Code, USER or PRIVILEGED + ****************************************************************************/ + +/* + * Note: Macros of the form XCHAL_HAVE_*** have a value of 1 if the option is + * configured, and a value of 0 otherwise. These macros are always defined. + */ + + +/*---------------------------------------------------------------------- + ISA + ----------------------------------------------------------------------*/ + +#define XCHAL_HAVE_BE 0 /* big-endian byte ordering */ +#define XCHAL_HAVE_WINDOWED 1 /* windowed registers option */ +#define XCHAL_NUM_AREGS 64 /* num of physical addr regs */ +#define XCHAL_NUM_AREGS_LOG2 6 /* log2(XCHAL_NUM_AREGS) */ +#define XCHAL_MAX_INSTRUCTION_SIZE 11 /* max instr bytes (3..8) */ +#define XCHAL_HAVE_DEBUG 1 /* debug option */ +#define XCHAL_HAVE_DENSITY 1 /* 16-bit instructions */ +#define XCHAL_HAVE_LOOPS 1 /* zero-overhead loops */ +#define XCHAL_LOOP_BUFFER_SIZE 256 /* zero-ov. loop instr buffer size */ +#define XCHAL_HAVE_NSA 1 /* NSA/NSAU instructions */ +#define XCHAL_HAVE_MINMAX 1 /* MIN/MAX instructions */ +#define XCHAL_HAVE_SEXT 1 /* SEXT instruction */ +#define XCHAL_HAVE_DEPBITS 0 /* DEPBITS instruction */ +#define XCHAL_HAVE_CLAMPS 1 /* CLAMPS instruction */ +#define XCHAL_HAVE_MUL16 1 /* MUL16S/MUL16U instructions */ +#define XCHAL_HAVE_MUL32 1 /* MULL instruction */ +#define XCHAL_HAVE_MUL32_HIGH 0 /* MULUH/MULSH instructions */ +#define XCHAL_HAVE_DIV32 1 /* QUOS/QUOU/REMS/REMU instructions */ +#define XCHAL_HAVE_L32R 1 /* L32R instruction */ +#define XCHAL_HAVE_ABSOLUTE_LITERALS 0 /* non-PC-rel (extended) L32R */ +#define XCHAL_HAVE_CONST16 0 /* CONST16 instruction */ +#define XCHAL_HAVE_ADDX 1 /* ADDX#/SUBX# instructions */ +#define XCHAL_HAVE_EXCLUSIVE 1 /* L32EX/S32EX instructions */ +#define XCHAL_HAVE_WIDE_BRANCHES 0 /* B*.W18 or B*.W15 instr's */ +#define XCHAL_HAVE_PREDICTED_BRANCHES 0 /* B[EQ/EQZ/NE/NEZ]T instr's */ +#define XCHAL_HAVE_CALL4AND12 1 /* (obsolete option) */ +#define XCHAL_HAVE_ABS 1 /* ABS instruction */ +#define XCHAL_HAVE_RELEASE_SYNC 1 /* L32AI/S32RI instructions */ +#define XCHAL_HAVE_S32C1I 0 /* S32C1I instruction */ +#define XCHAL_HAVE_SPECULATION 0 /* speculation */ +#define XCHAL_HAVE_FULL_RESET 1 /* all regs/state reset */ +#define XCHAL_NUM_CONTEXTS 1 /* */ +#define XCHAL_NUM_MISC_REGS 4 /* num of scratch regs (0..4) */ +#define XCHAL_HAVE_TAP_MASTER 0 /* JTAG TAP control instr's */ +#define XCHAL_HAVE_PRID 1 /* processor ID register */ +#define XCHAL_HAVE_EXTERN_REGS 1 /* WER/RER instructions */ +#define XCHAL_HAVE_MX 0 /* MX core (Tensilica internal) */ +#define XCHAL_HAVE_MP_INTERRUPTS 0 /* interrupt distributor port */ +#define XCHAL_HAVE_MP_RUNSTALL 0 /* core RunStall control port */ +#define XCHAL_HAVE_PSO 0 /* Power Shut-Off */ +#define XCHAL_HAVE_PSO_CDM 0 /* core/debug/mem pwr domains */ +#define XCHAL_HAVE_PSO_FULL_RETENTION 0 /* all regs preserved on PSO */ +#define XCHAL_HAVE_THREADPTR 1 /* THREADPTR register */ +#define XCHAL_HAVE_BOOLEANS 1 /* boolean registers */ +#define XCHAL_HAVE_CP 1 /* CPENABLE reg (coprocessor) */ +#define XCHAL_CP_MAXCFG 2 /* max allowed cp id plus one */ +#define XCHAL_HAVE_MAC16 0 /* MAC16 package */ +#define XCHAL_HAVE_LX 1 /* LX core */ +#define XCHAL_HAVE_NX 0 /* NX core (starting RH) */ + +#define XCHAL_HAVE_SUPERGATHER 0 /* SuperGather */ + +#define XCHAL_HAVE_FUSION 0 /* Fusion*/ +#define XCHAL_HAVE_FUSION_FP 0 /* Fusion FP option */ +#define XCHAL_HAVE_FUSION_LOW_POWER 0 /* Fusion Low Power option */ +#define XCHAL_HAVE_FUSION_AES 0 /* Fusion BLE/Wifi AES-128 CCM option */ +#define XCHAL_HAVE_FUSION_CONVENC 0 /* Fusion Conv Encode option */ +#define XCHAL_HAVE_FUSION_LFSR_CRC 0 /* Fusion LFSR-CRC option */ +#define XCHAL_HAVE_FUSION_BITOPS 0 /* Fusion Bit Operations Support option */ +#define XCHAL_HAVE_FUSION_AVS 0 /* Fusion AVS option */ +#define XCHAL_HAVE_FUSION_16BIT_BASEBAND 0 /* Fusion 16-bit Baseband option */ +#define XCHAL_HAVE_FUSION_VITERBI 0 /* Fusion Viterbi option */ +#define XCHAL_HAVE_FUSION_SOFTDEMAP 0 /* Fusion Soft Bit Demap option */ +#define XCHAL_HAVE_HIFIPRO 0 /* HiFiPro Audio Engine pkg */ +#define XCHAL_HAVE_HIFI5 0 /* HiFi5 Audio Engine pkg */ +#define XCHAL_HAVE_HIFI5_NN_MAC 0 /* HiFi5 Audio Engine NN-MAC option */ +#define XCHAL_HAVE_HIFI5_VFPU 0 /* HiFi5 Audio Engine Single-Precision VFPU option */ +#define XCHAL_HAVE_HIFI5_HP_VFPU 0 /* HiFi5 Audio Engine Half-Precision VFPU option */ +#define XCHAL_HAVE_HIFI4 1 /* HiFi4 Audio Engine pkg */ +#define XCHAL_HAVE_HIFI4_VFPU 1 /* HiFi4 Audio Engine VFPU option */ +#define XCHAL_HAVE_HIFI3 1 /* HiFi3 Audio Engine pkg */ +#define XCHAL_HAVE_HIFI3_VFPU 0 /* HiFi3 Audio Engine VFPU option */ +#define XCHAL_HAVE_HIFI3Z 0 /* HiFi3Z Audio Engine pkg */ +#define XCHAL_HAVE_HIFI3Z_VFPU 0 /* HiFi3Z Audio Engine VFPU option */ +#define XCHAL_HAVE_HIFI2 0 /* HiFi2 Audio Engine pkg */ +#define XCHAL_HAVE_HIFI2EP 0 /* HiFi2EP */ +#define XCHAL_HAVE_HIFI_MINI 0 + + +#define XCHAL_HAVE_VECTORFPU2005 0 /* vector floating-point pkg */ +#define XCHAL_HAVE_USER_DPFPU 0 /* user DP floating-point pkg */ +#define XCHAL_HAVE_USER_SPFPU 1 /* user SP floating-point pkg */ +#define XCHAL_HAVE_FP 1 /* single prec floating point */ +#define XCHAL_HAVE_FP_DIV 1 /* FP with DIV instructions */ +#define XCHAL_HAVE_FP_RECIP 1 /* FP with RECIP instructions */ +#define XCHAL_HAVE_FP_SQRT 1 /* FP with SQRT instructions */ +#define XCHAL_HAVE_FP_RSQRT 1 /* FP with RSQRT instructions */ +#define XCHAL_HAVE_DFP 0 /* double precision FP pkg */ +#define XCHAL_HAVE_DFP_DIV 0 /* DFP with DIV instructions */ +#define XCHAL_HAVE_DFP_RECIP 0 /* DFP with RECIP instructions*/ +#define XCHAL_HAVE_DFP_SQRT 0 /* DFP with SQRT instructions */ +#define XCHAL_HAVE_DFP_RSQRT 0 /* DFP with RSQRT instructions*/ +#define XCHAL_HAVE_DFP_ACCEL 0 /* double precision FP acceleration pkg */ +#define XCHAL_HAVE_DFP_accel XCHAL_HAVE_DFP_ACCEL /* for backward compatibility */ + +#define XCHAL_HAVE_DFPU_SINGLE_ONLY 0 /* DFPU Coprocessor, single precision only */ +#define XCHAL_HAVE_DFPU_SINGLE_DOUBLE 0 /* DFPU Coprocessor, single and double precision */ +#define XCHAL_HAVE_VECTRA1 0 /* Vectra I pkg */ +#define XCHAL_HAVE_VECTRALX 0 /* Vectra LX pkg */ + +#define XCHAL_HAVE_FUSIONG 0 /* FusionG */ +#define XCHAL_HAVE_FUSIONG3 0 /* FusionG3 */ +#define XCHAL_HAVE_FUSIONG6 0 /* FusionG6 */ +#define XCHAL_HAVE_FUSIONG_SP_VFPU 0 /* sp_vfpu option on FusionG */ +#define XCHAL_HAVE_FUSIONG_DP_VFPU 0 /* dp_vfpu option on FusionG */ +#define XCHAL_FUSIONG_SIMD32 0 /* simd32 for FusionG */ + +#define XCHAL_HAVE_FUSIONJ 0 /* FusionJ */ +#define XCHAL_HAVE_FUSIONJ6 0 /* FusionJ6 */ +#define XCHAL_HAVE_FUSIONJ_SP_VFPU 0 /* sp_vfpu option on FusionJ */ +#define XCHAL_HAVE_FUSIONJ_DP_VFPU 0 /* dp_vfpu option on FusionJ */ +#define XCHAL_FUSIONJ_SIMD32 0 /* simd32 for FusionJ */ + +#define XCHAL_HAVE_PDX 0 /* PDX-LX */ +#define XCHAL_PDX_SIMD32 0 /* simd32 for PDX */ +#define XCHAL_HAVE_PDX4 0 /* PDX4-LX */ +#define XCHAL_HAVE_PDX8 0 /* PDX8-LX */ +#define XCHAL_HAVE_PDX16 0 /* PDX16-LX */ +#define XCHAL_HAVE_PDXNX 0 /* PDX-NX */ + +#define XCHAL_HAVE_CONNXD2 0 /* ConnX D2 pkg */ +#define XCHAL_HAVE_CONNXD2_DUALLSFLIX 0 /* ConnX D2 & Dual LoadStore Flix */ +#define XCHAL_HAVE_BALL 0 +#define XCHAL_HAVE_BALLAP 0 +#define XCHAL_HAVE_BBE16 0 /* ConnX BBE16 pkg */ +#define XCHAL_HAVE_BBE16_RSQRT 0 /* BBE16 & vector recip sqrt */ +#define XCHAL_HAVE_BBE16_VECDIV 0 /* BBE16 & vector divide */ +#define XCHAL_HAVE_BBE16_DESPREAD 0 /* BBE16 & despread */ +#define XCHAL_HAVE_CONNX_B10 0 /* ConnX B10 pkg*/ +#define XCHAL_HAVE_CONNX_B20 0 /* ConnX B20 pkg*/ +#define XCHAL_HAVE_CONNX_B_SP_VFPU 0 /* Single-precision Vector Floating-point option on ConnX B10 & B20 */ +#define XCHAL_HAVE_CONNX_B_SPX_VFPU 0 /* Single-precision Extended Vector Floating-point option on ConnX B10 & B20 */ +#define XCHAL_HAVE_CONNX_B_HPX_VFPU 0 /* Half-precision Extended Vector Floating-point option on ConnX B10 & B20 */ +#define XCHAL_HAVE_CONNX_B_32B_MAC 0 /* 32-bit vector MAC (real and complex), FIR & FFT option on ConnX B10 & B20 */ +#define XCHAL_HAVE_CONNX_B_VITERBI 0 /* Viterbi option on ConnX B10 & B20 */ +#define XCHAL_HAVE_CONNX_B_TURBO 0 /* Turbo option on ConnX B10 & B20 */ +#define XCHAL_HAVE_BBENEP 0 /* ConnX BBENEP pkgs */ +#define XCHAL_HAVE_BBENEP_SP_VFPU 0 /* sp_vfpu option on BBE-EP */ +#define XCHAL_HAVE_BSP3 0 /* ConnX BSP3 pkg */ +#define XCHAL_HAVE_BSP3_TRANSPOSE 0 /* BSP3 & transpose32x32 */ +#define XCHAL_HAVE_SSP16 0 /* ConnX SSP16 pkg */ +#define XCHAL_HAVE_SSP16_VITERBI 0 /* SSP16 & viterbi */ +#define XCHAL_HAVE_TURBO16 0 /* ConnX Turbo16 pkg */ +#define XCHAL_HAVE_BBP16 0 /* ConnX BBP16 pkg */ +#define XCHAL_HAVE_FLIX3 0 /* basic 3-way FLIX option */ +#define XCHAL_HAVE_GRIVPEP 0 /* General Release of IVPEP */ +#define XCHAL_HAVE_GRIVPEP_HISTOGRAM 0 /* Histogram option on GRIVPEP */ + +#define XCHAL_HAVE_VISION 0 /* Vision P5/P6 */ +#define XCHAL_VISION_SIMD16 0 /* simd16 for Vision P5/P6 */ +#define XCHAL_VISION_TYPE 0 /* Vision P5, P6, Q6 or Q7 */ +#define XCHAL_VISION_QUAD_MAC_TYPE 0 /* quad_mac option on Vision P6 */ +#define XCHAL_HAVE_VISION_HISTOGRAM 0 /* histogram option on Vision P5/P6 */ +#define XCHAL_HAVE_VISION_SP_VFPU 0 /* sp_vfpu option on Vision P5/P6/Q6/Q7 */ +#define XCHAL_HAVE_VISION_SP_VFPU_2XFMAC 0 /* sp_vfpu_2xfma option on Vision Q7 */ +#define XCHAL_HAVE_VISION_HP_VFPU 0 /* hp_vfpu option on Vision P6/Q6 */ +#define XCHAL_HAVE_VISION_HP_VFPU_2XFMAC 0 /* hp_vfpu_2xfma option on Vision Q7 */ + +#define XCHAL_HAVE_VISIONC 0 /* Vision C */ + +#define XCHAL_HAVE_XNNE 0 /* XNNE */ + +/*---------------------------------------------------------------------- + MISC + ----------------------------------------------------------------------*/ + +#define XCHAL_NUM_LOADSTORE_UNITS 2 /* load/store units */ +#define XCHAL_NUM_WRITEBUFFER_ENTRIES 32 /* size of write buffer */ +#define XCHAL_INST_FETCH_WIDTH 16 /* instr-fetch width in bytes */ +#define XCHAL_DATA_WIDTH 8 /* data width in bytes */ +#define XCHAL_DATA_PIPE_DELAY 2 /* d-side pipeline delay + (1 = 5-stage, 2 = 7-stage) */ +#define XCHAL_CLOCK_GATING_GLOBAL 1 /* global clock gating */ +#define XCHAL_CLOCK_GATING_FUNCUNIT 1 /* funct. unit clock gating */ +/* In T1050, applies to selected core load and store instructions (see ISA): */ +#define XCHAL_UNALIGNED_LOAD_EXCEPTION 1 /* unaligned loads cause exc. */ +#define XCHAL_UNALIGNED_STORE_EXCEPTION 1 /* unaligned stores cause exc.*/ +#define XCHAL_UNALIGNED_LOAD_HW 0 /* unaligned loads work in hw */ +#define XCHAL_UNALIGNED_STORE_HW 0 /* unaligned stores work in hw*/ + +#define XCHAL_UNIFIED_LOADSTORE 0 + +#define XCHAL_SW_VERSION 1401000 /* sw version of this header */ +#define XCHAL_SW_MINOR_VERSION 1401000 /* same, with zeroed micro and patch */ +#define XCHAL_SW_MICRO_VERSION 1401000 /* same, with zeroed patch */ + +#define XCHAL_CORE_ID "hifi4_8195_PROD" /* alphanum core name + (CoreID) set in the Xtensa + Processor Generator */ + +#define XCHAL_BUILD_UNIQUE_ID 0x00089932 /* 22-bit sw build ID */ + +/* + * These definitions describe the hardware targeted by this software. + */ +#define XCHAL_HW_CONFIGID0 0xC003B286 /* ConfigID hi 32 bits*/ +#define XCHAL_HW_CONFIGID1 0x28489932 /* ConfigID lo 32 bits*/ +#define XCHAL_HW_VERSION_NAME "LX7.1.1" /* full version name */ +#define XCHAL_HW_VERSION_MAJOR 2810 /* major ver# of targeted hw */ +#define XCHAL_HW_VERSION_MINOR 1 /* minor ver# of targeted hw */ +#define XCHAL_HW_VERSION_MICRO /* subdot ver# of targeted hw */ +#define XCHAL_HW_VERSION 281010 /* major*100+(major<2810 ? minor : minor*10+micro) */ +#define XCHAL_HW_REL_LX7 1 +#define XCHAL_HW_REL_LX7_1 1 +#define XCHAL_HW_REL_LX7_1_1 1 +#define XCHAL_HW_CONFIGID_RELIABLE 1 +/* If software targets a *range* of hardware versions, these are the bounds: */ +#define XCHAL_HW_MIN_VERSION_MAJOR 2810 /* major v of earliest tgt hw */ +#define XCHAL_HW_MIN_VERSION_MINOR 1 /* minor v of earliest tgt hw */ +#define XCHAL_HW_MIN_VERSION_MICRO 0 /* micro v of earliest tgt hw */ +#define XCHAL_HW_MIN_VERSION 281010 /* earliest targeted hw */ +#define XCHAL_HW_MAX_VERSION_MAJOR 2810 /* major v of latest tgt hw */ +#define XCHAL_HW_MAX_VERSION_MINOR 1 /* minor v of latest tgt hw */ +#define XCHAL_HW_MAX_VERSION_MICRO /* micro v of latest tgt hw */ +#define XCHAL_HW_MAX_VERSION 281010 /* latest targeted hw */ + +/* Config is enabled for functional safety: */ +#define XCHAL_HAVE_FUNC_SAFETY 0 + +#define XCHAL_HAVE_APB 0 + +/*---------------------------------------------------------------------- + CACHE + ----------------------------------------------------------------------*/ + +#define XCHAL_ICACHE_LINESIZE 128 /* I-cache line size in bytes */ +#define XCHAL_DCACHE_LINESIZE 128 /* D-cache line size in bytes */ +#define XCHAL_ICACHE_LINEWIDTH 7 /* log2(I line size in bytes) */ +#define XCHAL_DCACHE_LINEWIDTH 7 /* log2(D line size in bytes) */ + +#define XCHAL_ICACHE_SIZE 32768 /* I-cache size in bytes or 0 */ +#define XCHAL_ICACHE_SIZE_LOG2 15 +#define XCHAL_DCACHE_SIZE 131072 /* D-cache size in bytes or 0 */ +#define XCHAL_DCACHE_SIZE_LOG2 17 + +#define XCHAL_DCACHE_IS_WRITEBACK 1 /* writeback feature */ +#define XCHAL_DCACHE_IS_COHERENT 0 /* MP coherence feature */ + +#define XCHAL_HAVE_PREFETCH 1 /* PREFCTL register */ +#define XCHAL_HAVE_PREFETCH_L1 0 /* prefetch to L1 cache */ +#define XCHAL_PREFETCH_CASTOUT_LINES 1 /* dcache pref. castout bufsz */ +#define XCHAL_PREFETCH_ENTRIES 16 /* cache prefetch entries */ +#define XCHAL_PREFETCH_BLOCK_ENTRIES 0 /* prefetch block streams */ +#define XCHAL_HAVE_CACHE_BLOCKOPS 0 /* block prefetch for caches */ +#define XCHAL_HAVE_CME_DOWNGRADES 0 +#define XCHAL_HAVE_ICACHE_TEST 1 /* Icache test instructions */ +#define XCHAL_HAVE_DCACHE_TEST 1 /* Dcache test instructions */ +#define XCHAL_HAVE_ICACHE_DYN_WAYS 1 /* Icache dynamic way support */ +#define XCHAL_HAVE_DCACHE_DYN_WAYS 1 /* Dcache dynamic way support */ +#define XCHAL_HAVE_ICACHE_DYN_ENABLE 1 /* Icache enabled via MEMCTL */ +#define XCHAL_HAVE_DCACHE_DYN_ENABLE 1 /* Dcache enabled via MEMCTL */ + +#define XCHAL_L1SCACHE_SIZE 0 +#define XCHAL_L1SCACHE_SIZE_LOG2 0 +#define XCHAL_L1SCACHE_WAYS 1 +#define XCHAL_L1SCACHE_WAYS_LOG2 0 +#define XCHAL_L1SCACHE_ACCESS_SIZE 0 +#define XCHAL_L1SCACHE_BANKS 1 + +#define XCHAL_HAVE_L2 0 /* NX L2 cache controller */ + +/* This one is a form of caching, though not architecturally visible: */ +#define XCHAL_HAVE_BRANCH_PREDICTION 0 /* branch [target] prediction */ + + + + +/**************************************************************************** + Parameters Useful for PRIVILEGED (Supervisory or Non-Virtualized) Code + ****************************************************************************/ + + +#ifndef XTENSA_HAL_NON_PRIVILEGED_ONLY + +/*---------------------------------------------------------------------- + CACHE + ----------------------------------------------------------------------*/ + +#define XCHAL_HAVE_PIF 1 /* any outbound bus present */ + +#define XCHAL_HAVE_AXI 1 /* AXI bus */ +#define XCHAL_HAVE_AXI_ECC 1 /* ECC on AXI bus */ +#define XCHAL_HAVE_ACELITE 0 /* ACELite bus */ + +#define XCHAL_HAVE_PIF_WR_RESP 1 /* pif write response */ +#define XCHAL_HAVE_PIF_REQ_ATTR 1 /* pif attribute */ + +/* If present, cache size in bytes == (ways * 2^(linewidth + setwidth)). */ + +/* Number of cache sets in log2(lines per way): */ +#define XCHAL_ICACHE_SETWIDTH 6 +#define XCHAL_DCACHE_SETWIDTH 8 + +/* Cache set associativity (number of ways): */ +#define XCHAL_ICACHE_WAYS 4 +#define XCHAL_ICACHE_WAYS_LOG2 2 +#define XCHAL_DCACHE_WAYS 4 +#define XCHAL_DCACHE_WAYS_LOG2 2 + +/* Cache features: */ +#define XCHAL_ICACHE_LINE_LOCKABLE 1 +#define XCHAL_DCACHE_LINE_LOCKABLE 1 +#define XCHAL_ICACHE_ECC_PARITY 0 +#define XCHAL_DCACHE_ECC_PARITY 0 +#define XCHAL_ICACHE_ECC_WIDTH 4 +#define XCHAL_DCACHE_ECC_WIDTH 1 + +/* Cache access size in bytes (affects operation of SICW instruction): */ +#define XCHAL_ICACHE_ACCESS_SIZE 16 +#define XCHAL_DCACHE_ACCESS_SIZE 8 + +#define XCHAL_DCACHE_BANKS 2 /* number of banks */ + +/* The number of Cache lines associated with a single cache tag */ +#define XCHAL_DCACHE_LINES_PER_TAG_LOG2 0 + +/* Number of encoded cache attr bits (see for decoded bits): */ + + +/*---------------------------------------------------------------------- + INTERNAL I/D RAM/ROMs and XLMI + ----------------------------------------------------------------------*/ +#define XCHAL_NUM_INSTROM 0 /* number of core instr. ROMs */ +#define XCHAL_NUM_INSTRAM 0 /* number of core instr. RAMs */ +#define XCHAL_NUM_DATAROM 0 /* number of core data ROMs */ +#define XCHAL_NUM_DATARAM 0 /* number of core data RAMs */ +#define XCHAL_NUM_URAM 0 /* number of core unified RAMs*/ +#define XCHAL_NUM_XLMI 0 /* number of core XLMI ports */ +#define XCHAL_HAVE_IRAMCFG 0 /* IRAMxCFG register present */ +#define XCHAL_HAVE_DRAMCFG 0 /* DRAMxCFG register present */ + + +#define XCHAL_HAVE_IDMA 0 + + +#define XCHAL_HAVE_IMEM_LOADSTORE 1 /* can load/store to IROM/IRAM*/ + +/*---------------------------------------------------------------------- + INTERRUPTS and TIMERS + ----------------------------------------------------------------------*/ + +#define XCHAL_HAVE_INTERRUPTS 1 /* interrupt option */ +#define XCHAL_HAVE_NMI 0 /* non-maskable interrupt */ +#define XCHAL_HAVE_CCOUNT 1 /* CCOUNT reg. (timer option) */ +#define XCHAL_NUM_TIMERS 3 /* number of CCOMPAREn regs */ +#define XCHAL_NUM_INTERRUPTS 25 /* number of interrupts */ +#define XCHAL_NUM_INTERRUPTS_LOG2 5 /* ceil(log2(NUM_INTERRUPTS)) */ +#define XCHAL_NUM_EXTINTERRUPTS 18 /* num of external interrupts */ +#define XCHAL_NUM_INTLEVELS 4 /* number of interrupt levels + (not including level zero) */ + + +#define XCHAL_HAVE_HIGHPRI_INTERRUPTS 1 /* med/high-pri. interrupts */ +#define XCHAL_EXCM_LEVEL 2 /* level masked by PS.EXCM */ + /* (always 1 in XEA1; levels 2 .. EXCM_LEVEL are "medium priority") */ + +/* Masks of interrupts at each interrupt level: */ +#define XCHAL_INTLEVEL1_MASK 0x00B900FF +#define XCHAL_INTLEVEL2_MASK 0x0142FF00 +#define XCHAL_INTLEVEL3_MASK 0x00040000 +#define XCHAL_INTLEVEL4_MASK 0x00000000 +#define XCHAL_INTLEVEL5_MASK 0x00000000 +#define XCHAL_INTLEVEL6_MASK 0x00000000 +#define XCHAL_INTLEVEL7_MASK 0x00000000 + +/* Masks of interrupts at each range 1..n of interrupt levels: */ +#define XCHAL_INTLEVEL1_ANDBELOW_MASK 0x00B900FF +#define XCHAL_INTLEVEL2_ANDBELOW_MASK 0x01FBFFFF +#define XCHAL_INTLEVEL3_ANDBELOW_MASK 0x01FFFFFF +#define XCHAL_INTLEVEL4_ANDBELOW_MASK 0x01FFFFFF +#define XCHAL_INTLEVEL5_ANDBELOW_MASK 0x01FFFFFF +#define XCHAL_INTLEVEL6_ANDBELOW_MASK 0x01FFFFFF +#define XCHAL_INTLEVEL7_ANDBELOW_MASK 0x01FFFFFF + +/* Level of each interrupt: */ +#define XCHAL_INT0_LEVEL 1 +#define XCHAL_INT1_LEVEL 1 +#define XCHAL_INT2_LEVEL 1 +#define XCHAL_INT3_LEVEL 1 +#define XCHAL_INT4_LEVEL 1 +#define XCHAL_INT5_LEVEL 1 +#define XCHAL_INT6_LEVEL 1 +#define XCHAL_INT7_LEVEL 1 +#define XCHAL_INT8_LEVEL 2 +#define XCHAL_INT9_LEVEL 2 +#define XCHAL_INT10_LEVEL 2 +#define XCHAL_INT11_LEVEL 2 +#define XCHAL_INT12_LEVEL 2 +#define XCHAL_INT13_LEVEL 2 +#define XCHAL_INT14_LEVEL 2 +#define XCHAL_INT15_LEVEL 2 +#define XCHAL_INT16_LEVEL 1 +#define XCHAL_INT17_LEVEL 2 +#define XCHAL_INT18_LEVEL 3 +#define XCHAL_INT19_LEVEL 1 +#define XCHAL_INT20_LEVEL 1 +#define XCHAL_INT21_LEVEL 1 +#define XCHAL_INT22_LEVEL 2 +#define XCHAL_INT23_LEVEL 1 +#define XCHAL_INT24_LEVEL 2 +#define XCHAL_DEBUGLEVEL 4 /* debug interrupt level */ +#define XCHAL_HAVE_DEBUG_EXTERN_INT 1 /* OCD external db interrupt */ + +/* Type of each interrupt: */ +#define XCHAL_INT0_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT1_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT2_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT3_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT4_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT5_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT6_TYPE XTHAL_INTTYPE_EXTERN_EDGE +#define XCHAL_INT7_TYPE XTHAL_INTTYPE_EXTERN_EDGE +#define XCHAL_INT8_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT9_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT10_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT11_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT12_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT13_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT14_TYPE XTHAL_INTTYPE_EXTERN_EDGE +#define XCHAL_INT15_TYPE XTHAL_INTTYPE_EXTERN_EDGE +#define XCHAL_INT16_TYPE XTHAL_INTTYPE_TIMER +#define XCHAL_INT17_TYPE XTHAL_INTTYPE_TIMER +#define XCHAL_INT18_TYPE XTHAL_INTTYPE_TIMER +#define XCHAL_INT19_TYPE XTHAL_INTTYPE_WRITE_ERROR +#define XCHAL_INT20_TYPE XTHAL_INTTYPE_PROFILING +#define XCHAL_INT21_TYPE XTHAL_INTTYPE_SOFTWARE +#define XCHAL_INT22_TYPE XTHAL_INTTYPE_SOFTWARE +#define XCHAL_INT23_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT24_TYPE XTHAL_INTTYPE_EXTERN_LEVEL + +/* Masks of interrupts for each type of interrupt: */ +#define XCHAL_INTTYPE_MASK_UNCONFIGURED 0xFE000000 +#define XCHAL_INTTYPE_MASK_EXTERN_LEVEL 0x01803F3F +#define XCHAL_INTTYPE_MASK_EXTERN_EDGE 0x0000C0C0 +#define XCHAL_INTTYPE_MASK_NMI 0x00000000 +#define XCHAL_INTTYPE_MASK_SOFTWARE 0x00600000 +#define XCHAL_INTTYPE_MASK_TIMER 0x00070000 +#define XCHAL_INTTYPE_MASK_WRITE_ERROR 0x00080000 +#define XCHAL_INTTYPE_MASK_DBG_REQUEST 0x00000000 +#define XCHAL_INTTYPE_MASK_BREAKIN 0x00000000 +#define XCHAL_INTTYPE_MASK_TRAX 0x00000000 +#define XCHAL_INTTYPE_MASK_PROFILING 0x00100000 +#define XCHAL_INTTYPE_MASK_IDMA_DONE 0x00000000 +#define XCHAL_INTTYPE_MASK_IDMA_ERR 0x00000000 +#define XCHAL_INTTYPE_MASK_GS_ERR 0x00000000 +#define XCHAL_INTTYPE_MASK_L2_ERR 0x00000000 +#define XCHAL_INTTYPE_MASK_L2_STATUS 0x00000000 +#define XCHAL_INTTYPE_MASK_COR_ECC_ERR 0x00000000 + +/* Interrupt numbers assigned to specific interrupt sources: */ +#define XCHAL_TIMER0_INTERRUPT 16 /* CCOMPARE0 */ +#define XCHAL_TIMER1_INTERRUPT 17 /* CCOMPARE1 */ +#define XCHAL_TIMER2_INTERRUPT 18 /* CCOMPARE2 */ +#define XCHAL_TIMER3_INTERRUPT XTHAL_TIMER_UNCONFIGURED +#define XCHAL_WRITE_ERROR_INTERRUPT 19 +#define XCHAL_PROFILING_INTERRUPT 20 + +/* Interrupt numbers for levels at which only one interrupt is configured: */ +#define XCHAL_INTLEVEL3_NUM 18 +/* (There are many interrupts each at level(s) 1, 2.) */ + + +/* + * External interrupt mapping. + * These macros describe how Xtensa processor interrupt numbers + * (as numbered internally, eg. in INTERRUPT and INTENABLE registers) + * map to external BInterrupt pins, for those interrupts + * configured as external (level-triggered, edge-triggered, or NMI). + * See the Xtensa processor databook for more details. + */ + +/* Core interrupt numbers mapped to each EXTERNAL BInterrupt pin number: */ +#define XCHAL_EXTINT0_NUM 0 /* (intlevel 1) */ +#define XCHAL_EXTINT1_NUM 1 /* (intlevel 1) */ +#define XCHAL_EXTINT2_NUM 2 /* (intlevel 1) */ +#define XCHAL_EXTINT3_NUM 3 /* (intlevel 1) */ +#define XCHAL_EXTINT4_NUM 4 /* (intlevel 1) */ +#define XCHAL_EXTINT5_NUM 5 /* (intlevel 1) */ +#define XCHAL_EXTINT6_NUM 6 /* (intlevel 1) */ +#define XCHAL_EXTINT7_NUM 7 /* (intlevel 1) */ +#define XCHAL_EXTINT8_NUM 8 /* (intlevel 2) */ +#define XCHAL_EXTINT9_NUM 9 /* (intlevel 2) */ +#define XCHAL_EXTINT10_NUM 10 /* (intlevel 2) */ +#define XCHAL_EXTINT11_NUM 11 /* (intlevel 2) */ +#define XCHAL_EXTINT12_NUM 12 /* (intlevel 2) */ +#define XCHAL_EXTINT13_NUM 13 /* (intlevel 2) */ +#define XCHAL_EXTINT14_NUM 14 /* (intlevel 2) */ +#define XCHAL_EXTINT15_NUM 15 /* (intlevel 2) */ +#define XCHAL_EXTINT16_NUM 23 /* (intlevel 1) */ +#define XCHAL_EXTINT17_NUM 24 /* (intlevel 2) */ +/* EXTERNAL BInterrupt pin numbers mapped to each core interrupt number: */ +#define XCHAL_INT0_EXTNUM 0 /* (intlevel 1) */ +#define XCHAL_INT1_EXTNUM 1 /* (intlevel 1) */ +#define XCHAL_INT2_EXTNUM 2 /* (intlevel 1) */ +#define XCHAL_INT3_EXTNUM 3 /* (intlevel 1) */ +#define XCHAL_INT4_EXTNUM 4 /* (intlevel 1) */ +#define XCHAL_INT5_EXTNUM 5 /* (intlevel 1) */ +#define XCHAL_INT6_EXTNUM 6 /* (intlevel 1) */ +#define XCHAL_INT7_EXTNUM 7 /* (intlevel 1) */ +#define XCHAL_INT8_EXTNUM 8 /* (intlevel 2) */ +#define XCHAL_INT9_EXTNUM 9 /* (intlevel 2) */ +#define XCHAL_INT10_EXTNUM 10 /* (intlevel 2) */ +#define XCHAL_INT11_EXTNUM 11 /* (intlevel 2) */ +#define XCHAL_INT12_EXTNUM 12 /* (intlevel 2) */ +#define XCHAL_INT13_EXTNUM 13 /* (intlevel 2) */ +#define XCHAL_INT14_EXTNUM 14 /* (intlevel 2) */ +#define XCHAL_INT15_EXTNUM 15 /* (intlevel 2) */ +#define XCHAL_INT23_EXTNUM 16 /* (intlevel 1) */ +#define XCHAL_INT24_EXTNUM 17 /* (intlevel 2) */ + +#define XCHAL_HAVE_ISB 0 /* No ISB */ +#define XCHAL_ISB_VADDR 0 /* N/A */ +#define XCHAL_HAVE_ITB 0 /* No ITB */ +#define XCHAL_ITB_VADDR 0 /* N/A */ + +#define XCHAL_HAVE_KSL 0 /* Kernel Stack Limit */ +#define XCHAL_HAVE_ISL 0 /* Interrupt Stack Limit */ +#define XCHAL_HAVE_PSL 0 /* Pageable Stack Limit */ + + +/*---------------------------------------------------------------------- + EXCEPTIONS and VECTORS + ----------------------------------------------------------------------*/ + +#define XCHAL_XEA_VERSION 2 /* Xtensa Exception Architecture + number: 1 == XEA1 (until T1050) + 2 == XEA2 (T1040 onwards) + 3 == XEA3 (LX8/NX/SX onwards) + 0 == XEAX (extern) or TX */ +#define XCHAL_HAVE_XEA1 0 /* Exception Architecture 1 */ +#define XCHAL_HAVE_XEA2 1 /* Exception Architecture 2 */ +#define XCHAL_HAVE_XEA3 0 /* Exception Architecture 3 */ +#define XCHAL_HAVE_XEAX 0 /* External Exception Arch. */ +#define XCHAL_HAVE_EXCEPTIONS 1 /* exception option */ +#define XCHAL_HAVE_IMPRECISE_EXCEPTIONS 0 /* imprecise exception option */ +#define XCHAL_EXCCAUSE_NUM 64 /* Number of exceptions */ +#define XCHAL_HAVE_HALT 0 /* halt architecture option */ +#define XCHAL_HAVE_BOOTLOADER 0 /* boot loader (for TX) */ +#define XCHAL_HAVE_MEM_ECC_PARITY 0 /* local memory ECC/parity */ +#define XCHAL_HAVE_VECTOR_SELECT 1 /* relocatable vectors */ +#define XCHAL_HAVE_VECBASE 1 /* relocatable vectors */ +#define XCHAL_VECBASE_RESET_VADDR 0x40000400 /* VECBASE reset value */ +#define XCHAL_VECBASE_RESET_PADDR 0x40000400 +#define XCHAL_RESET_VECBASE_OVERLAP 0 /* UNUSED */ + +#define XCHAL_RESET_VECTOR0_VADDR 0x40000000 +#define XCHAL_RESET_VECTOR0_PADDR 0x40000000 +#define XCHAL_RESET_VECTOR1_VADDR 0x40000640 +#define XCHAL_RESET_VECTOR1_PADDR 0x40000640 +#define XCHAL_RESET_VECTOR_VADDR XCHAL_RESET_VECTOR1_VADDR +#define XCHAL_RESET_VECTOR_PADDR XCHAL_RESET_VECTOR1_PADDR +#define XCHAL_USER_VECOFS 0x000001FC +#define XCHAL_USER_VECTOR_VADDR 0x400005FC +#define XCHAL_USER_VECTOR_PADDR 0x400005FC +#define XCHAL_KERNEL_VECOFS 0x000001DC +#define XCHAL_KERNEL_VECTOR_VADDR 0x400005DC +#define XCHAL_KERNEL_VECTOR_PADDR 0x400005DC +#define XCHAL_DOUBLEEXC_VECOFS 0x0000021C +#define XCHAL_DOUBLEEXC_VECTOR_VADDR 0x4000061C +#define XCHAL_DOUBLEEXC_VECTOR_PADDR 0x4000061C +#define XCHAL_WINDOW_OF4_VECOFS 0x00000000 +#define XCHAL_WINDOW_UF4_VECOFS 0x00000040 +#define XCHAL_WINDOW_OF8_VECOFS 0x00000080 +#define XCHAL_WINDOW_UF8_VECOFS 0x000000C0 +#define XCHAL_WINDOW_OF12_VECOFS 0x00000100 +#define XCHAL_WINDOW_UF12_VECOFS 0x00000140 +#define XCHAL_WINDOW_VECTORS_VADDR 0x40000400 +#define XCHAL_WINDOW_VECTORS_PADDR 0x40000400 +#define XCHAL_INTLEVEL2_VECOFS 0x0000017C +#define XCHAL_INTLEVEL2_VECTOR_VADDR 0x4000057C +#define XCHAL_INTLEVEL2_VECTOR_PADDR 0x4000057C +#define XCHAL_INTLEVEL3_VECOFS 0x0000019C +#define XCHAL_INTLEVEL3_VECTOR_VADDR 0x4000059C +#define XCHAL_INTLEVEL3_VECTOR_PADDR 0x4000059C +#define XCHAL_INTLEVEL4_VECOFS 0x000001BC +#define XCHAL_INTLEVEL4_VECTOR_VADDR 0x400005BC +#define XCHAL_INTLEVEL4_VECTOR_PADDR 0x400005BC +#define XCHAL_DEBUG_VECOFS XCHAL_INTLEVEL4_VECOFS +#define XCHAL_DEBUG_VECTOR_VADDR XCHAL_INTLEVEL4_VECTOR_VADDR +#define XCHAL_DEBUG_VECTOR_PADDR XCHAL_INTLEVEL4_VECTOR_PADDR + + +/*---------------------------------------------------------------------- + DEBUG MODULE + ----------------------------------------------------------------------*/ + +/* Misc */ +#define XCHAL_HAVE_DEBUG_ERI 1 /* ERI to debug module */ +#define XCHAL_HAVE_DEBUG_APB 1 /* APB to debug module */ +#define XCHAL_HAVE_DEBUG_JTAG 1 /* JTAG to debug module */ + +/* On-Chip Debug (OCD) */ +#define XCHAL_HAVE_OCD 1 /* OnChipDebug option */ +#define XCHAL_NUM_IBREAK 2 /* number of IBREAKn regs */ +#define XCHAL_NUM_DBREAK 2 /* number of DBREAKn regs */ +#define XCHAL_HAVE_OCD_DIR_ARRAY 0 /* faster OCD option (to LX4) */ +#define XCHAL_HAVE_OCD_LS32DDR 1 /* L32DDR/S32DDR (faster OCD) */ + +/* TRAX (in core) */ +#define XCHAL_HAVE_TRAX 1 /* TRAX in debug module */ +#define XCHAL_TRAX_MEM_SIZE 4096 /* TRAX memory size in bytes */ +#define XCHAL_TRAX_MEM_SHAREABLE 1 /* start/end regs; ready sig. */ +#define XCHAL_TRAX_ATB_WIDTH 32 /* ATB width (bits), 0=no ATB */ +#define XCHAL_TRAX_TIME_WIDTH 0 /* timestamp bitwidth, 0=none */ + +/* Perf counters */ +#define XCHAL_NUM_PERF_COUNTERS 8 /* performance counters */ + + +/*---------------------------------------------------------------------- + MMU + ----------------------------------------------------------------------*/ + +/* See core-matmap.h header file for more details. */ + +#define XCHAL_HAVE_TLBS 0 /* inverse of HAVE_CACHEATTR */ +#define XCHAL_HAVE_SPANNING_WAY 0 /* one way maps I+D 4GB vaddr */ +#define XCHAL_HAVE_IDENTITY_MAP 1 /* vaddr == paddr always */ +#define XCHAL_HAVE_CACHEATTR 0 /* CACHEATTR register present */ +#define XCHAL_HAVE_MIMIC_CACHEATTR 0 /* region protection */ +#define XCHAL_HAVE_XLT_CACHEATTR 0 /* region prot. w/translation */ +#define XCHAL_HAVE_PTP_MMU 0 /* full MMU (with page table + [autorefill] and protection) + usable for an MMU-based OS */ + +/* If none of the above last 5 are set, it's a custom TLB configuration. */ + +#define XCHAL_MMU_ASID_BITS 0 /* number of bits in ASIDs */ +#define XCHAL_MMU_RINGS 1 /* number of rings (1..4) */ +#define XCHAL_MMU_RING_BITS 0 /* num of bits in RING field */ + +/*---------------------------------------------------------------------- + MPU + ----------------------------------------------------------------------*/ +#define XCHAL_HAVE_MPU 1 +#define XCHAL_MPU_ENTRIES 32 + +#define XCHAL_MPU_ALIGN_REQ 1 /* MPU requires alignment of entries to background map */ +#define XCHAL_MPU_BACKGROUND_ENTRIES 2 /* number of entries in bg map*/ +#define XCHAL_MPU_BG_CACHEADRDIS 0xFF /* default CACHEADRDIS for bg */ + +#define XCHAL_MPU_ALIGN_BITS 12 +#define XCHAL_MPU_ALIGN 4096 + +#endif /* !XTENSA_HAL_NON_PRIVILEGED_ONLY */ + + +#endif /* _XTENSA_CORE_CONFIGURATION_H */ + diff --git a/src/platform/mt8195/include/arch/xtensa/config/core-matmap.h b/src/platform/mt8195/include/arch/xtensa/config/core-matmap.h new file mode 100644 index 000000000000..d6e9558c0eb4 --- /dev/null +++ b/src/platform/mt8195/include/arch/xtensa/config/core-matmap.h @@ -0,0 +1,105 @@ +/* + * xtensa/config/core-matmap.h -- Memory access and translation mapping + * parameters (CHAL) of the Xtensa processor core configuration. + * + * If you are using Xtensa Tools, see (which includes + * this file) for more details. + * + * In the Xtensa processor products released to date, all parameters + * defined in this file are derivable (at least in theory) from + * information contained in the core-isa.h header file. + * In particular, the following core configuration parameters are relevant: + * XCHAL_HAVE_CACHEATTR + * XCHAL_HAVE_MIMIC_CACHEATTR + * XCHAL_HAVE_XLT_CACHEATTR + * XCHAL_HAVE_PTP_MMU + * XCHAL_ITLB_ARF_ENTRIES_LOG2 + * XCHAL_DTLB_ARF_ENTRIES_LOG2 + * XCHAL_DCACHE_IS_WRITEBACK + * XCHAL_ICACHE_SIZE (presence of I-cache) + * XCHAL_DCACHE_SIZE (presence of D-cache) + * XCHAL_HW_VERSION_MAJOR + * XCHAL_HW_VERSION_MINOR + */ + +/* Customer ID=16233; Build=0x89932; Copyright (c) 1999-2020 Tensilica Inc. + + Permission is hereby granted, free of charge, to any person obtaining + a copy of this software and associated documentation files (the + "Software"), to deal in the Software without restriction, including + without limitation the rights to use, copy, modify, merge, publish, + distribute, sublicense, and/or sell copies of the Software, and to + permit persons to whom the Software is furnished to do so, subject to + the following conditions: + + The above copyright notice and this permission notice shall be included + in all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ + + +#ifndef XTENSA_CONFIG_CORE_MATMAP_H +#define XTENSA_CONFIG_CORE_MATMAP_H + + +/*---------------------------------------------------------------------- + CACHE (MEMORY ACCESS) ATTRIBUTES + ----------------------------------------------------------------------*/ +/*---------------------------------------------------------------------- + MPU + ----------------------------------------------------------------------*/ + +/* Mappings for legacy constants where appropriate */ + +#define XCHAL_CA_WRITEBACK (XTHAL_MEM_WRITEBACK | XTHAL_AR_RWXrwx) + +#define XCHAL_CA_WRITEBACK_NOALLOC (XTHAL_MEM_WRITEBACK_NOALLOC | XTHAL_AR_RWXrwx) + +#define XCHAL_CA_WRITETHRU (XTHAL_MEM_WRITETHRU | XTHAL_AR_RWXrwx) + +#define XCHAL_CA_ILLEGAL (XTHAL_AR_NONE | XTHAL_MEM_DEVICE) +#define XCHAL_CA_BYPASS (XTHAL_AR_RWXrwx | XTHAL_MEM_DEVICE) +#define XCHAL_CA_BYPASSBUF (XTHAL_AR_RWXrwx | XTHAL_MEM_DEVICE | XTHAL_MEM_BUFFERABLE) +#define XCHAL_CA_BYPASS_RX (XTHAL_AR_RX | XTHAL_MEM_DEVICE) +#define XCHAL_CA_BYPASS_RW (XTHAL_AR_RW | XTHAL_MEM_DEVICE) +#define XCHAL_CA_BYPASS_R (XTHAL_AR_R | XTHAL_MEM_DEVICE) +#define XCHAL_HAVE_CA_WRITEBACK_NOALLOC 1 + +#define XCHAL_CA_R (XTHAL_AR_R) +#define XCHAL_CA_RX (XTHAL_AR_RX) +#define XCHAL_CA_RW (XTHAL_AR_RW) +#define XCHAL_CA_RWX (XTHAL_AR_RWX) + + +/* + * Contents of MPU background map. + * NOTE: caller must define the XCHAL_MPU_BGMAP() macro (not defined here + * but specified below) before expanding the XCHAL_MPU_BACKGROUND_MAP(s) macro. + * + * XCHAL_MPU_BGMAP(s, vaddr_start, vaddr_last, rights, memtype, x...) + * + * s = passed from XCHAL_MPU_BACKGROUND_MAP(s), eg. to select how to expand + * vaddr_start = first byte of region (always 0 for first entry) + * vaddr_end = last byte of region (always 0xFFFFFFFF for last entry) + * rights = access rights + * memtype = memory type + * x = reserved for future use (0 until then) + */ +/* parasoft-begin-suppress MISRA2012-RULE-20_7 "Macro use model requires s to not be in ()" */ +#define XCHAL_MPU_BACKGROUND_MAP(s) \ + (XCHAL_MPU_BGMAP(s, 0x00000000, 0x7fffffff, 7, 6, 0) \ + XCHAL_MPU_BGMAP(s, 0x80000000, 0xffffffff, 7, 6, 0)) +/* parasoft-end-suppress MISRA2012-RULE-20_7 "Macro use model requires s to not be in ()" */ + + /* end */ + + + +#endif /*XTENSA_CONFIG_CORE_MATMAP_H*/ + diff --git a/src/platform/mt8195/include/arch/xtensa/config/defs.h b/src/platform/mt8195/include/arch/xtensa/config/defs.h new file mode 100644 index 000000000000..23229428bb0b --- /dev/null +++ b/src/platform/mt8195/include/arch/xtensa/config/defs.h @@ -0,0 +1,38 @@ +/* Definitions for Xtensa instructions, types, and protos. */ + +/* Customer ID=16233; Build=0x89932; Copyright (c) 2003-2004 Tensilica Inc. + + Permission is hereby granted, free of charge, to any person obtaining + a copy of this software and associated documentation files (the + "Software"), to deal in the Software without restriction, including + without limitation the rights to use, copy, modify, merge, publish, + distribute, sublicense, and/or sell copies of the Software, and to + permit persons to whom the Software is furnished to do so, subject to + the following conditions: + + The above copyright notice and this permission notice shall be included + in all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ + +/* NOTE: This file exists only for backward compatibility with T1050 + and earlier Xtensa releases. It includes only a subset of the + available header files. */ + +#ifndef _XTENSA_BASE_HEADER +#define _XTENSA_BASE_HEADER + +#ifdef __XTENSA__ + +#include +#include +#include + +#endif /* __XTENSA__ */ +#endif /* !_XTENSA_BASE_HEADER */ diff --git a/src/platform/mt8195/include/arch/xtensa/config/specreg.h b/src/platform/mt8195/include/arch/xtensa/config/specreg.h new file mode 100644 index 000000000000..4961e38f895f --- /dev/null +++ b/src/platform/mt8195/include/arch/xtensa/config/specreg.h @@ -0,0 +1,104 @@ +/* + * Xtensa Special Register symbolic names + */ + +/* $Id: /depot/rel/Homewood/ib.1/Xtensa/SWConfig/hal/specreg.h.tpp#1 $ */ + +/* Customer ID=16233; Build=0x89932; Copyright (c) 1998-2002 Tensilica Inc. + + Permission is hereby granted, free of charge, to any person obtaining + a copy of this software and associated documentation files (the + "Software"), to deal in the Software without restriction, including + without limitation the rights to use, copy, modify, merge, publish, + distribute, sublicense, and/or sell copies of the Software, and to + permit persons to whom the Software is furnished to do so, subject to + the following conditions: + + The above copyright notice and this permission notice shall be included + in all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ + +#ifndef XTENSA_SPECREG_H +#define XTENSA_SPECREG_H + +/* Include these special register bitfield definitions, for historical reasons: */ +#include + + +/* Special registers: */ +#define LBEG 0 +#define LEND 1 +#define LCOUNT 2 +#define SAR 3 +#define BR 4 +#define PREFCTL 40 +#define WINDOWBASE 72 +#define WINDOWSTART 73 +#define MPUENB 90 +#define ERACCESS 95 +#define IBREAKENABLE 96 +#define MEMCTL 97 +#define CACHEADRDIS 98 +#define DDR 104 +#define IBREAKA_0 128 +#define IBREAKA_1 129 +#define DBREAKA_0 144 +#define DBREAKA_1 145 +#define DBREAKC_0 160 +#define DBREAKC_1 161 +#define EPC_1 177 +#define EPC_2 178 +#define EPC_3 179 +#define EPC_4 180 +#define DEPC 192 +#define EPS_2 194 +#define EPS_3 195 +#define EPS_4 196 +#define EXCSAVE_1 209 +#define EXCSAVE_2 210 +#define EXCSAVE_3 211 +#define EXCSAVE_4 212 +#define CPENABLE 224 +#define INTERRUPT 226 +#define INTENABLE 228 +#define PS 230 +#define VECBASE 231 +#define EXCCAUSE 232 +#define DEBUGCAUSE 233 +#define CCOUNT 234 +#define PRID 235 +#define ICOUNT 236 +#define ICOUNTLEVEL 237 +#define EXCVADDR 238 +#define CCOMPARE_0 240 +#define CCOMPARE_1 241 +#define CCOMPARE_2 242 +#define MISC_REG_0 244 +#define MISC_REG_1 245 +#define MISC_REG_2 246 +#define MISC_REG_3 247 + + +/* Special cases (bases of special register series): */ +#define IBREAKA 128 +#define DBREAKA 144 +#define DBREAKC 160 +#define EPC 176 +#define EPS 192 +#define EXCSAVE 208 +#define CCOMPARE 240 + +/* Special names for read-only and write-only interrupt registers: */ +#define INTREAD 226 +#define INTSET 226 +#define INTCLEAR 227 + +#endif /* XTENSA_SPECREG_H */ + diff --git a/src/platform/mt8195/include/arch/xtensa/config/system.h b/src/platform/mt8195/include/arch/xtensa/config/system.h new file mode 100644 index 000000000000..aa462dbdd47b --- /dev/null +++ b/src/platform/mt8195/include/arch/xtensa/config/system.h @@ -0,0 +1,249 @@ +/* + * xtensa/config/system.h -- HAL definitions that are dependent on SYSTEM configuration + * + * NOTE: The location and contents of this file are highly subject to change. + * + * Source for configuration-independent binaries (which link in a + * configuration-specific HAL library) must NEVER include this file. + * The HAL itself has historically included this file in some instances, + * but this is not appropriate either, because the HAL is meant to be + * core-specific but system independent. + */ + +/* Customer ID=16233; Build=0x89932; Copyright (c) 2000-2010 Tensilica Inc. + + Permission is hereby granted, free of charge, to any person obtaining + a copy of this software and associated documentation files (the + "Software"), to deal in the Software without restriction, including + without limitation the rights to use, copy, modify, merge, publish, + distribute, sublicense, and/or sell copies of the Software, and to + permit persons to whom the Software is furnished to do so, subject to + the following conditions: + + The above copyright notice and this permission notice shall be included + in all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ + + +#ifndef XTENSA_CONFIG_SYSTEM_H +#define XTENSA_CONFIG_SYSTEM_H + + +/*---------------------------------------------------------------------- + CONFIGURED SOFTWARE OPTIONS + ----------------------------------------------------------------------*/ + +#define XSHAL_USE_ABSOLUTE_LITERALS 0 /* (sw-only option, whether software uses absolute literals) */ +#define XSHAL_HAVE_TEXT_SECTION_LITERALS 1 /* Set if there is some memory that allows both code and literals. */ + +#define XSHAL_ABI XTHAL_ABI_WINDOWED /* (sw-only option, selected ABI) */ +/* The above maps to one of the following constants: */ +#define XTHAL_ABI_WINDOWED 0 +#define XTHAL_ABI_CALL0 1 + +#define XSHAL_CLIB XTHAL_CLIB_XCLIB /* (sw-only option, selected C library) */ +/* The above maps to one of the following constants: */ +#define XTHAL_CLIB_NEWLIB 0 +#define XTHAL_CLIB_UCLIBC 1 +#define XTHAL_CLIB_XCLIB 2 + +#define XSHAL_USE_FLOATING_POINT 1 + +#define XSHAL_FLOATING_POINT_ABI 1 + +/* SW workarounds enabled for HW errata: */ + +/*---------------------------------------------------------------------- + DEVICE ADDRESSES + ----------------------------------------------------------------------*/ + +/* + * Strange place to find these, but the configuration GUI + * allows moving these around to account for various core + * configurations. Specific boards (and their BSP software) + * will have specific meanings for these components. + */ + +/* I/O Block areas: */ +#define XSHAL_IOBLOCK_CACHED_VADDR 0x70000000 +#define XSHAL_IOBLOCK_CACHED_PADDR 0x70000000 +#define XSHAL_IOBLOCK_CACHED_SIZE 0x0E000000 + +#define XSHAL_IOBLOCK_BYPASS_VADDR 0x90000000 +#define XSHAL_IOBLOCK_BYPASS_PADDR 0x90000000 +#define XSHAL_IOBLOCK_BYPASS_SIZE 0x0E000000 + +/* System ROM: */ + +/* System RAM: */ +#define XSHAL_RAM_VADDR 0x40000000 +#define XSHAL_RAM_PADDR 0x40000000 +#define XSHAL_RAM_VSIZE 0x80000000 +#define XSHAL_RAM_PSIZE 0x80000000 +#define XSHAL_RAM_SIZE XSHAL_RAM_PSIZE +/* Largest available area (free of vectors): */ +#define XSHAL_RAM_AVAIL_VADDR 0x40000640 +#define XSHAL_RAM_AVAIL_VSIZE 0x7FFFF9C0 + +/* + * Shadow system RAM (same device as system RAM, at different address). + * (Emulation boards need this for the SONIC Ethernet driver + * when data caches are configured for writeback mode.) + * NOTE: on full MMU configs, this points to the BYPASS virtual address + * of system RAM, ie. is the same as XSHAL_RAM_* except that virtual + * addresses are viewed through the BYPASS static map rather than + * the CACHED static map. + */ +#define XSHAL_RAM_BYPASS_VADDR 0x20000000 +#define XSHAL_RAM_BYPASS_PADDR 0x20000000 +#define XSHAL_RAM_BYPASS_PSIZE 0x20000000 + +/* Alternate system RAM (different device than system RAM): */ + +/* Some available location in which to place devices in a simulation (eg. XTMP): */ +#define XSHAL_SIMIO_CACHED_VADDR 0xC0000000 +#define XSHAL_SIMIO_BYPASS_VADDR 0xC0000000 +#define XSHAL_SIMIO_PADDR 0xC0000000 +#define XSHAL_SIMIO_SIZE 0x20000000 + + +/*---------------------------------------------------------------------- + * For use by reference testbench exit and diagnostic routines. + */ +#define XSHAL_MAGIC_EXIT 0xdeece000 +#define XSHAL_STL_INFO_LOCATION 0x6c + +/*---------------------------------------------------------------------- + * DEVICE-ADDRESS DEPENDENT... + * + * Values written to CACHEATTR special register (or its equivalent) + * to enable and disable caches in various modes. + *----------------------------------------------------------------------*/ + +/*---------------------------------------------------------------------- + BACKWARD COMPATIBILITY ... + ----------------------------------------------------------------------*/ + +/* + * NOTE: the following two macros are DEPRECATED. Use the latter + * board-specific macros instead, which are specially tuned for the + * particular target environments' memory maps. + */ +#define XSHAL_CACHEATTR_BYPASS XSHAL_XT2000_CACHEATTR_BYPASS /* disable caches in bypass mode */ +#define XSHAL_CACHEATTR_DEFAULT XSHAL_XT2000_CACHEATTR_DEFAULT /* default setting to enable caches (no writeback!) */ + +/*---------------------------------------------------------------------- + GENERIC + ----------------------------------------------------------------------*/ + +/* For the following, a 512MB region is used if it contains a system (PIF) RAM, + * system (PIF) ROM, local memory, or XLMI. */ + +/* These set any unused 512MB region to cache-BYPASS attribute: */ +#define XSHAL_ALLVALID_CACHEATTR_WRITEBACK 0x22444422 /* enable caches in write-back mode */ +#define XSHAL_ALLVALID_CACHEATTR_WRITEALLOC 0x22111122 /* enable caches in write-allocate mode */ +#define XSHAL_ALLVALID_CACHEATTR_WRITETHRU 0x22111122 /* enable caches in write-through mode */ +#define XSHAL_ALLVALID_CACHEATTR_BYPASS 0x22222222 /* disable caches in bypass mode */ +#define XSHAL_ALLVALID_CACHEATTR_DEFAULT XSHAL_ALLVALID_CACHEATTR_WRITEBACK /* default setting to enable caches */ + +/* These set any unused 512MB region to ILLEGAL attribute: */ +#define XSHAL_STRICT_CACHEATTR_WRITEBACK 0xFF4444FF /* enable caches in write-back mode */ +#define XSHAL_STRICT_CACHEATTR_WRITEALLOC 0xFF1111FF /* enable caches in write-allocate mode */ +#define XSHAL_STRICT_CACHEATTR_WRITETHRU 0xFF1111FF /* enable caches in write-through mode */ +#define XSHAL_STRICT_CACHEATTR_BYPASS 0xFF2222FF /* disable caches in bypass mode */ +#define XSHAL_STRICT_CACHEATTR_DEFAULT XSHAL_STRICT_CACHEATTR_WRITEBACK /* default setting to enable caches */ + +/* These set the first 512MB, if unused, to ILLEGAL attribute to help catch + * NULL-pointer dereference bugs; all other unused 512MB regions are set + * to cache-BYPASS attribute: */ +#define XSHAL_TRAPNULL_CACHEATTR_WRITEBACK 0x2244442F /* enable caches in write-back mode */ +#define XSHAL_TRAPNULL_CACHEATTR_WRITEALLOC 0x2211112F /* enable caches in write-allocate mode */ +#define XSHAL_TRAPNULL_CACHEATTR_WRITETHRU 0x2211112F /* enable caches in write-through mode */ +#define XSHAL_TRAPNULL_CACHEATTR_BYPASS 0x2222222F /* disable caches in bypass mode */ +#define XSHAL_TRAPNULL_CACHEATTR_DEFAULT XSHAL_TRAPNULL_CACHEATTR_WRITEBACK /* default setting to enable caches */ + +/*---------------------------------------------------------------------- + ISS (Instruction Set Simulator) SPECIFIC ... + ----------------------------------------------------------------------*/ + +/* For now, ISS defaults to the TRAPNULL settings: */ +#define XSHAL_ISS_CACHEATTR_WRITEBACK XSHAL_TRAPNULL_CACHEATTR_WRITEBACK +#define XSHAL_ISS_CACHEATTR_WRITEALLOC XSHAL_TRAPNULL_CACHEATTR_WRITEALLOC +#define XSHAL_ISS_CACHEATTR_WRITETHRU XSHAL_TRAPNULL_CACHEATTR_WRITETHRU +#define XSHAL_ISS_CACHEATTR_BYPASS XSHAL_TRAPNULL_CACHEATTR_BYPASS +#define XSHAL_ISS_CACHEATTR_DEFAULT XSHAL_TRAPNULL_CACHEATTR_WRITEBACK + +#define XSHAL_ISS_PIPE_REGIONS 0 +#define XSHAL_ISS_SDRAM_REGIONS 0 + + +/*---------------------------------------------------------------------- + XT2000 BOARD SPECIFIC ... + ----------------------------------------------------------------------*/ + +/* For the following, a 512MB region is used if it contains any system RAM, + * system ROM, local memory, XLMI, or other XT2000 board device or memory. + * Regions containing devices are forced to cache-BYPASS mode regardless + * of whether the macro is _WRITEBACK vs. _BYPASS etc. */ + +/* These set any 512MB region unused on the XT2000 to ILLEGAL attribute: */ +#define XSHAL_XT2000_CACHEATTR_WRITEBACK 0xFF42442F /* enable caches in write-back mode */ +#define XSHAL_XT2000_CACHEATTR_WRITEALLOC 0xFF12112F /* enable caches in write-allocate mode */ +#define XSHAL_XT2000_CACHEATTR_WRITETHRU 0xFF12112F /* enable caches in write-through mode */ +#define XSHAL_XT2000_CACHEATTR_BYPASS 0xFF22222F /* disable caches in bypass mode */ +#define XSHAL_XT2000_CACHEATTR_DEFAULT XSHAL_XT2000_CACHEATTR_WRITEBACK /* default setting to enable caches */ + +#define XSHAL_XT2000_PIPE_REGIONS 0x00000000 /* BusInt pipeline regions */ +#define XSHAL_XT2000_SDRAM_REGIONS 0x00000014 /* BusInt SDRAM regions */ + + +/*---------------------------------------------------------------------- + VECTOR INFO AND SIZES + ----------------------------------------------------------------------*/ + +#define XSHAL_VECTORS_PACKED 0 /* UNUSED */ +#define XSHAL_STATIC_VECTOR_SELECT 1 +#define XSHAL_RESET_VECTOR_VADDR 0x40000640 +#define XSHAL_RESET_VECTOR_PADDR 0x40000640 + +/* + * Sizes allocated to vectors by the system (memory map) configuration. + * These sizes are constrained by core configuration (eg. one vector's + * code cannot overflow into another vector) but are dependent on the + * system or board (or LSP) memory map configuration. + * + * Whether or not each vector happens to be in a system ROM is also + * a system configuration matter, sometimes useful, included here also: + */ +#define XSHAL_RESET_VECTOR_SIZE 0x000002E0 +#define XSHAL_RESET_VECTOR_ISROM 0 +#define XSHAL_USER_VECTOR_SIZE 0x0000001C +#define XSHAL_USER_VECTOR_ISROM 0 +#define XSHAL_PROGRAMEXC_VECTOR_SIZE XSHAL_USER_VECTOR_SIZE /* for backward compatibility */ +#define XSHAL_USEREXC_VECTOR_SIZE XSHAL_USER_VECTOR_SIZE /* for backward compatibility */ +#define XSHAL_KERNEL_VECTOR_SIZE 0x0000001C +#define XSHAL_KERNEL_VECTOR_ISROM 0 +#define XSHAL_STACKEDEXC_VECTOR_SIZE XSHAL_KERNEL_VECTOR_SIZE /* for backward compatibility */ +#define XSHAL_KERNELEXC_VECTOR_SIZE XSHAL_KERNEL_VECTOR_SIZE /* for backward compatibility */ +#define XSHAL_DOUBLEEXC_VECTOR_SIZE 0x0000001C +#define XSHAL_DOUBLEEXC_VECTOR_ISROM 0 +#define XSHAL_WINDOW_VECTORS_SIZE 0x00000178 +#define XSHAL_WINDOW_VECTORS_ISROM 0 +#define XSHAL_INTLEVEL2_VECTOR_SIZE 0x0000001C +#define XSHAL_INTLEVEL2_VECTOR_ISROM 0 +#define XSHAL_INTLEVEL3_VECTOR_SIZE 0x0000001C +#define XSHAL_INTLEVEL3_VECTOR_ISROM 0 +#define XSHAL_INTLEVEL4_VECTOR_SIZE 0x0000001C +#define XSHAL_INTLEVEL4_VECTOR_ISROM 0 +#define XSHAL_DEBUG_VECTOR_SIZE XSHAL_INTLEVEL4_VECTOR_SIZE +#define XSHAL_DEBUG_VECTOR_ISROM XSHAL_INTLEVEL4_VECTOR_ISROM + +#endif /*XTENSA_CONFIG_SYSTEM_H*/ + diff --git a/src/platform/mt8195/include/arch/xtensa/config/tie-asm.h b/src/platform/mt8195/include/arch/xtensa/config/tie-asm.h new file mode 100644 index 000000000000..5d3937e9e977 --- /dev/null +++ b/src/platform/mt8195/include/arch/xtensa/config/tie-asm.h @@ -0,0 +1,314 @@ +/* + * tie-asm.h -- compile-time HAL assembler definitions dependent on CORE & TIE + * + * NOTE: This header file is not meant to be included directly. + */ + +/* This header file contains assembly-language definitions (assembly + macros, etc.) for this specific Xtensa processor's TIE extensions + and options. It is customized to this Xtensa processor configuration. + + Customer ID=16233; Build=0x89932; Copyright (c) 1999-2020 Cadence Design Systems Inc. + + Permission is hereby granted, free of charge, to any person obtaining + a copy of this software and associated documentation files (the + "Software"), to deal in the Software without restriction, including + without limitation the rights to use, copy, modify, merge, publish, + distribute, sublicense, and/or sell copies of the Software, and to + permit persons to whom the Software is furnished to do so, subject to + the following conditions: + + The above copyright notice and this permission notice shall be included + in all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ + +#ifndef _XTENSA_CORE_TIE_ASM_H +#define _XTENSA_CORE_TIE_ASM_H + +#include + +/* Selection parameter values for save-area save/restore macros: */ +/* Option vs. TIE: */ +#define XTHAL_SAS_TIE 0x0001 /* custom extension or coprocessor */ +#define XTHAL_SAS_OPT 0x0002 /* optional (and not a coprocessor) */ +#define XTHAL_SAS_ANYOT 0x0003 /* both of the above */ +/* Whether used automatically by compiler: */ +#define XTHAL_SAS_NOCC 0x0004 /* not used by compiler w/o special opts/code */ +#define XTHAL_SAS_CC 0x0008 /* used by compiler without special opts/code */ +#define XTHAL_SAS_ANYCC 0x000C /* both of the above */ +/* ABI handling across function calls: */ +#define XTHAL_SAS_CALR 0x0010 /* caller-saved */ +#define XTHAL_SAS_CALE 0x0020 /* callee-saved */ +#define XTHAL_SAS_GLOB 0x0040 /* global across function calls (in thread) */ +#define XTHAL_SAS_ANYABI 0x0070 /* all of the above three */ +/* Misc */ +#define XTHAL_SAS_ALL 0xFFFF /* include all default NCP contents */ +#define XTHAL_SAS3(optie, ccuse, abi) (((optie) & XTHAL_SAS_ANYOT) \ + | ((ccuse) & XTHAL_SAS_ANYCC) \ + | ((abi) & XTHAL_SAS_ANYABI)) + + + /* + * Macro to store all non-coprocessor (extra) custom TIE and optional state + * (not including zero-overhead loop registers). + * Required parameters: + * ptr Save area pointer address register (clobbered) + * (register must contain a 4 byte aligned address). + * at1..at4 Four temporary address registers (first XCHAL_NCP_NUM_ATMPS + * registers are clobbered, the remaining are unused). + * Optional parameters: + * continue If macro invoked as part of a larger store sequence, set to 1 + * if this is not the first in the sequence. Defaults to 0. + * ofs Offset from start of larger sequence (from value of first ptr + * in sequence) at which to store. Defaults to next available space + * (or 0 if is 0). + * select Select what category(ies) of registers to store, as a bitmask + * (see XTHAL_SAS_xxx constants). Defaults to all registers. + * alloc Select what category(ies) of registers to allocate; if any + * category is selected here that is not in , space for + * the corresponding registers is skipped without doing any load. + */ + .macro xchal_ncp_load ptr at1 at2 at3 at4 continue = 0 ofs = -1 select = XTHAL_SAS_ALL alloc = 0 + xchal_sa_start \continue, \ofs + /* Optional global registers used by default by the compiler: */ + .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~(\select) + xchal_sa_align \ptr, 0, 1016, 4, 4 + l32i \at1, \ptr, .Lxchal_ofs_+0 + wur.threadptr \at1 /* threadptr option */ + .set .Lxchal_ofs_, .Lxchal_ofs_ + 4 + .elseif ((XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~(\alloc)) == 0 + xchal_sa_align \ptr, 0, 1016, 4, 4 + .set .Lxchal_ofs_, .Lxchal_ofs_ + 4 + .endif + /* Optional caller-saved registers not used by default by the compiler: */ + .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select) + xchal_sa_align \ptr, 0, 1016, 4, 4 + l32i \at1, \ptr, .Lxchal_ofs_+0 + wsr.br \at1 /* boolean option */ + .set .Lxchal_ofs_, .Lxchal_ofs_ + 4 + .elseif ((XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0 + xchal_sa_align \ptr, 0, 1016, 4, 4 + .set .Lxchal_ofs_, .Lxchal_ofs_ + 4 + .endif + .endm /* xchal_ncp_load */ + + +#define XCHAL_NCP_NUM_ATMPS 1 + + /* + * Macro to store the state of TIE coprocessor AudioEngineLX. + * Required parameters: + * ptr Save area pointer address register (clobbered) + * (register must contain a 8 byte aligned address). + * at1..at4 Four temporary address registers (first XCHAL_CP1_NUM_ATMPS + * registers are clobbered, the remaining are unused). + * Optional parameters are the same as for xchal_ncp_store. + */ +#define xchal_cp_AudioEngineLX_store xchal_cp1_store + .macro xchal_cp1_store ptr at1 at2 at3 at4 continue = 0 ofs = -1 select = XTHAL_SAS_ALL alloc = 0 + xchal_sa_start \continue, \ofs + /* Custom caller-saved registers not used by default by the compiler: */ + .ifeq (XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select) + xchal_sa_align \ptr, 0, 0, 8, 8 + ae_s64.i aed0, \ptr, .Lxchal_ofs_+40 + ae_s64.i aed1, \ptr, .Lxchal_ofs_+48 + ae_s64.i aed2, \ptr, .Lxchal_ofs_+56 + addi.a \ptr, \ptr, 64 + ae_s64.i aed3, \ptr, .Lxchal_ofs_+0 + ae_s64.i aed4, \ptr, .Lxchal_ofs_+8 + ae_s64.i aed5, \ptr, .Lxchal_ofs_+16 + ae_s64.i aed6, \ptr, .Lxchal_ofs_+24 + ae_s64.i aed7, \ptr, .Lxchal_ofs_+32 + ae_s64.i aed8, \ptr, .Lxchal_ofs_+40 + ae_s64.i aed9, \ptr, .Lxchal_ofs_+48 + ae_s64.i aed10, \ptr, .Lxchal_ofs_+56 + addi.a \ptr, \ptr, 64 + ae_s64.i aed11, \ptr, .Lxchal_ofs_+0 + ae_s64.i aed12, \ptr, .Lxchal_ofs_+8 + ae_s64.i aed13, \ptr, .Lxchal_ofs_+16 + ae_s64.i aed14, \ptr, .Lxchal_ofs_+24 + ae_s64.i aed15, \ptr, .Lxchal_ofs_+32 + ae_movae \at1, aep0 + s8i \at1, \ptr, .Lxchal_ofs_+40 + ae_movae \at1, aep1 + s8i \at1, \ptr, .Lxchal_ofs_+41 + ae_movae \at1, aep2 + s8i \at1, \ptr, .Lxchal_ofs_+42 + ae_movae \at1, aep3 + s8i \at1, \ptr, .Lxchal_ofs_+43 + ae_salign64.i u0, \ptr, .Lxchal_ofs_+48 + ae_salign64.i u1, \ptr, .Lxchal_ofs_+56 + addi.a \ptr, \ptr, 64 + ae_salign64.i u2, \ptr, .Lxchal_ofs_+0 + ae_salign64.i u3, \ptr, .Lxchal_ofs_+8 + addi.a \ptr, \ptr, -192 + ae_movvfcrfsr aed0 /* ureg FCR_FSR */ + ae_s64.i aed0, \ptr, .Lxchal_ofs_+0 + 0 + rur.ae_ovf_sar \at1 /* ureg 240 */ + s32i \at1, \ptr, .Lxchal_ofs_+8 + rur.ae_bithead \at1 /* ureg 241 */ + s32i \at1, \ptr, .Lxchal_ofs_+12 + rur.ae_ts_fts_bu_bp \at1 /* ureg 242 */ + s32i \at1, \ptr, .Lxchal_ofs_+16 + rur.ae_cw_sd_no \at1 /* ureg 243 */ + s32i \at1, \ptr, .Lxchal_ofs_+20 + rur.ae_cbegin0 \at1 /* ureg 246 */ + s32i \at1, \ptr, .Lxchal_ofs_+24 + rur.ae_cend0 \at1 /* ureg 247 */ + s32i \at1, \ptr, .Lxchal_ofs_+28 + rur.ae_cbegin1 \at1 /* ureg 248 */ + s32i \at1, \ptr, .Lxchal_ofs_+32 + rur.ae_cend1 \at1 /* ureg 249 */ + s32i \at1, \ptr, .Lxchal_ofs_+36 + .set .Lxchal_ofs_, .Lxchal_ofs_ + 208 + .elseif ((XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0 + xchal_sa_align \ptr, 0, 0, 8, 8 + .set .Lxchal_ofs_, .Lxchal_ofs_ + 208 + .endif + .endm /* xchal_cp1_store */ + + /* + * Macro to load the state of TIE coprocessor AudioEngineLX. + * Required parameters: + * ptr Save area pointer address register (clobbered) + * (register must contain a 8 byte aligned address). + * at1..at4 Four temporary address registers (first XCHAL_CP1_NUM_ATMPS + * registers are clobbered, the remaining are unused). + * Optional parameters are the same as for xchal_ncp_load. + */ +#define xchal_cp_AudioEngineLX_load xchal_cp1_load + .macro xchal_cp1_load ptr at1 at2 at3 at4 continue = 0 ofs = -1 select = XTHAL_SAS_ALL alloc = 0 + xchal_sa_start \continue, \ofs + /* Custom caller-saved registers not used by default by the compiler: */ + .ifeq (XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select) + xchal_sa_align \ptr, 0, 0, 8, 8 + ae_l64.i aed0, \ptr, .Lxchal_ofs_+0 + 0 /* ureg FCR_FSR */ + ae_movfcrfsrv aed0 + l32i \at1, \ptr, .Lxchal_ofs_+8 + wur.ae_ovf_sar \at1 /* ureg 240 */ + l32i \at1, \ptr, .Lxchal_ofs_+12 + wur.ae_bithead \at1 /* ureg 241 */ + l32i \at1, \ptr, .Lxchal_ofs_+16 + wur.ae_ts_fts_bu_bp \at1 /* ureg 242 */ + l32i \at1, \ptr, .Lxchal_ofs_+20 + wur.ae_cw_sd_no \at1 /* ureg 243 */ + l32i \at1, \ptr, .Lxchal_ofs_+24 + wur.ae_cbegin0 \at1 /* ureg 246 */ + l32i \at1, \ptr, .Lxchal_ofs_+28 + wur.ae_cend0 \at1 /* ureg 247 */ + l32i \at1, \ptr, .Lxchal_ofs_+32 + wur.ae_cbegin1 \at1 /* ureg 248 */ + l32i \at1, \ptr, .Lxchal_ofs_+36 + wur.ae_cend1 \at1 /* ureg 249 */ + ae_l64.i aed0, \ptr, .Lxchal_ofs_+40 + ae_l64.i aed1, \ptr, .Lxchal_ofs_+48 + ae_l64.i aed2, \ptr, .Lxchal_ofs_+56 + addi.a \ptr, \ptr, 64 + ae_l64.i aed3, \ptr, .Lxchal_ofs_+0 + ae_l64.i aed4, \ptr, .Lxchal_ofs_+8 + ae_l64.i aed5, \ptr, .Lxchal_ofs_+16 + ae_l64.i aed6, \ptr, .Lxchal_ofs_+24 + ae_l64.i aed7, \ptr, .Lxchal_ofs_+32 + ae_l64.i aed8, \ptr, .Lxchal_ofs_+40 + ae_l64.i aed9, \ptr, .Lxchal_ofs_+48 + ae_l64.i aed10, \ptr, .Lxchal_ofs_+56 + addi.a \ptr, \ptr, 64 + ae_l64.i aed11, \ptr, .Lxchal_ofs_+0 + ae_l64.i aed12, \ptr, .Lxchal_ofs_+8 + ae_l64.i aed13, \ptr, .Lxchal_ofs_+16 + ae_l64.i aed14, \ptr, .Lxchal_ofs_+24 + ae_l64.i aed15, \ptr, .Lxchal_ofs_+32 + addi.a \ptr, \ptr, 40 + l8ui \at1, \ptr, .Lxchal_ofs_+0 + ae_movea aep0, \at1 + l8ui \at1, \ptr, .Lxchal_ofs_+1 + ae_movea aep1, \at1 + l8ui \at1, \ptr, .Lxchal_ofs_+2 + ae_movea aep2, \at1 + l8ui \at1, \ptr, .Lxchal_ofs_+3 + ae_movea aep3, \at1 + addi.a \ptr, \ptr, 8 + ae_lalign64.i u0, \ptr, .Lxchal_ofs_+0 + ae_lalign64.i u1, \ptr, .Lxchal_ofs_+8 + ae_lalign64.i u2, \ptr, .Lxchal_ofs_+16 + ae_lalign64.i u3, \ptr, .Lxchal_ofs_+24 + .set .Lxchal_pofs_, .Lxchal_pofs_ + 176 + .set .Lxchal_ofs_, .Lxchal_ofs_ + 32 + .elseif ((XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0 + xchal_sa_align \ptr, 0, 0, 8, 8 + .set .Lxchal_ofs_, .Lxchal_ofs_ + 208 + .endif + .endm /* xchal_cp1_load */ + +#define XCHAL_CP1_NUM_ATMPS 1 +#define XCHAL_SA_NUM_ATMPS 1 + + /* Empty macros for unconfigured coprocessors: */ + .macro xchal_cp0_store p a b c d continue = 0 ofs = -1 select = -1 ; .endm + .macro xchal_cp0_load p a b c d continue = 0 ofs = -1 select = -1 ; .endm + .macro xchal_cp2_store p a b c d continue = 0 ofs = -1 select = -1 ; .endm + .macro xchal_cp2_load p a b c d continue = 0 ofs = -1 select = -1 ; .endm + .macro xchal_cp3_store p a b c d continue = 0 ofs = -1 select = -1 ; .endm + .macro xchal_cp3_load p a b c d continue = 0 ofs = -1 select = -1 ; .endm + .macro xchal_cp4_store p a b c d continue = 0 ofs = -1 select = -1 ; .endm + .macro xchal_cp4_load p a b c d continue = 0 ofs = -1 select = -1 ; .endm + .macro xchal_cp5_store p a b c d continue = 0 ofs = -1 select = -1 ; .endm + .macro xchal_cp5_load p a b c d continue = 0 ofs = -1 select = -1 ; .endm + .macro xchal_cp6_store p a b c d continue = 0 ofs = -1 select = -1 ; .endm + .macro xchal_cp6_load p a b c d continue = 0 ofs = -1 select = -1 ; .endm + .macro xchal_cp7_store p a b c d continue = 0 ofs = -1 select = -1 ; .endm + .macro xchal_cp7_load p a b c d continue = 0 ofs = -1 select = -1 ; .endm + +#endif /*_XTENSA_CORE_TIE_ASM_H*/ + diff --git a/src/platform/mt8195/include/arch/xtensa/config/tie.h b/src/platform/mt8195/include/arch/xtensa/config/tie.h new file mode 100644 index 000000000000..e7e8a6847e43 --- /dev/null +++ b/src/platform/mt8195/include/arch/xtensa/config/tie.h @@ -0,0 +1,191 @@ +/* + * tie.h -- compile-time HAL definitions dependent on CORE & TIE configuration + * + * NOTE: This header file is not meant to be included directly. + */ + +/* This header file describes this specific Xtensa processor's TIE extensions + that extend basic Xtensa core functionality. It is customized to this + Xtensa processor configuration. + + Customer ID=16233; Build=0x89932; Copyright (c) 1999-2020 Cadence Design Systems Inc. + + Permission is hereby granted, free of charge, to any person obtaining + a copy of this software and associated documentation files (the + "Software"), to deal in the Software without restriction, including + without limitation the rights to use, copy, modify, merge, publish, + distribute, sublicense, and/or sell copies of the Software, and to + permit persons to whom the Software is furnished to do so, subject to + the following conditions: + + The above copyright notice and this permission notice shall be included + in all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ + +#ifndef XTENSA_CORE_TIE_H +#define XTENSA_CORE_TIE_H + +/* parasoft-begin-suppress ALL "This file not MISRA checked." */ + +#define XCHAL_CP_NUM 1 /* number of coprocessors */ +#define XCHAL_CP_MAX 2 /* max CP ID + 1 (0 if none) */ +#define XCHAL_CP_MASK 0x02 /* bitmask of all CPs by ID */ +#define XCHAL_CP_PORT_MASK 0x00 /* bitmask of only port CPs */ + +/* Basic parameters of each coprocessor: */ +#define XCHAL_CP1_NAME "AudioEngineLX" +#define XCHAL_CP1_IDENT AudioEngineLX +#define XCHAL_CP1_SA_SIZE 208 /* size of state save area */ +#define XCHAL_CP1_SA_ALIGN 8 /* min alignment of save area */ +#define XCHAL_CP_ID_AUDIOENGINELX 1 /* coprocessor ID (0..7) */ + +/* Filler info for unassigned coprocessors, to simplify arrays etc: */ +#define XCHAL_CP0_SA_SIZE 0 +#define XCHAL_CP0_SA_ALIGN 1 +#define XCHAL_CP2_SA_SIZE 0 +#define XCHAL_CP2_SA_ALIGN 1 +#define XCHAL_CP3_SA_SIZE 0 +#define XCHAL_CP3_SA_ALIGN 1 +#define XCHAL_CP4_SA_SIZE 0 +#define XCHAL_CP4_SA_ALIGN 1 +#define XCHAL_CP5_SA_SIZE 0 +#define XCHAL_CP5_SA_ALIGN 1 +#define XCHAL_CP6_SA_SIZE 0 +#define XCHAL_CP6_SA_ALIGN 1 +#define XCHAL_CP7_SA_SIZE 0 +#define XCHAL_CP7_SA_ALIGN 1 + +/* Save area for non-coprocessor optional and custom (TIE) state: */ +#define XCHAL_NCP_SA_SIZE 8 +#define XCHAL_NCP_SA_ALIGN 4 + +/* Total save area for optional and custom state (NCP + CPn): */ +#define XCHAL_TOTAL_SA_SIZE 224 /* with 16-byte align padding */ +#define XCHAL_TOTAL_SA_ALIGN 8 /* actual minimum alignment */ + +/* + * Detailed contents of save areas. + * NOTE: caller must define the XCHAL_SA_REG macro (not defined here) + * before expanding the XCHAL_xxx_SA_LIST() macros. + * + * XCHAL_SA_REG(s,ccused,abikind,kind,opt,name,galign,align,asize, + * dbnum,base,regnum,bitsz,gapsz,reset,x...) + * + * s = passed from XCHAL_*_LIST(s), eg. to select how to expand + * ccused = set if used by compiler without special options or code + * abikind = 0 (caller-saved), 1 (callee-saved), or 2 (thread-global) + * kind = 0 (special reg), 1 (TIE user reg), or 2 (TIE regfile reg) + * opt = 0 (custom TIE extension or coprocessor), or 1 (optional reg) + * name = lowercase reg name (no quotes) + * galign = group byte alignment (power of 2) (galign >= align) + * align = register byte alignment (power of 2) + * asize = allocated size in bytes (asize*8 == bitsz + gapsz + padsz) + * (not including any pad bytes required to galign this or next reg) + * dbnum = unique target number f/debug (see ) + * base = reg shortname w/o index (or sr=special, ur=TIE user reg) + * regnum = reg index in regfile, or special/TIE-user reg number + * bitsz = number of significant bits (regfile width, or ur/sr mask bits) + * gapsz = intervening bits, if bitsz bits not stored contiguously + * (padsz = pad bits at end [TIE regfile] or at msbits [ur,sr] of asize) + * reset = register reset value (or 0 if undefined at reset) + * x = reserved for future use (0 until then) + * + * To filter out certain registers, e.g. to expand only the non-global + * registers used by the compiler, you can do something like this: + * + * #define XCHAL_SA_REG(s,ccused,p...) SELCC##ccused(p) + * #define SELCC0(p...) + * #define SELCC1(abikind,p...) SELAK##abikind(p) + * #define SELAK0(p...) REG(p) + * #define SELAK1(p...) REG(p) + * #define SELAK2(p...) + * #define REG(kind,tie,name,galn,aln,asz,csz,dbnum,base,rnum,bsz,rst,x...) \ + * ...what you want to expand... + */ + +#define XCHAL_NCP_SA_NUM 2 +#define XCHAL_NCP_SA_LIST(s) \ + (XCHAL_SA_REG(s, 1, 2, 1, 1, threadptr, 4, 4, 4, 0x03E7, ur, 231, 32, 0, 0, 0) \ + XCHAL_SA_REG(s, 0, 0, 0, 1, br, 4, 4, 4, 0x0204, sr, 4, 16, 0, 0, 0)) + +#define XCHAL_CP0_SA_NUM 0 +#define XCHAL_CP0_SA_LIST(s) /* empty */ + +#define XCHAL_CP1_SA_NUM 33 +#define XCHAL_CP1_SA_LIST(s) \ + (XCHAL_SA_REG(s, 0, 0, 1, 0, fcr_fsr, 8, 8, 8, 0x1019, ur, -1, 7, 0, 0, 0) \ + XCHAL_SA_REG(s, 0, 0, 1, 0, ae_ovf_sar, 4, 4, 4, 0x03F0, ur, 240, 15, 0, 0, 0) \ + XCHAL_SA_REG(s, 0, 0, 1, 0, ae_bithead, 4, 4, 4, 0x03F1, ur, 241, 32, 0, 0, 0) \ + XCHAL_SA_REG(s, 0, 0, 1, 0, ae_ts_fts_bu_bp, 4, 4, 4, 0x03F2, ur, 242, 16, 0, 0, 0) \ + XCHAL_SA_REG(s, 0, 0, 1, 0, ae_cw_sd_no, 4, 4, 4, 0x03F3, ur, 243, 29, 0, 0, 0) \ + XCHAL_SA_REG(s, 0, 0, 1, 0, ae_cbegin0, 4, 4, 4, 0x03F6, ur, 246, 32, 0, 0, 0) \ + XCHAL_SA_REG(s, 0, 0, 1, 0, ae_cend0, 4, 4, 4, 0x03F7, ur, 247, 32, 0, 0, 0) \ + XCHAL_SA_REG(s, 0, 0, 1, 0, ae_cbegin1, 4, 4, 4, 0x03F8, ur, 248, 32, 0, 0, 0) \ + XCHAL_SA_REG(s, 0, 0, 1, 0, ae_cend1, 4, 4, 4, 0x03F9, ur, 249, 32, 0, 0, 0) \ + XCHAL_SA_REG(s, 0, 0, 2, 0, aed0, 8, 8, 8, 0x1000, aed, 0, 64, 0, 0, 0) \ + XCHAL_SA_REG(s, 0, 0, 2, 0, aed1, 8, 8, 8, 0x1001, aed, 1, 64, 0, 0, 0) \ + XCHAL_SA_REG(s, 0, 0, 2, 0, aed2, 8, 8, 8, 0x1002, aed, 2, 64, 0, 0, 0) \ + XCHAL_SA_REG(s, 0, 0, 2, 0, aed3, 8, 8, 8, 0x1003, aed, 3, 64, 0, 0, 0) \ + XCHAL_SA_REG(s, 0, 0, 2, 0, aed4, 8, 8, 8, 0x1004, aed, 4, 64, 0, 0, 0) \ + XCHAL_SA_REG(s, 0, 0, 2, 0, aed5, 8, 8, 8, 0x1005, aed, 5, 64, 0, 0, 0) \ + XCHAL_SA_REG(s, 0, 0, 2, 0, aed6, 8, 8, 8, 0x1006, aed, 6, 64, 0, 0, 0) \ + XCHAL_SA_REG(s, 0, 0, 2, 0, aed7, 8, 8, 8, 0x1007, aed, 7, 64, 0, 0, 0) \ + XCHAL_SA_REG(s, 0, 0, 2, 0, aed8, 8, 8, 8, 0x1008, aed, 8, 64, 0, 0, 0) \ + XCHAL_SA_REG(s, 0, 0, 2, 0, aed9, 8, 8, 8, 0x1009, aed, 9, 64, 0, 0, 0) \ + XCHAL_SA_REG(s, 0, 0, 2, 0, aed10, 8, 8, 8, 0x100A, aed, 10, 64, 0, 0, 0) \ + XCHAL_SA_REG(s, 0, 0, 2, 0, aed11, 8, 8, 8, 0x100B, aed, 11, 64, 0, 0, 0) \ + XCHAL_SA_REG(s, 0, 0, 2, 0, aed12, 8, 8, 8, 0x100C, aed, 12, 64, 0, 0, 0) \ + XCHAL_SA_REG(s, 0, 0, 2, 0, aed13, 8, 8, 8, 0x100D, aed, 13, 64, 0, 0, 0) \ + XCHAL_SA_REG(s, 0, 0, 2, 0, aed14, 8, 8, 8, 0x100E, aed, 14, 64, 0, 0, 0) \ + XCHAL_SA_REG(s, 0, 0, 2, 0, aed15, 8, 8, 8, 0x100F, aed, 15, 64, 0, 0, 0) \ + XCHAL_SA_REG(s, 0, 0, 2, 0, aep0, 1, 1, 1, 0x1014, aep, 0, 8, 0, 0, 0) \ + XCHAL_SA_REG(s, 0, 0, 2, 0, aep1, 1, 1, 1, 0x1015, aep, 1, 8, 0, 0, 0) \ + XCHAL_SA_REG(s, 0, 0, 2, 0, aep2, 1, 1, 1, 0x1016, aep, 2, 8, 0, 0, 0) \ + XCHAL_SA_REG(s, 0, 0, 2, 0, aep3, 1, 1, 1, 0x1017, aep, 3, 8, 0, 0, 0) \ + XCHAL_SA_REG(s, 0, 0, 2, 0, u0, 8, 8, 8, 0x1010, u, 0, 64, 0, 0, 0) \ + XCHAL_SA_REG(s, 0, 0, 2, 0, u1, 8, 8, 8, 0x1011, u, 1, 64, 0, 0, 0) \ + XCHAL_SA_REG(s, 0, 0, 2, 0, u2, 8, 8, 8, 0x1012, u, 2, 64, 0, 0, 0) \ + XCHAL_SA_REG(s, 0, 0, 2, 0, u3, 8, 8, 8, 0x1013, u, 3, 64, 0, 0, 0)) + +#define XCHAL_CP2_SA_NUM 0 +#define XCHAL_CP2_SA_LIST(s) /* empty */ + +#define XCHAL_CP3_SA_NUM 0 +#define XCHAL_CP3_SA_LIST(s) /* empty */ + +#define XCHAL_CP4_SA_NUM 0 +#define XCHAL_CP4_SA_LIST(s) /* empty */ + +#define XCHAL_CP5_SA_NUM 0 +#define XCHAL_CP5_SA_LIST(s) /* empty */ + +#define XCHAL_CP6_SA_NUM 0 +#define XCHAL_CP6_SA_LIST(s) /* empty */ + +#define XCHAL_CP7_SA_NUM 0 +#define XCHAL_CP7_SA_LIST(s) /* empty */ + +/* Byte length of instruction from its first nibble (op0 field), per FLIX. */ +/* (not available, must use XCHAL_BYTE0_FORMAT_LENGTHS for this processor) */ +/* Byte length of instruction from its first byte, per FLIX. */ +#define XCHAL_BYTE0_FORMAT_LENGTHS \ + (3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 6, 11, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 6, 11,\ + 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 6, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 6, 11,\ + 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 6, 11, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 6, 11,\ + 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 6, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 6, 11,\ + 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 6, 11, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 6, 11,\ + 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 6, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 6, 11,\ + 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 6, 11, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 6, 11,\ + 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 6, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 6, 11) + +/* parasoft-end-suppress ALL "This file not MISRA checked." */ + +#endif /* XTENSA_CORE_TIE_H */ + From e7e6df082232c522d1b13e0a2e7594d094a3ed97 Mon Sep 17 00:00:00 2001 From: Allen-KH Cheng Date: Fri, 27 Aug 2021 14:21:05 +0800 Subject: [PATCH 02/15] configs: mtk: add default config for mt8195 Add default config for mt8195 platform. Signed-off-by: YC Hung Signed-off-by: Allen-KH Cheng --- src/arch/xtensa/configs/mt8195_defconfig | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) create mode 100644 src/arch/xtensa/configs/mt8195_defconfig diff --git a/src/arch/xtensa/configs/mt8195_defconfig b/src/arch/xtensa/configs/mt8195_defconfig new file mode 100644 index 000000000000..3e6769d58901 --- /dev/null +++ b/src/arch/xtensa/configs/mt8195_defconfig @@ -0,0 +1,17 @@ +CONFIG_MT8195=y +CONFIG_CORE_COUNT=1 +CONFIG_XT_VIRTUAL_OPS=1 +CONFIG_COMP_VOLUME=y +CONFIG_COMP_SRC=n +CONFIG_COMP_FIR=n +CONFIG_COMP_IIR=n +CONFIG_COMP_DCBLOCK=n +CONFIG_COMP_TDFB=n +CONFIG_COMP_TONE=n +CONFIG_COMP_MIXER=n +CONFIG_COMP_MUX=n +CONFIG_COMP_SWITCH=n +CONFIG_COMP_KPB=n +CONFIG_COMP_SEL=n +CONFIG_COMP_ASRC=n + From a9d5477fcb3a01e7d31b202bc6d14dbda53c25f4 Mon Sep 17 00:00:00 2001 From: Allen-KH Cheng Date: Fri, 27 Aug 2021 14:21:40 +0800 Subject: [PATCH 03/15] drivers: mtk: add drivers for mt8195 Add irq, ipc and timer drivers for mtk mt8195 About mt8195: Two domains of IRQ: IRQ_EXT_DOMAIN0 and IRQ_EXT_DOMAIN1 IRQ num: 25 interrupts IPC: use mbx0 and mbx1 to transfer ipc msg Signed-off-by: YC Hung Signed-off-by: Allen-KH Cheng --- src/drivers/mediatek/mt8195/interrupt.c | 266 ++++++++++++++++++++++++ src/drivers/mediatek/mt8195/ipc.c | 156 ++++++++++++++ src/drivers/mediatek/mt8195/timer.c | 104 +++++++++ 3 files changed, 526 insertions(+) create mode 100644 src/drivers/mediatek/mt8195/interrupt.c create mode 100644 src/drivers/mediatek/mt8195/ipc.c create mode 100644 src/drivers/mediatek/mt8195/timer.c diff --git a/src/drivers/mediatek/mt8195/interrupt.c b/src/drivers/mediatek/mt8195/interrupt.c new file mode 100644 index 000000000000..6b49387fa6cc --- /dev/null +++ b/src/drivers/mediatek/mt8195/interrupt.c @@ -0,0 +1,266 @@ +// SPDX-License-Identifier: BSD-3-Clause +// +// Copyright(c) 2021 Mediatek +// +// Author: Allen-KH Cheng + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* fa00558c-d653-4851-a03a-b21f125a9524 */ +DECLARE_SOF_UUID("irq-mt8195", irq_mt8195_uuid, 0xfa00558c, 0xd653, 0x4851, + 0xa0, 0x3a, 0xb2, 0x1f, 0x12, 0x5a, 0x95, 0x24); + +DECLARE_TR_CTX(int_tr, SOF_UUID(irq_mt8195_uuid), LOG_LEVEL_INFO); + +/* os timer reg value * 77ns 13M os timer + * 1 ms: 12987* 1.5ms: 19436 + * 2 ms: 25974* 3 ms: 38961 + */ + +static void irq_mask_all(void) +{ + io_reg_update_bits(RG_DSP_IRQ_EN, 0xffffffff, 0x0); + io_reg_update_bits(DSP_IRQ_EN, 0xffffffff, 0x0); +} + +static void mtk_irq_mask(struct irq_desc *desc, uint32_t irq, unsigned int core) +{ + int32_t in_irq, level; + + if (!desc) { + level = GET_INTLEVEL(irq); + in_irq = GET_INTERRUPT_ID(irq); + if (level > MAX_IRQ_NUM) { + tr_err(&int_tr, "Invalid interrupt %d", irq); + return; + } + + io_reg_update_bits(RG_DSP_IRQ_EN, BIT(in_irq), 0x0); + } else { + switch (desc->irq) { + case IRQ_EXT_DOMAIN0: + io_reg_update_bits(RG_DSP_IRQ_EN, BIT(irq + IRQ_EXT_DOMAIN0_OFFSET), 0x0); + break; + case IRQ_EXT_DOMAIN1: + io_reg_update_bits(DSP_IRQ_EN, BIT(irq), 0x0); + break; + default: + tr_err(&int_tr, "Invalid interrupt %d", desc->irq); + return; + } + } +} + +static void mtk_irq_unmask(struct irq_desc *desc, uint32_t irq, unsigned int core) +{ + int32_t in_irq, level; + + if (!desc) { + level = GET_INTLEVEL(irq); + in_irq = GET_INTERRUPT_ID(irq); + if (level > MAX_IRQ_NUM) { + tr_err(&int_tr, "Invalid interrupt %d", irq); + return; + } + + io_reg_update_bits(RG_DSP_IRQ_EN, BIT(in_irq), BIT(in_irq)); + } else { + switch (desc->irq) { + case IRQ_EXT_DOMAIN0: + io_reg_update_bits(RG_DSP_IRQ_EN, BIT(irq + IRQ_EXT_DOMAIN0_OFFSET), + BIT(irq + IRQ_EXT_DOMAIN0_OFFSET)); + break; + case IRQ_EXT_DOMAIN1: + io_reg_update_bits(DSP_IRQ_EN, BIT(irq), BIT(irq)); + break; + default: + tr_err(&int_tr, "Invalid interrupt %d", desc->irq); + return; + } + } +} + +static uint64_t mtk_get_irq_interrupts(uint32_t irq) +{ + uint32_t irq_status; + + switch (irq) { + case IRQ_NUM_EXT_LEVEL23: + irq_status = io_reg_read(DSP_IRQ_STATUS); + irq_status &= IRQ_EXT_DOMAIN2_MASK; + break; + default: + irq_status = io_reg_read(RG_DSP_IRQ_STATUS); + irq_status &= IRQ_EXT_DOMAIN1_MASK; + break; + } + return irq_status; +} + +static int get_first_irq(uint64_t ints) +{ + return ffs(ints) - 1; +} + +static inline void mtk_handle_irq(struct irq_cascade_desc *cascade, + uint32_t line_index, uint64_t status) +{ + int core = cpu_get_id(); + struct list_item *clist; + struct irq_desc *child = NULL; + int bit; + bool handled; + + while (status) { + bit = get_first_irq(status); + handled = false; + status &= ~(1ull << bit); + + spin_lock(&cascade->lock); + + list_for_item(clist, &cascade->child[bit].list) { + child = container_of(clist, struct irq_desc, irq_list); + + if (child->handler && (child->cpu_mask & 1 << core)) { + child->handler(child->handler_arg); + handled = true; + } + } + + spin_unlock(&cascade->lock); + + if (!handled) { + tr_err(&int_tr, "irq_handler(): not handled, bit %d", bit); + if (line_index == IRQ_NUM_EXT_LEVEL23) + io_reg_update_bits(DSP_IRQ_EN, BIT(bit), 0x0); + else + io_reg_update_bits(RG_DSP_IRQ_EN, BIT(bit), 0x0); + } + } +} + +static inline void irq_handler(void *data, uint32_t line_index) +{ + struct irq_desc *parent = data; + struct irq_cascade_desc *cascade = + container_of(parent, struct irq_cascade_desc, desc); + uint64_t status; + + status = mtk_get_irq_interrupts(line_index); + + if (status) + /* Handle current interrupts */ + mtk_handle_irq(cascade, line_index, status); + else + tr_err(&int_tr, "invalid interrupt status"); +} + +#define DEFINE_IRQ_HANDLER(n) \ + static void irqhandler_##n(void *arg) \ + { \ + irq_handler(arg, n); \ + } + +DEFINE_IRQ_HANDLER(1) +DEFINE_IRQ_HANDLER(23) + +static const char mtk_irq_ext_domain0[] = "mtk_irq_ext_domain0"; +static const char mtk_irq_ext_domain1[] = "mtk_irq_ext_domain1"; + +static const struct irq_cascade_ops irq_ops = { + .mask = mtk_irq_mask, + .unmask = mtk_irq_unmask, +}; + +static const struct irq_cascade_tmpl dsp_irq[] = { + { + .name = mtk_irq_ext_domain0, + .irq = IRQ_NUM_EXT_LEVEL01, + .handler = irqhandler_1, + .ops = &irq_ops, + .global_mask = false, + }, + { + .name = mtk_irq_ext_domain1, + .irq = IRQ_NUM_EXT_LEVEL23, + .handler = irqhandler_23, + .ops = &irq_ops, + .global_mask = false, + }, +}; + +uint32_t mtk_get_irq_domain_id(int32_t irq) +{ + uint32_t in_irq = GET_INTERRUPT_ID(irq); + int32_t level = GET_INTLEVEL(irq); + + if (in_irq >= DOMAIN1_MAX_IRQ_NUM) + in_irq -= DOMAIN1_MAX_IRQ_NUM; + + if (level == IRQ_EXT_DOMAIN0) + return interrupt_get_irq(in_irq, dsp_irq[0].name); + else + return interrupt_get_irq(in_irq, dsp_irq[1].name); +} + +void platform_interrupt_init(void) +{ + int i; + + irq_mask_all(); + + for (i = 0; i < ARRAY_SIZE(dsp_irq); i++) + interrupt_cascade_register(dsp_irq + i); +} + +void platform_interrupt_set(uint32_t irq) +{ + if (interrupt_is_dsp_direct(irq)) + arch_interrupt_set(irq); +} + +void platform_interrupt_clear(uint32_t irq, uint32_t mask) +{ + if (interrupt_is_dsp_direct(irq)) + arch_interrupt_clear(irq); +} + +uint32_t platform_interrupt_get_enabled(void) +{ + return 0; +} + +void interrupt_mask(uint32_t irq, unsigned int cpu) +{ + struct irq_cascade_desc *cascade = interrupt_get_parent(irq); + + if (cascade && cascade->ops->mask) + cascade->ops->mask(&cascade->desc, irq - cascade->irq_base, + cpu); + else + mtk_irq_mask(NULL, irq, 0); +} + +void interrupt_unmask(uint32_t irq, unsigned int cpu) +{ + struct irq_cascade_desc *cascade = interrupt_get_parent(irq); + + if (cascade && cascade->ops->unmask) + cascade->ops->unmask(&cascade->desc, irq - cascade->irq_base, + cpu); + else + mtk_irq_unmask(NULL, irq, 0); +} diff --git a/src/drivers/mediatek/mt8195/ipc.c b/src/drivers/mediatek/mt8195/ipc.c new file mode 100644 index 000000000000..9daaece5efc3 --- /dev/null +++ b/src/drivers/mediatek/mt8195/ipc.c @@ -0,0 +1,156 @@ +// SPDX-License-Identifier: BSD-3-Clause +// +// Copyright(c) 2021 Mediatek +// +// Author: Allen-KH Cheng + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define IPC_DSPMBOX_DSP_RSP 0 +#define IPC_DSPMBOX_DSP_REQ 1 + +/* 389c9186-5a7d-4ad1-a02c-a02ecdadfb33 */ +DECLARE_SOF_UUID("ipc-task", ipc_task_uuid, 0x389c9186, 0x5a7d, 0x4ad1, + 0xa0, 0x2c, 0xa0, 0x2e, 0xcd, 0xad, 0xfb, 0x33); + +static struct ipc *local_ipc; + +struct ipc_data { + struct ipc_data_host_buffer dh_buffer; +}; + +static void mbox0_handler(void *args) +{ + uint32_t op = io_reg_read(MTK_DSP_MBOX_IN_CMD(0)); + + /* clear interrupt */ + io_reg_write(MTK_DSP_MBOX_IN_CMD_CLR(0), op); + ipc_schedule_process(local_ipc); +} + +static void mbox1_handler(void *args) +{ + uint32_t op = io_reg_read(MTK_DSP_MBOX_IN_CMD(1)); + + /* clear interrupt */ + io_reg_write(MTK_DSP_MBOX_IN_CMD_CLR(1), op); + local_ipc->is_notification_pending = false; +} + +void trigger_irq_to_host_rsp(void) +{ + io_reg_write(MTK_DSP_MBOX_OUT_CMD(0), ADSP_IPI_OP_RSP); +} + +void trigger_irq_to_host_req(void) +{ + io_reg_write(MTK_DSP_MBOX_OUT_CMD(1), ADSP_IPI_OP_REQ); +} + +enum task_state ipc_platform_do_cmd(void *data) +{ + ipc_cmd_hdr *hdr; + + hdr = mailbox_validate(); + ipc_cmd(hdr); + + return SOF_TASK_STATE_COMPLETED; +} + +void ipc_platform_complete_cmd(void *data) +{ + struct ipc *ipc = data; + + trigger_irq_to_host_rsp(); + while (ipc->pm_prepare_D3) + wait_for_interrupt(0); +} + +int ipc_platform_send_msg(struct ipc_msg *msg) +{ + struct ipc *ipc = ipc_get(); + + if (ipc->is_notification_pending) + return -EBUSY; + + /* now send the message */ + mailbox_dspbox_write(0, msg->tx_data, msg->tx_size); + list_item_del(&msg->list); + ipc->is_notification_pending = true; + + /* now interrupt host to tell it we have sent a message */ + trigger_irq_to_host_req(); + return 0; +} + +#if CONFIG_HOST_PTABLE +struct ipc_data_host_buffer *ipc_platform_get_host_buffer(struct ipc *ipc) +{ + struct ipc_data *iipc = ipc_get_drvdata(ipc); + + return &iipc->dh_buffer; +} +#endif + +int platform_ipc_init(struct ipc *ipc) +{ + uint32_t mbox_irq0, mbox_irq1; +#if CONFIG_HOST_PTABLE + struct ipc_data *iipc; + + iipc = rzalloc(SOF_MEM_ZONE_SYS, 0, SOF_MEM_CAPS_RAM, sizeof(*iipc)); + ipc_set_drvdata(ipc, iipc); +#else + ipc_set_drvdata(ipc, NULL); +#endif + + local_ipc = ipc; + + /* schedule */ + schedule_task_init_edf(&ipc->ipc_task, SOF_UUID(ipc_task_uuid), &ipc_task_ops, ipc, 0, 0); + +#if CONFIG_HOST_PTABLE + /* allocate page table buffer */ + iipc->dh_buffer.page_table = + rzalloc(SOF_MEM_ZONE_SYS, 0, SOF_MEM_CAPS_RAM, PLATFORM_PAGE_TABLE_SIZE); + + iipc->dh_buffer.dmac = dma_get(DMA_DIR_HMEM_TO_LMEM, 0, DMA_DEV_HOST, DMA_ACCESS_SHARED); + if (!iipc->dh_buffer.dmac) { + tr_err(&ipc_tr, "Unable to find DMA for host page table"); + panic(SOF_IPC_PANIC_IPC); + } +#endif + + mbox_irq0 = mtk_get_irq_domain_id(LX_MBOX_IRQ0_B); + mbox_irq1 = mtk_get_irq_domain_id(LX_MBOX_IRQ1_B); + interrupt_register(mbox_irq0, mbox0_handler, ipc); + interrupt_register(mbox_irq1, mbox1_handler, ipc); + interrupt_enable(mbox_irq0, ipc); + interrupt_enable(mbox_irq1, ipc); + + return 0; +} diff --git a/src/drivers/mediatek/mt8195/timer.c b/src/drivers/mediatek/mt8195/timer.c new file mode 100644 index 000000000000..40e81cb21096 --- /dev/null +++ b/src/drivers/mediatek/mt8195/timer.c @@ -0,0 +1,104 @@ +// SPDX-License-Identifier: BSD-3-Clause +// +// Copyright(c) 2021 Mediatek +// +// Author:Fengquan Chen + +#include +#include +#include +#include +#include +#include +#include +#include + +void platform_timer_start(struct timer *timer) +{ + /* nothing to do for cpu timer */ +} + +void platform_timer_stop(struct timer *timer) +{ + arch_timer_disable(timer); +} + +int64_t platform_timer_set(struct timer *timer, uint64_t ticks) +{ + return arch_timer_set(timer, ticks); +} + +void platform_timer_clear(struct timer *timer) +{ + arch_timer_clear(timer); +} + +uint64_t platform_timer_get(struct timer *timer) +{ + return arch_timer_get_system(timer); +} + +/* IRQs off in arch_timer_get_system() */ +uint64_t platform_timer_get_atomic(struct timer *timer) +{ + return arch_timer_get_system(timer); +} + +/* get timestamp for host stream DMA position */ +void platform_host_timestamp(struct comp_dev *host, + struct sof_ipc_stream_posn *posn) +{ + int err; + + /* get host position */ + err = comp_position(host, posn); + if (err == 0) + posn->flags |= SOF_TIME_HOST_VALID | SOF_TIME_HOST_64; +} + +/* get timestamp for DAI stream DMA position */ +void platform_dai_timestamp(struct comp_dev *dai, + struct sof_ipc_stream_posn *posn) +{ + int err; + + /* get DAI position */ + err = comp_position(dai, posn); + if (err == 0) + posn->flags |= SOF_TIME_DAI_VALID; + + posn->wallclock = timer_get_system(timer_get()) - posn->wallclock; + posn->flags |= SOF_TIME_WALL_VALID | SOF_TIME_WALL_64; +} + +/* get current wallclock for componnent */ +void platform_dai_wallclock(struct comp_dev *dai, uint64_t *wallclock) +{ + *wallclock = timer_get_system(timer_get()); +} + +int timer_register(struct timer *timer, void(*handler)(void *arg), void *arg) +{ + switch (timer->id) { + case TIMER0: + case TIMER1: + return arch_timer_register(timer, handler, arg); + default: + return -EINVAL; + } +} + +void timer_unregister(struct timer *timer, void *arg) +{ + interrupt_unregister(timer->irq, arg); +} + +void timer_enable(struct timer *timer, void *arg, int core) +{ + interrupt_enable(timer->irq, arg); +} + +void timer_disable(struct timer *timer, void *arg, int core) +{ + interrupt_disable(timer->irq, arg); +} From a2e7d0c8e72e7f106a2bf3cc74ece59567ffa573 Mon Sep 17 00:00:00 2001 From: Allen-KH Cheng Date: Fri, 27 Aug 2021 14:24:56 +0800 Subject: [PATCH 04/15] platform: mtk: add memory layout for mt8195 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add memory layout and register address for mtk mt8195 mt8195: Cache  I-Cache: 32KB, 4-way Associativity  D-Cache: 128KB, 4-way Associativity External Memory DRAM: DSP can access DRAM which shared with CPU L2TCM: 256KB DSP SRAM POOL Currently, use phy addr:0x60000000, size:0x1000000 dma phy addr: 0x61000000, size: 0x0100000 Signed-off-by: YC Hung Signed-off-by: Allen-KH Cheng --- .../include/platform/drivers/mt_reg_base.h | 140 +++++ .../mt8195/include/platform/lib/memory.h | 214 ++++++++ src/platform/mt8195/lib/memory.c | 100 ++++ src/platform/mt8195/mt8195.x.in | 497 ++++++++++++++++++ 4 files changed, 951 insertions(+) create mode 100644 src/platform/mt8195/include/platform/drivers/mt_reg_base.h create mode 100644 src/platform/mt8195/include/platform/lib/memory.h create mode 100644 src/platform/mt8195/lib/memory.c create mode 100644 src/platform/mt8195/mt8195.x.in diff --git a/src/platform/mt8195/include/platform/drivers/mt_reg_base.h b/src/platform/mt8195/include/platform/drivers/mt_reg_base.h new file mode 100644 index 000000000000..9fe624d7cb91 --- /dev/null +++ b/src/platform/mt8195/include/platform/drivers/mt_reg_base.h @@ -0,0 +1,140 @@ +// SPDX-License-Identifier: BSD-3-Clause +// +// Copyright(c) 2021 Mediatek +// +// Author: YC Hung +// Allen-KH Cheng + +#ifndef MT_REG_BASE_H +#define MT_REG_BASE_H + +#define MTK_DSP_IRQ_BASE 0x10009000 +#define MTK_DSP_IRQ_SIZE 0x1000 + +#define MTK_TOPCKGEN_REG_BASE 0x1001B000 +#define MTK_TOPCKGEN_REG_SIZE 0x00001000 + +#define MTK_DSP_REG_REMAP_BASE 0x10800000 +#define MTK_DSP_REG_REMAP_SIZE 0xE000 +#define MTK_DSP_TIMER_BASE 0x10800000 +#define MTK_DSP_UART0_BASE 0x10801000 +#define MTK_DSP_REG_BASE 0x10803000 /* DSPCFG base */ +#define MTK_DSP_WDT_BASE 0x10803400 +#define MTK_DSP_OSTIMER_BASE 0x1080D000 + +#define MTK_DSP_JTAGMUX (MTK_DSP_REG_BASE + 0x0000) +#define MTK_DSP_ALTRESETVEC (MTK_DSP_REG_BASE + 0x0004) +#define MTK_DSP_PDEBUGDATA (MTK_DSP_REG_BASE + 0x0008) +#define MTK_DSP_PDEBUGBUS0 (MTK_DSP_REG_BASE + 0x000c) +#define MTK_DSP_PDEBUGBUS1 (MTK_DSP_REG_BASE + 0x0010) +#define MTK_DSP_PDEBUGINST (MTK_DSP_REG_BASE + 0x0014) +#define MTK_DSP_PDEBUGLS0STAT (MTK_DSP_REG_BASE + 0x0018) +#define MTK_DSP_PDEBUGLS1STAT (MTK_DSP_REG_BASE + 0x001c) +#define MTK_DSP_PDEBUGPC (MTK_DSP_REG_BASE + 0x0020) +#define MTK_DSP_RESET_SW (MTK_DSP_REG_BASE + 0x0024) +#define MTK_DSP_PFAULTBUS (MTK_DSP_REG_BASE + 0x0028) +#define MTK_DSP_PFAULTINFO (MTK_DSP_REG_BASE + 0x002c) +#define MTK_DSP_GPR00 (MTK_DSP_REG_BASE + 0x0030) +#define MTK_DSP_GPR01 (MTK_DSP_REG_BASE + 0x0034) +#define MTK_DSP_GPR02 (MTK_DSP_REG_BASE + 0x0038) +#define MTK_DSP_GPR03 (MTK_DSP_REG_BASE + 0x003c) +#define MTK_DSP_GPR04 (MTK_DSP_REG_BASE + 0x0040) +#define MTK_DSP_GPR05 (MTK_DSP_REG_BASE + 0x0044) +#define MTK_DSP_GPR06 (MTK_DSP_REG_BASE + 0x0048) +#define MTK_DSP_GPR07 (MTK_DSP_REG_BASE + 0x004c) +#define MTK_DSP_GPR08 (MTK_DSP_REG_BASE + 0x0050) +#define MTK_DSP_GPR09 (MTK_DSP_REG_BASE + 0x0054) +#define MTK_DSP_GPR0A (MTK_DSP_REG_BASE + 0x0058) +#define MTK_DSP_GPR0B (MTK_DSP_REG_BASE + 0x005c) +#define MTK_DSP_GPR0C (MTK_DSP_REG_BASE + 0x0060) +#define MTK_DSP_GPR0D (MTK_DSP_REG_BASE + 0x0064) +#define MTK_DSP_GPR0E (MTK_DSP_REG_BASE + 0x0068) +#define MTK_DSP_GPR0F (MTK_DSP_REG_BASE + 0x006c) +#define MTK_DSP_GPR10 (MTK_DSP_REG_BASE + 0x0070) +#define MTK_DSP_GPR11 (MTK_DSP_REG_BASE + 0x0074) +#define MTK_DSP_GPR12 (MTK_DSP_REG_BASE + 0x0078) +#define MTK_DSP_GPR13 (MTK_DSP_REG_BASE + 0x007c) +#define MTK_DSP_GPR14 (MTK_DSP_REG_BASE + 0x0080) +#define MTK_DSP_GPR15 (MTK_DSP_REG_BASE + 0x0084) +#define MTK_DSP_GPR16 (MTK_DSP_REG_BASE + 0x0088) +#define MTK_DSP_GPR17 (MTK_DSP_REG_BASE + 0x008c) +#define MTK_DSP_GPR18 (MTK_DSP_REG_BASE + 0x0090) +#define MTK_DSP_GPR19 (MTK_DSP_REG_BASE + 0x0094) +#define MTK_DSP_GPR1A (MTK_DSP_REG_BASE + 0x0098) +#define MTK_DSP_GPR1B (MTK_DSP_REG_BASE + 0x009c) +#define MTK_DSP_GPR1C (MTK_DSP_REG_BASE + 0x00a0) +#define MTK_DSP_GPR1D (MTK_DSP_REG_BASE + 0x00a4) +#define MTK_DSP_GPR1E (MTK_DSP_REG_BASE + 0x00a8) +#define MTK_DSP_GPR1F (MTK_DSP_REG_BASE + 0x00ac) +#define MTK_DSP_TCM_OFFSET (MTK_DSP_REG_BASE + 0x00b0) /* not used */ +#define MTK_DSP_DDR_OFFSET (MTK_DSP_REG_BASE + 0x00b4) /* not used */ +#define MTK_DSP_INTFDSP (MTK_DSP_REG_BASE + 0x00d0) +#define MTK_DSP_INTFDSP_CLR (MTK_DSP_REG_BASE + 0x00d4) +#define MTK_DSP_SRAM_PD_SW1 (MTK_DSP_REG_BASE + 0x00d8) +#define MTK_DSP_SRAM_PD_SW2 (MTK_DSP_REG_BASE + 0x00dc) +#define MTK_DSP_OCD (MTK_DSP_REG_BASE + 0x00e0) +#define MTK_DSP_RG_DSP_IRQ_POL (MTK_DSP_REG_BASE + 0x00f0) +#define MTK_DSP_DSP_IRQ_EN (MTK_DSP_REG_BASE + 0x00f4) +#define MTK_DSP_DSP_IRQ_LEVEL (MTK_DSP_REG_BASE + 0x00f8) +#define MTK_DSP_DSP_IRQ_STATUS (MTK_DSP_REG_BASE + 0x00fc) +#define MTK_DSP_RG_INT2CIRQ (MTK_DSP_REG_BASE + 0x0114) +#define MTK_DSP_RG_INT_POL_CTL0 (MTK_DSP_REG_BASE + 0x0120) +#define MTK_DSP_RG_INT_EN_CTL0 (MTK_DSP_REG_BASE + 0x0130) +#define MTK_DSP_RG_INT_LV_CTL0 (MTK_DSP_REG_BASE + 0x0140) +#define MTK_DSP_RG_INT_STATUS0 (MTK_DSP_REG_BASE + 0x0150) +#define MTK_DSP_PDEBUGSTATUS0 (MTK_DSP_REG_BASE + 0x0200) +#define MTK_DSP_PDEBUGSTATUS1 (MTK_DSP_REG_BASE + 0x0204) +#define MTK_DSP_PDEBUGSTATUS2 (MTK_DSP_REG_BASE + 0x0208) +#define MTK_DSP_PDEBUGSTATUS3 (MTK_DSP_REG_BASE + 0x020c) +#define MTK_DSP_PDEBUGSTATUS4 (MTK_DSP_REG_BASE + 0x0210) +#define MTK_DSP_PDEBUGSTATUS5 (MTK_DSP_REG_BASE + 0x0214) +#define MTK_DSP_PDEBUGSTATUS6 (MTK_DSP_REG_BASE + 0x0218) +#define MTK_DSP_PDEBUGSTATUS7 (MTK_DSP_REG_BASE + 0x021c) +#define MTK_DSP_DSP2PSRAM_PRIORITY (MTK_DSP_REG_BASE + 0x0220) /* not used */ +#define MTK_DSP_AUDIO_DSP2SPM_INT (MTK_DSP_REG_BASE + 0x0224) +#define MTK_DSP_AUDIO_DSP2SPM_INT_ACK (MTK_DSP_REG_BASE + 0x0228) +#define MTK_DSP_AUDIO_DSP_DEBUG_SEL (MTK_DSP_REG_BASE + 0x022C) +#define MTK_DSP_AUDIO_DSP_EMI_BASE_ADDR (MTK_DSP_REG_BASE + 0x02E0) /* not used */ +#define MTK_DSP_AUDIO_DSP_SHARED_IRAM (MTK_DSP_REG_BASE + 0x02E4) +#define MTK_DSP_AUDIO_DSP_CKCTRL_P2P_CK_CON (MTK_DSP_REG_BASE + 0x02F0) +#define MTK_DSP_RG_SEMAPHORE00 (MTK_DSP_REG_BASE + 0x0300) +#define MTK_DSP_RG_SEMAPHORE01 (MTK_DSP_REG_BASE + 0x0304) +#define MTK_DSP_RG_SEMAPHORE02 (MTK_DSP_REG_BASE + 0x0308) +#define MTK_DSP_RG_SEMAPHORE03 (MTK_DSP_REG_BASE + 0x030C) +#define MTK_DSP_RG_SEMAPHORE04 (MTK_DSP_REG_BASE + 0x0310) +#define MTK_DSP_RG_SEMAPHORE05 (MTK_DSP_REG_BASE + 0x0314) +#define MTK_DSP_RG_SEMAPHORE06 (MTK_DSP_REG_BASE + 0x0318) +#define MTK_DSP_RG_SEMAPHORE07 (MTK_DSP_REG_BASE + 0x031C) +#define MTK_DSP_RESERVED_0 (MTK_DSP_REG_BASE + 0x03F0) +#define MTK_DSP_RESERVED_1 (MTK_DSP_REG_BASE + 0x03F4) + +/*MBOX registers*/ +#define MTK_DSP_MBOX_REG_BASE(x) (0x10816000 + (0x1000 * (x))) +#define MTK_DSP_MBOX_REG_SIZE (0x5000) +#define MTK_DSP_MBOX_IN_CMD(x) (MTK_DSP_MBOX_REG_BASE(x) + 0x0) +#define MTK_DSP_MBOX_IN_CMD_CLR(x) (MTK_DSP_MBOX_REG_BASE(x) + 0x04) +#define MTK_DSP_MBOX_OUT_CMD(x) (MTK_DSP_MBOX_REG_BASE(x) + 0x1c) +#define MTK_DSP_MBOX_OUT_CMD_CLR(x) (MTK_DSP_MBOX_REG_BASE(x) + 0x20) +#define MTK_DSP_MBOX_OUT_CMD_MSG0(x) (MTK_DSP_MBOX_REG_BASE(x) + 0x24) +#define MTK_DSP_MBOX_OUT_CMD_MSG1(x) (MTK_DSP_MBOX_REG_BASE(x) + 0x28) +#define MTK_DSP_MBOX_OUT_CMD_MSG2(x) (MTK_DSP_MBOX_REG_BASE(x) + 0x2c) +#define MTK_DSP_MBOX_OUT_CMD_MSG3(x) (MTK_DSP_MBOX_REG_BASE(x) + 0x30) +#define MTK_DSP_MBOX_OUT_CMD_MSG4(x) (MTK_DSP_MBOX_REG_BASE(x) + 0x34) + +/* Redefinition for using Special registers */ +#define MTK_TICKLESS_STATUS_REG (DSP_RESERVED_1) + +/* WDT CONFIGS */ +#define MTK_ADSP_WDT_MODE (MTK_DSP_WDT_BASE + 0x00) +#define MTK_ADSP_WDT_LENGTH (MTK_DSP_WDT_BASE + 0x04) +#define MTK_ADSP_WDT_RESTART (MTK_DSP_WDT_BASE + 0x08) +#define MTK_ADSP_WDT_STA (MTK_DSP_WDT_BASE + 0x0C) +#define MTK_ADSP_WDT_SWRST (MTK_DSP_WDT_BASE + 0x14) + +#define MTK_ADSP_WDT_SWRST_KEY 0x1209 +#define MTK_ADSP_WDT_RESTART_RELOAD 0x1971 +#define MTK_ADSP_WDT_LENGTH_KEY 0x8 + +#define MTK_WDT_LENGTH_TIMEOUT(n) ((n) << 5) + +#endif /* MT_REG_BASE_H */ diff --git a/src/platform/mt8195/include/platform/lib/memory.h b/src/platform/mt8195/include/platform/lib/memory.h new file mode 100644 index 000000000000..873cdd951159 --- /dev/null +++ b/src/platform/mt8195/include/platform/lib/memory.h @@ -0,0 +1,214 @@ +// SPDX-License-Identifier: BSD-3-Clause +// +// Copyright(c) 2021 Mediatek +// +// Author: YC Hung +// Allen-KH Cheng + +#ifdef __SOF_LIB_MEMORY_H__ + +#ifndef __PLATFORM_LIB_MEMORY_H__ +#define __PLATFORM_LIB_MEMORY_H__ + +#include +#include + +#define BOOT_WITH_DRAM /*Use DRAM as SRAM1 for heap related*/ +/* data cache line alignment */ +#define PLATFORM_DCACHE_ALIGN sizeof(void *) + +/* BOOT_WITH_DRAM ONLY */ +/* physical DSP addresses */ +#define DRAM_BASE 0x60000000 +#define DRAM_AUDIO_SHARED_SIZE 0x80000 +#define DRAM_SIZE 0x1000000 /*DRAM Size : 16M , need to sync with Host side*/ + +#define SRAM_TOTAL_SIZE 0x40000 /*256KB DSP SRAM*/ +#define VECTOR_SIZE 0x628 + +#define SRAM0_BASE DRAM_BASE +#define SRAM0_SIZE (DRAM_SIZE >> 1) +#define SRAM1_BASE (DRAM_BASE + SRAM0_SIZE) +#define SRAM1_SIZE \ + (DRAM_SIZE - SRAM0_SIZE - DRAM_AUDIO_SHARED_SIZE - UUID_ENTRY_ELF_SIZE - \ + LOG_ENTRY_ELF_SIZE - EXT_MANIFEST_ELF_SIZE) + +#define DMA_SIZE 0x100000 + +#define UUID_ENTRY_ELF_SIZE 0x6000 +#define LOG_ENTRY_ELF_SIZE 0x200000 +#define EXT_MANIFEST_ELF_SIZE 0x100000 + +#define UUID_ENTRY_ELF_BASE (SRAM1_BASE + SRAM1_SIZE) +#define LOG_ENTRY_ELF_BASE (UUID_ENTRY_ELF_BASE + UUID_ENTRY_ELF_SIZE) +#define EXT_MANIFEST_ELF_BASE (LOG_ENTRY_ELF_BASE + LOG_ENTRY_ELF_SIZE) + +/* + * The Heap and Stack on MT8195 are organised like this :- + * + * +--------------------------------------------------------------------------+ + * | Offset | Region | Size | + * +---------------------+----------------+-----------------------------------+ + * | SRAM1_BASE | RO Data | SOF_DATA_SIZE | + * | | Data | | + * | | BSS | | + * +---------------------+----------------+-----------------------------------+ + * | HEAP_SYSTEM_BASE | System Heap | HEAP_SYSTEM_SIZE | + * +---------------------+----------------+-----------------------------------+ + * | HEAP_RUNTIME_BASE | Runtime Heap | HEAP_RUNTIME_SIZE | + * +---------------------+----------------+-----------------------------------+ + * | HEAP_BUFFER_BASE | Module Buffers | HEAP_BUFFER_SIZE | + * +---------------------+----------------+-----------------------------------+ + * | SOF_STACK_END | Stack | SOF_STACK_SIZE | + * +---------------------+----------------+-----------------------------------+ + * | SOF_STACK_BASE | | | + * +---------------------+----------------+-----------------------------------+ + */ + +/* Mailbox configuration */ +#define SRAM_OUTBOX_BASE SRAM1_BASE +#define SRAM_OUTBOX_SIZE 0x1000 +#define SRAM_OUTBOX_OFFSET 0 + +#define SRAM_INBOX_BASE (SRAM_OUTBOX_BASE + SRAM_OUTBOX_SIZE) +#define SRAM_INBOX_SIZE 0x1000 +#define SRAM_INBOX_OFFSET SRAM_OUTBOX_SIZE + +#define SRAM_DEBUG_BASE (SRAM_INBOX_BASE + SRAM_INBOX_SIZE) +#define SRAM_DEBUG_SIZE 0x800 +#define SRAM_DEBUG_OFFSET (SRAM_INBOX_OFFSET + SRAM_INBOX_SIZE) + +#define SRAM_EXCEPT_BASE (SRAM_DEBUG_BASE + SRAM_DEBUG_SIZE) +#define SRAM_EXCEPT_SIZE 0x800 +#define SRAM_EXCEPT_OFFSET (SRAM_DEBUG_OFFSET + SRAM_DEBUG_SIZE) + +#define SRAM_STREAM_BASE (SRAM_EXCEPT_BASE + SRAM_EXCEPT_SIZE) +#define SRAM_STREAM_SIZE 0x1000 +#define SRAM_STREAM_OFFSET (SRAM_EXCEPT_OFFSET + SRAM_EXCEPT_SIZE) + +#define SRAM_TRACE_BASE (SRAM_STREAM_BASE + SRAM_STREAM_SIZE) +#define SRAM_TRACE_SIZE 0x1000 +#define SRAM_TRACE_OFFSET (SRAM_STREAM_OFFSET + SRAM_STREAM_SIZE) + +/*4K + 4K +2K + 2K + 4K + 4K = 20KB*/ +#define SOF_MAILBOX_SIZE \ + (SRAM_INBOX_SIZE + SRAM_OUTBOX_SIZE + SRAM_DEBUG_SIZE + SRAM_EXCEPT_SIZE + \ + SRAM_STREAM_SIZE + SRAM_TRACE_SIZE) + +/* Heap section sizes for module pool */ +#define HEAP_RT_COUNT8 0 +#define HEAP_RT_COUNT16 48 +#define HEAP_RT_COUNT32 48 +#define HEAP_RT_COUNT64 32 +#define HEAP_RT_COUNT128 32 +#define HEAP_RT_COUNT256 32 +#define HEAP_RT_COUNT512 4 +#define HEAP_RT_COUNT1024 4 +#define HEAP_RT_COUNT2048 2 +#define HEAP_RT_COUNT4096 2 + +/* Heap section sizes for system runtime heap */ +#define HEAP_SYS_RT_COUNT64 128 +#define HEAP_SYS_RT_COUNT512 16 +#define HEAP_SYS_RT_COUNT1024 8 + +/* Heap configuration */ + +#define HEAP_SYSTEM_BASE (SRAM1_BASE + SOF_MAILBOX_SIZE) +#define HEAP_SYSTEM_SIZE 0x6000 + +#define HEAP_SYSTEM_0_BASE HEAP_SYSTEM_BASE + +#define HEAP_SYS_RUNTIME_BASE (HEAP_SYSTEM_BASE + HEAP_SYSTEM_SIZE) +/*24KB*/ +#define HEAP_SYS_RUNTIME_SIZE \ + (HEAP_SYS_RT_COUNT64 * 64 + HEAP_SYS_RT_COUNT512 * 512 + HEAP_SYS_RT_COUNT1024 * 1024) + +#define HEAP_RUNTIME_BASE (HEAP_SYS_RUNTIME_BASE + HEAP_SYS_RUNTIME_SIZE) +/*48*(16 +32) + 32*(64 128+256) + 4*(512+1024) + 1*2048 = 24832 = 24.25KB*/ +#define HEAP_RUNTIME_SIZE \ + (HEAP_RT_COUNT8 * 8 + HEAP_RT_COUNT16 * 16 + HEAP_RT_COUNT32 * 32 + HEAP_RT_COUNT64 * 64 + \ + HEAP_RT_COUNT128 * 128 + HEAP_RT_COUNT256 * 256 + HEAP_RT_COUNT512 * 512 + \ + HEAP_RT_COUNT1024 * 1024 + HEAP_RT_COUNT2048 * 2048 + HEAP_RT_COUNT4096 * 4096) + +#define HEAP_BUFFER_BASE (HEAP_RUNTIME_BASE + HEAP_RUNTIME_SIZE) +#define HEAP_BUFFER_SIZE \ + (SRAM1_SIZE - SOF_MAILBOX_SIZE - HEAP_RUNTIME_SIZE - SOF_STACK_TOTAL_SIZE - \ + HEAP_SYS_RUNTIME_SIZE - HEAP_SYSTEM_SIZE) + +#define HEAP_BUFFER_BLOCK_SIZE 0x100 +#define HEAP_BUFFER_COUNT (HEAP_BUFFER_SIZE / HEAP_BUFFER_BLOCK_SIZE) + +#define PLATFORM_HEAP_SYSTEM 1 /* one per core */ +#define PLATFORM_HEAP_SYSTEM_RUNTIME 1 /* one per core */ +#define PLATFORM_HEAP_RUNTIME 1 +#define PLATFORM_HEAP_BUFFER 1 + +/* Stack configuration */ +#define SOF_STACK_SIZE 0x8000 +#define SOF_STACK_TOTAL_SIZE SOF_STACK_SIZE /*4KB*/ +#define SOF_STACK_BASE (SRAM1_BASE + SRAM1_SIZE) +#define SOF_STACK_END (SOF_STACK_BASE - SOF_STACK_TOTAL_SIZE) + +/* Vector and literal sizes - not in core-isa.h */ +#define SOF_MEM_VECT_LIT_SIZE 0x4 +#define SOF_MEM_VECT_TEXT_SIZE 0x1c +#define SOF_MEM_VECT_SIZE (SOF_MEM_VECT_TEXT_SIZE + SOF_MEM_VECT_LIT_SIZE) + +#define SOF_MEM_RESET_TEXT_SIZE 0x2e0 +#define SOF_MEM_RESET_LIT_SIZE 0x120 +#define SOF_MEM_VECBASE_LIT_SIZE 0x178 + +#define SOF_MEM_RO_SIZE 0x8 + +#define HEAP_BUF_ALIGNMENT DCACHE_LINE_SIZE + +/** \brief EDF task's default stack size in bytes. */ +#define PLATFORM_TASK_DEFAULT_STACK_SIZE 3072 + +#if !defined(__ASSEMBLER__) && !defined(LINKER) + +struct sof; + +/** + * \brief Data shared between different cores. + * Does nothing, since mt8195 doesn't support SMP. + */ +#define SHARED_DATA + +void platform_init_memmap(struct sof *sof); + +static inline void *platform_shared_get(void *ptr, int bytes) +{ + return ptr; +} + +#define uncache_to_cache(address) address +#define cache_to_uncache(address) address +#define is_uncached(address) 0 + +/** + * \brief Function for keeping shared data synchronized. + * It's used after usage of data shared by different cores. + * Such data is either statically marked with SHARED_DATA + * or dynamically allocated with SOF_MEM_FLAG_SHARED flag. + * Does nothing, since mt8195 doesn't support SMP. + */ + +static inline void *platform_rfree_prepare(void *ptr) +{ + return ptr; +} + +#endif + +#define host_to_local(addr) (addr) +#define local_to_host(addr) (addr) + +#endif /* __PLATFORM_LIB_MEMORY_H__ */ + +#else + +#error "This file shouldn't be included from outside of sof/lib/memory.h" + +#endif /* __SOF_LIB_MEMORY_H__ */ diff --git a/src/platform/mt8195/lib/memory.c b/src/platform/mt8195/lib/memory.c new file mode 100644 index 000000000000..bba9d2f9827c --- /dev/null +++ b/src/platform/mt8195/lib/memory.c @@ -0,0 +1,100 @@ +// SPDX-License-Identifier: BSD-3-Clause +// +// Copyright(c) 2021 Mediatek +// +// Author: YC Hung + +#include +#include +#include +#include +#include + +/* Heap blocks for system runtime */ +static SHARED_DATA struct block_hdr sys_rt_block64[HEAP_SYS_RT_COUNT64]; +static SHARED_DATA struct block_hdr sys_rt_block512[HEAP_SYS_RT_COUNT512]; +static SHARED_DATA struct block_hdr sys_rt_block1024[HEAP_SYS_RT_COUNT1024]; + +/* Heap memory for system runtime */ +static SHARED_DATA struct block_map sys_rt_heap_map[] = { + BLOCK_DEF(64, HEAP_SYS_RT_COUNT64, sys_rt_block64), + BLOCK_DEF(512, HEAP_SYS_RT_COUNT512, sys_rt_block512), + BLOCK_DEF(1024, HEAP_SYS_RT_COUNT1024, sys_rt_block1024), +}; + +/* Heap blocks for modules */ +static SHARED_DATA struct block_hdr mod_block16[HEAP_RT_COUNT16]; +static SHARED_DATA struct block_hdr mod_block32[HEAP_RT_COUNT32]; +static SHARED_DATA struct block_hdr mod_block64[HEAP_RT_COUNT64]; +static SHARED_DATA struct block_hdr mod_block128[HEAP_RT_COUNT128]; +static SHARED_DATA struct block_hdr mod_block256[HEAP_RT_COUNT256]; +static SHARED_DATA struct block_hdr mod_block512[HEAP_RT_COUNT512]; +static SHARED_DATA struct block_hdr mod_block1024[HEAP_RT_COUNT1024]; +static SHARED_DATA struct block_hdr mod_block2048[HEAP_RT_COUNT2048]; +static SHARED_DATA struct block_hdr mod_block4096[HEAP_RT_COUNT4096]; + +/* Heap memory map for modules */ +static SHARED_DATA struct block_map rt_heap_map[] = { + BLOCK_DEF(16, HEAP_RT_COUNT16, mod_block16), + BLOCK_DEF(32, HEAP_RT_COUNT32, mod_block32), + BLOCK_DEF(64, HEAP_RT_COUNT64, mod_block64), + BLOCK_DEF(128, HEAP_RT_COUNT128, mod_block128), + BLOCK_DEF(256, HEAP_RT_COUNT256, mod_block256), + BLOCK_DEF(512, HEAP_RT_COUNT512, mod_block512), + BLOCK_DEF(1024, HEAP_RT_COUNT1024, mod_block1024), + BLOCK_DEF(2048, HEAP_RT_COUNT2048, mod_block2048), + BLOCK_DEF(4096, HEAP_RT_COUNT4096, mod_block4096), +}; + +/* Heap blocks for buffers */ +static SHARED_DATA struct block_hdr buf_block[HEAP_BUFFER_COUNT]; + +/* Heap memory map for buffers */ +static SHARED_DATA struct block_map buf_heap_map[] = { + BLOCK_DEF(HEAP_BUFFER_BLOCK_SIZE, HEAP_BUFFER_COUNT, buf_block), +}; + +static SHARED_DATA struct mm memmap = { + .system[0] = { + .heap = HEAP_SYSTEM_BASE, + .size = HEAP_SYSTEM_SIZE, + .info = {.free = HEAP_SYSTEM_SIZE,}, + .caps = SOF_MEM_CAPS_RAM | SOF_MEM_CAPS_CACHE | + SOF_MEM_CAPS_DMA, + }, + .system_runtime[0] = { + .blocks = ARRAY_SIZE(sys_rt_heap_map), + .map = sys_rt_heap_map, + .heap = HEAP_SYS_RUNTIME_BASE, + .size = HEAP_SYS_RUNTIME_SIZE, + .info = {.free = HEAP_SYS_RUNTIME_SIZE,}, + .caps = SOF_MEM_CAPS_RAM | SOF_MEM_CAPS_CACHE | + SOF_MEM_CAPS_DMA, + }, + .runtime[0] = { + .blocks = ARRAY_SIZE(rt_heap_map), + .map = rt_heap_map, + .heap = HEAP_RUNTIME_BASE, + .size = HEAP_RUNTIME_SIZE, + .info = {.free = HEAP_RUNTIME_SIZE,}, + .caps = SOF_MEM_CAPS_RAM | SOF_MEM_CAPS_CACHE | + SOF_MEM_CAPS_DMA, + }, + .buffer[0] = { + .blocks = ARRAY_SIZE(buf_heap_map), + .map = buf_heap_map, + .heap = HEAP_BUFFER_BASE, + .size = HEAP_BUFFER_SIZE, + .info = {.free = HEAP_BUFFER_SIZE,}, + .caps = SOF_MEM_CAPS_RAM | SOF_MEM_CAPS_CACHE | + SOF_MEM_CAPS_DMA, + }, + .total = {.free = HEAP_SYSTEM_SIZE + HEAP_SYS_RUNTIME_SIZE + + HEAP_RUNTIME_SIZE + HEAP_BUFFER_SIZE,}, +}; + +void platform_init_memmap(struct sof *sof) +{ + /* memmap has been initialized statically as a part of .data */ + sof->memory_map = &memmap; +} diff --git a/src/platform/mt8195/mt8195.x.in b/src/platform/mt8195/mt8195.x.in new file mode 100644 index 000000000000..0a207cec150d --- /dev/null +++ b/src/platform/mt8195/mt8195.x.in @@ -0,0 +1,497 @@ +/* + * Linker Script for mt8195 Mediatek + * + * This script is run through the GNU C preprocessor to align the memory + * offsets with headers. + * + * Use spaces for formatting as cpp ignore tab sizes. + */ + + +#include +#include + +OUTPUT_ARCH(xtensa) + +MEMORY +{ + vector_reset_text : + org = XCHAL_RESET_VECTOR0_PADDR, + len = SOF_MEM_RESET_TEXT_SIZE + vector_reset_lit : + org = XCHAL_RESET_VECTOR0_PADDR + SOF_MEM_RESET_TEXT_SIZE, + len = SOF_MEM_RESET_LIT_SIZE + vector_base_text : + org = XCHAL_VECBASE_RESET_PADDR, + len = SOF_MEM_VECBASE_LIT_SIZE + vector_int2_lit : + org = XCHAL_INTLEVEL2_VECTOR_PADDR - SOF_MEM_VECT_LIT_SIZE, + len = SOF_MEM_VECT_LIT_SIZE + vector_int2_text : + org = XCHAL_INTLEVEL2_VECTOR_PADDR, + len = SOF_MEM_VECT_TEXT_SIZE + vector_int3_lit : + org = XCHAL_INTLEVEL3_VECTOR_PADDR - SOF_MEM_VECT_LIT_SIZE, + len = SOF_MEM_VECT_LIT_SIZE + vector_int3_text : + org = XCHAL_INTLEVEL3_VECTOR_PADDR, + len = SOF_MEM_VECT_TEXT_SIZE + vector_int4_lit : + org = XCHAL_INTLEVEL4_VECTOR_PADDR - SOF_MEM_VECT_LIT_SIZE, + len = SOF_MEM_VECT_LIT_SIZE + vector_int4_text : + org = XCHAL_INTLEVEL4_VECTOR_PADDR, + len = SOF_MEM_VECT_TEXT_SIZE + vector_kernel_lit : + org = XCHAL_KERNEL_VECTOR_PADDR - SOF_MEM_VECT_LIT_SIZE, + len = SOF_MEM_VECT_LIT_SIZE + vector_kernel_text : + org = XCHAL_KERNEL_VECTOR_PADDR, + len = SOF_MEM_VECT_TEXT_SIZE + vector_user_lit : + org = XCHAL_USER_VECTOR_PADDR - SOF_MEM_VECT_LIT_SIZE, + len = SOF_MEM_VECT_LIT_SIZE + vector_user_text : + org = XCHAL_USER_VECTOR_PADDR, + len = SOF_MEM_VECT_TEXT_SIZE + vector_double_lit : + org = XCHAL_DOUBLEEXC_VECTOR_PADDR - SOF_MEM_VECT_LIT_SIZE, + len = SOF_MEM_VECT_LIT_SIZE + vector_double_text : + org = XCHAL_DOUBLEEXC_VECTOR_PADDR, + len = SOF_MEM_VECT_TEXT_SIZE + sof_sram0 : + org = SRAM0_BASE, + len = SRAM0_SIZE + sof_sram1 : + org = SRAM1_BASE, + len = SRAM1_SIZE + system_heap : + org = HEAP_SYSTEM_BASE, + len = HEAP_SYSTEM_SIZE + system_runtime_heap : + org = HEAP_SYS_RUNTIME_BASE, + len = HEAP_SYS_RUNTIME_SIZE + runtime_heap : + org = HEAP_RUNTIME_BASE, + len = HEAP_RUNTIME_SIZE + buffer_heap : + org = HEAP_BUFFER_BASE, + len = HEAP_BUFFER_SIZE + sof_stack : + org = SOF_STACK_END, + len = SOF_STACK_BASE - SOF_STACK_END + static_uuid_entries_seg (!ari) : + org = UUID_ENTRY_ELF_BASE, + len = UUID_ENTRY_ELF_SIZE + static_log_entries_seg (!ari) : + org = LOG_ENTRY_ELF_BASE, + len = LOG_ENTRY_ELF_SIZE + fw_metadata_seg (!ari) : + org = EXT_MANIFEST_ELF_BASE, + len = EXT_MANIFEST_ELF_SIZE +} + +PHDRS +{ + vector_reset_text_phdr PT_LOAD; + vector_reset_lit_phdr PT_LOAD; + vector_base_text_phdr PT_LOAD; + vector_base_lit_phdr PT_LOAD; + vector_int2_text_phdr PT_LOAD; + vector_int2_lit_phdr PT_LOAD; + vector_int3_text_phdr PT_LOAD; + vector_int3_lit_phdr PT_LOAD; + vector_int4_text_phdr PT_LOAD; + vector_int4_lit_phdr PT_LOAD; + vector_kernel_text_phdr PT_LOAD; + vector_kernel_lit_phdr PT_LOAD; + vector_user_text_phdr PT_LOAD; + vector_user_lit_phdr PT_LOAD; + vector_double_text_phdr PT_LOAD; + vector_double_lit_phdr PT_LOAD; + sof_sram0_phdr PT_LOAD; + sof_sram1_phdr PT_LOAD; + system_heap_phdr PT_LOAD; + system_runtime_heap_phdr PT_LOAD; + runtime_heap_phdr PT_LOAD; + buffer_heap_phdr PT_LOAD; + sof_stack_phdr PT_LOAD; + static_uuid_entries_phdr PT_NOTE; + static_log_entries_phdr PT_NOTE; + metadata_entries_phdr PT_NOTE; +} + +/* Default entry point: */ +ENTRY(_ResetVector) +_rom_store_table = 0; + +/* ABI0 does not use Window base */ +PROVIDE(_memmap_vecbase_reset = XCHAL_VECBASE_RESET_PADDR); + +/* Various memory-map dependent cache attribute settings: */ +_memmap_cacheattr_wb_base = 0x00000100; +_memmap_cacheattr_wt_base = 0x00000300; +_memmap_cacheattr_bp_base = 0x00000400; +_memmap_cacheattr_unused_mask = 0xFFFFF0FF; +_memmap_cacheattr_wb_trapnull = 0x44444140; +_memmap_cacheattr_wba_trapnull = 0x44444140; +_memmap_cacheattr_wbna_trapnull = 0x44444240; +_memmap_cacheattr_wt_trapnull = 0x44444340; +_memmap_cacheattr_bp_trapnull = 0x44444440; +_memmap_cacheattr_wb_strict = 0x00000100; +_memmap_cacheattr_wt_strict = 0x00000300; +_memmap_cacheattr_bp_strict = 0x00000400; +_memmap_cacheattr_wb_allvalid = 0x44444144; +_memmap_cacheattr_wt_allvalid = 0x44444344; +_memmap_cacheattr_bp_allvalid = 0x44444444; +PROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_wb_trapnull); + +_EXT_MAN_ALIGN_ = 16; +EXTERN(ext_man_fw_ver) + +SECTIONS +{ + .ResetVector.text : ALIGN(4) + { + _ResetVector_text_start = ABSOLUTE(.); + KEEP (*(.ResetVector.text)) + _ResetVector_text_end = ABSOLUTE(.); + } >vector_reset_text :vector_reset_text_phdr + + .ResetVector.literal : ALIGN(4) + { + _ResetVector_literal_start = ABSOLUTE(.); + *(.ResetVector.literal) + _ResetVector_literal_end = ABSOLUTE(.); + } >vector_reset_lit :vector_reset_lit_phdr + + .WindowVectors.text : ALIGN(4) + { + _WindowVectors_text_start = ABSOLUTE(.); + KEEP (*(.WindowVectors.text)) + _WindowVectors_text_end = ABSOLUTE(.); + } >vector_base_text :vector_base_text_phdr + + .Level2InterruptVector.literal : ALIGN(4) + { + _Level2InterruptVector_literal_start = ABSOLUTE(.); + *(.Level2InterruptVector.literal) + _Level2InterruptVector_literal_end = ABSOLUTE(.); + } >vector_int2_lit :vector_int2_lit_phdr + + .Level2InterruptVector.text : ALIGN(4) + { + _Level2InterruptVector_text_start = ABSOLUTE(.); + KEEP (*(.Level2InterruptVector.text)) + _Level2InterruptVector_text_end = ABSOLUTE(.); + } >vector_int2_text :vector_int2_text_phdr + + .Level3InterruptVector.literal : ALIGN(4) + { + _Level3InterruptVector_literal_start = ABSOLUTE(.); + *(.Level3InterruptVector.literal) + _Level3InterruptVector_literal_end = ABSOLUTE(.); + } >vector_int3_lit :vector_int3_lit_phdr + + .Level3InterruptVector.text : ALIGN(4) + { + _Level3InterruptVector_text_start = ABSOLUTE(.); + KEEP (*(.Level3InterruptVector.text)) + _Level3InterruptVector_text_end = ABSOLUTE(.); + } >vector_int3_text :vector_int3_text_phdr + + .DebugExceptionVector.literal : ALIGN(4) + { + _DebugExceptionVector_literal_start = ABSOLUTE(.); + *(.DebugExceptionVector.literal) + _DebugExceptionVector_literal_end = ABSOLUTE(.); + } >vector_int4_lit :vector_int4_lit_phdr + + .DebugExceptionVector.text : ALIGN(4) + { + _DebugExceptionVector_text_start = ABSOLUTE(.); + KEEP (*(.DebugExceptionVector.text)) + _DebugExceptionVector_text_end = ABSOLUTE(.); + } >vector_int4_text :vector_int4_text_phdr + + .KernelExceptionVector.literal : ALIGN(4) + { + _KernelExceptionVector_literal_start = ABSOLUTE(.); + *(.KernelExceptionVector.literal) + _KernelExceptionVector_literal_end = ABSOLUTE(.); + } >vector_kernel_lit :vector_kernel_lit_phdr + + .KernelExceptionVector.text : ALIGN(4) + { + _KernelExceptionVector_text_start = ABSOLUTE(.); + KEEP (*(.KernelExceptionVector.text)) + _KernelExceptionVector_text_end = ABSOLUTE(.); + } >vector_kernel_text :vector_kernel_text_phdr + + .UserExceptionVector.literal : ALIGN(4) + { + _UserExceptionVector_literal_start = ABSOLUTE(.); + *(.UserExceptionVector.literal) + _UserExceptionVector_literal_end = ABSOLUTE(.); + } >vector_user_lit :vector_user_lit_phdr + + .UserExceptionVector.text : ALIGN(4) + { + _UserExceptionVector_text_start = ABSOLUTE(.); + KEEP (*(.UserExceptionVector.text)) + _UserExceptionVector_text_end = ABSOLUTE(.); + } >vector_user_text :vector_user_text_phdr + + .DoubleExceptionVector.literal : ALIGN(4) + { + _DoubleExceptionVector_literal_start = ABSOLUTE(.); + *(.DoubleExceptionVector.literal) + _DoubleExceptionVector_literal_end = ABSOLUTE(.); + } >vector_double_lit :vector_double_lit_phdr + + .DoubleExceptionVector.text : ALIGN(4) + { + _DoubleExceptionVector_text_start = ABSOLUTE(.); + KEEP (*(.DoubleExceptionVector.text)) + _DoubleExceptionVector_text_end = ABSOLUTE(.); + } >vector_double_text :vector_double_text_phdr + + .rodata : ALIGN(4) + { + _rodata_start = ABSOLUTE(.); + *(.rodata) + *(.rodata.*) + *(.gnu.linkonce.r.*) + *(.rodata1) + __XT_EXCEPTION_TABLE__ = ABSOLUTE(.); + KEEP (*(.xt_except_table)) + KEEP (*(.gcc_except_table)) + *(.gnu.linkonce.e.*) + *(.gnu.version_r) + KEEP (*(.eh_frame)) + /* C++ constructor and destructor tables, properly ordered: */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + KEEP (*crtbegin.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + /* C++ exception handlers table: */ + __XT_EXCEPTION_DESCS__ = ABSOLUTE(.); + *(.xt_except_desc) + *(.gnu.linkonce.h.*) + __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.); + *(.xt_except_desc_end) + *(.dynamic) + *(.gnu.version_d) + . = ALIGN(4); /* this table MUST be 4-byte aligned */ + _bss_table_start = ABSOLUTE(.); + LONG(_bss_start) + LONG(_bss_end) + _bss_table_end = ABSOLUTE(.); + _rodata_end = ABSOLUTE(.); + } >sof_sram0 :sof_sram0_phdr + + .module_init : ALIGN(4) + { + _module_init_start = ABSOLUTE(.); + *(*.module_init) + _module_init_end = ABSOLUTE(.); + } >sof_sram0 :sof_sram0_phdr + + .text : ALIGN(4) + { + _stext = .; + _text_start = ABSOLUTE(.); + *(.entry.text) + *(.init.literal) + KEEP(*(.init)) + *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*) + *(.fini.literal) + KEEP(*(.fini)) + *(.gnu.version) + _text_end = ABSOLUTE(.); + _etext = .; + } >sof_sram0 :sof_sram0_phdr + + .reset.rodata : ALIGN(4) + { + _reset_rodata_start = ABSOLUTE(.); + *(.reset.rodata) + _reset_rodata_end = ABSOLUTE(.); + } >sof_sram0 :sof_sram0_phdr + + + .data : ALIGN(4) + { + _data_start = ABSOLUTE(.); + *(.data) + *(.data.*) + *(.gnu.linkonce.d.*) + KEEP(*(.gnu.linkonce.d.*personality*)) + *(.data1) + *(.sdata) + *(.sdata.*) + *(.gnu.linkonce.s.*) + *(.sdata2) + *(.sdata2.*) + *(.gnu.linkonce.s2.*) + KEEP(*(.jcr)) + _trace_ctx_start = ABSOLUTE(.); + *(.trace_ctx) + _trace_ctx_end = ABSOLUTE(.); + _data_end = ABSOLUTE(.); + } >sof_sram0 :sof_sram0_phdr + + .lit4 : ALIGN(4) + { + _lit4_start = ABSOLUTE(.); + *(*.lit4) + *(.lit4.*) + *(.gnu.linkonce.lit4.*) + _lit4_end = ABSOLUTE(.); + } >sof_sram0 :sof_sram0_phdr + + .bss (NOLOAD) : ALIGN(8) + { + . = ALIGN (8); + _bss_start = ABSOLUTE(.); + *(.dynsbss) + *(.sbss) + *(.sbss.*) + *(.gnu.linkonce.sb.*) + *(.scommon) + *(.sbss2) + *(.sbss2.*) + *(.gnu.linkonce.sb2.*) + *(.dynbss) + *(.bss) + *(.bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN (8); + _bss_end = ABSOLUTE(.); + } >sof_sram0 :sof_sram0_phdr + + /* stack */ + _end = SOF_STACK_END; + PROVIDE(end = SOF_STACK_END); + _stack_sentry = SOF_STACK_END; + __stack = SOF_STACK_BASE; + + .debug 0 : { *(.debug) } + .line 0 : { *(.line) } + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_sfnames 0 : { *(.debug_sfnames) } + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_info 0 : { *(.debug_info) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } + .debug_weaknames 0 : { *(.debug_weaknames) } + .debug_funcnames 0 : { *(.debug_funcnames) } + .debug_typenames 0 : { *(.debug_typenames) } + .debug_varnames 0 : { *(.debug_varnames) } + + .xt.insn 0 : + { + KEEP (*(.xt.insn)) + KEEP (*(.gnu.linkonce.x.*)) + } + .xt.prop 0 : + { + KEEP (*(.xt.prop)) + KEEP (*(.xt.prop.*)) + KEEP (*(.gnu.linkonce.prop.*)) + } + .xt.lit 0 : + { + KEEP (*(.xt.lit)) + KEEP (*(.xt.lit.*)) + KEEP (*(.gnu.linkonce.p.*)) + } + .xt.profile_range 0 : + { + KEEP (*(.xt.profile_range)) + KEEP (*(.gnu.linkonce.profile_range.*)) + } + .xt.profile_ranges 0 : + { + KEEP (*(.xt.profile_ranges)) + KEEP (*(.gnu.linkonce.xt.profile_ranges.*)) + } + .xt.profile_files 0 : + { + KEEP (*(.xt.profile_files)) + KEEP (*(.gnu.linkonce.xt.profile_files.*)) + } + + .system_heap (NOLOAD) : ALIGN(8) + { + . = ALIGN (32); + _system_heap_start = ABSOLUTE(.); + . = . + HEAP_SYSTEM_SIZE; + _system_heap_end = ABSOLUTE(.); + } >system_heap :system_heap_phdr + + .system_runtime_heap (NOLOAD) : ALIGN(8) + { + . = ALIGN (HEAP_BUF_ALIGNMENT); + _system_runtime_heap_start = ABSOLUTE(.); + . = . + HEAP_SYS_RUNTIME_SIZE; + _system_runtime_heap_end = ABSOLUTE(.); + } >system_runtime_heap :system_runtime_heap_phdr + + .runtime_heap (NOLOAD) : ALIGN(8) + { + . = ALIGN (32); + _runtime_heap_start = ABSOLUTE(.); + . = . + HEAP_RUNTIME_SIZE; + _runtime_heap_end = ABSOLUTE(.); + } >runtime_heap :runtime_heap_phdr + + .buffer_heap (NOLOAD) : ALIGN(8) + { + . = ALIGN (HEAP_BUF_ALIGNMENT); + _buffer_heap_start = ABSOLUTE(.); + . = . + HEAP_BUFFER_SIZE; + _buffer_heap_end = ABSOLUTE(.); + } >buffer_heap :buffer_heap_phdr + + .sof_stack (NOLOAD) : ALIGN(8) + { + . = ALIGN (4096); + _sof_stack_start = ABSOLUTE(.); + . = . + SOF_STACK_TOTAL_SIZE; + _sof_stack_end = ABSOLUTE(.); + } >sof_stack :sof_stack_phdr + + .static_uuid_entries (COPY) : ALIGN(1024) + { + *(*.static_uuids) + } > static_uuid_entries_seg :static_uuid_entries_phdr + + .static_log_entries (COPY) : ALIGN(1024) + { + *(*.static_log*) + } > static_log_entries_seg :static_log_entries_phdr + + .fw_ready : ALIGN(4) + { + KEEP (*(.fw_ready)) + KEEP (*(.fw_ready_metadata)) + } >sof_sram0 :sof_sram0_phdr + + .fw_metadata (COPY) : ALIGN(1024) + { + KEEP (*(.fw_metadata)) + . = ALIGN(_EXT_MAN_ALIGN_); + } >fw_metadata_seg :metadata_entries_phdr +} From 45df427a77dba2878d6beda64f47a53d1f9bef03 Mon Sep 17 00:00:00 2001 From: Allen-KH Cheng Date: Fri, 27 Aug 2021 14:29:44 +0800 Subject: [PATCH 05/15] platform: mtk: add support for mt8195 platform Add support for platform drivers : idc, irq, timer, clk dma. Add mtk mt8195 platform initialization. 1. MT8195 includes one Cadence HiFi-4 DSP, which support for four 32x32-bit MACs, some support for 72-bit accumulators, limited ability to support eight 32x16-bit MACs, a fourth VLIW slot and the ability to issue two 64-bit loads per cycle. 2. 25 interrupts 3. Clock Rate: DSP can operate at 720 MHz (0P75 V)/540 MHz (0P65 V)/370 MHz (0P6 V)/220 MHz (0P55 V) 4. DRAM: it can access data on DRAM by DMA or by CPU directly (through Cache). 5. 32x32-bit MACs 6. Supports SPM(System Power Manager) to control power sequence Signed-off-by: YC Hung Signed-off-by: Allen-KH Cheng --- .../mt8195/include/platform/drivers/idc.h | 32 +++ .../include/platform/drivers/interrupt.h | 152 ++++++++++++++ .../mt8195/include/platform/lib/clk.h | 35 ++++ .../mt8195/include/platform/lib/cpu.h | 21 ++ .../mt8195/include/platform/lib/dai.h | 18 ++ .../mt8195/include/platform/lib/dma.h | 29 +++ .../mt8195/include/platform/lib/mailbox.h | 74 +++++++ .../mt8195/include/platform/lib/pm_runtime.h | 65 ++++++ .../mt8195/include/platform/platform.h | 97 +++++++++ .../mt8195/include/platform/trace/trace.h | 32 +++ src/platform/mt8195/lib/clk.c | 48 +++++ src/platform/mt8195/lib/dai.c | 56 +++++ src/platform/mt8195/lib/dma.c | 55 +++++ src/platform/mt8195/platform.c | 196 ++++++++++++++++++ 14 files changed, 910 insertions(+) create mode 100644 src/platform/mt8195/include/platform/drivers/idc.h create mode 100644 src/platform/mt8195/include/platform/drivers/interrupt.h create mode 100644 src/platform/mt8195/include/platform/lib/clk.h create mode 100644 src/platform/mt8195/include/platform/lib/cpu.h create mode 100644 src/platform/mt8195/include/platform/lib/dai.h create mode 100644 src/platform/mt8195/include/platform/lib/dma.h create mode 100644 src/platform/mt8195/include/platform/lib/mailbox.h create mode 100644 src/platform/mt8195/include/platform/lib/pm_runtime.h create mode 100644 src/platform/mt8195/include/platform/platform.h create mode 100644 src/platform/mt8195/include/platform/trace/trace.h create mode 100644 src/platform/mt8195/lib/clk.c create mode 100644 src/platform/mt8195/lib/dai.c create mode 100644 src/platform/mt8195/lib/dma.c create mode 100644 src/platform/mt8195/platform.c diff --git a/src/platform/mt8195/include/platform/drivers/idc.h b/src/platform/mt8195/include/platform/drivers/idc.h new file mode 100644 index 000000000000..007d956d5f8b --- /dev/null +++ b/src/platform/mt8195/include/platform/drivers/idc.h @@ -0,0 +1,32 @@ +// SPDX-License-Identifier: BSD-3-Clause +// +// Copyright(c) 2021 Mediatek +// +// Author: YC Hung + +#ifdef __SOF_DRIVERS_IDC_H__ + +#ifndef __PLATFORM_DRIVERS_IDC_H__ +#define __PLATFORM_DRIVERS_IDC_H__ + +#include + +struct idc_msg; + +static inline int idc_send_msg(struct idc_msg *msg, uint32_t mode) +{ + return 0; +} + +static inline int idc_init(void) +{ + return 0; +} + +#endif /* __PLATFORM_DRIVERS_IDC_H__ */ + +#else + +#error "This file shouldn't be included from outside of sof/drivers/idc.h" + +#endif /* __SOF_DRIVERS_IDC_H__ */ diff --git a/src/platform/mt8195/include/platform/drivers/interrupt.h b/src/platform/mt8195/include/platform/drivers/interrupt.h new file mode 100644 index 000000000000..7cc528e74dd5 --- /dev/null +++ b/src/platform/mt8195/include/platform/drivers/interrupt.h @@ -0,0 +1,152 @@ +// SPDX-License-Identifier: BSD-3-Clause +// +// Copyright(c) 2021 Mediatek +// +// Author: Hailong Fan +// Allen-KH Cheng + +#ifdef __SOF_DRIVERS_INTERRUPT_H__ + +#ifndef __PLATFORM_DRIVERS_INTERRUPT_H__ +#define __PLATFORM_DRIVERS_INTERRUPT_H__ + +#include +#include + +#define PLATFORM_IRQ_HW_NUM XCHAL_NUM_INTERRUPTS +#define PLATFORM_IRQ_FIRST_CHILD PLATFORM_IRQ_HW_NUM +#define PLATFORM_IRQ_CHILDREN 32 + +/* IRQ numbers - wrt Tensilica DSP */ +#if CONFIG_XT_INTERRUPT_LEVEL_1 +#define IRQ_NUM_TIMER0 16 +#define IRQ_NUM_SOFTWARE0 21 +#define IRQ_NUM_EXT_LEVEL01 1 +#define IRQ_NUM_EXT_LEVEL23 23 +#define IRQ_EXT_DOMAIN0 IRQ_NUM_EXT_LEVEL01 +#define IRQ_EXT_DOMAIN1 IRQ_NUM_EXT_LEVEL23 +#define IRQ_EXT_DOMAIN0_OFFSET 4 +#define IRQ_MASK_SOFTWARE0 BIT(IRQ_NUM_SOFTWARE0) +#define IRQ_MASK_TIMER0 BIT(IRQ_NUM_TIMER0) +#define IRQ_MASK_GROUP16 BIT(IRQ_NUM_GROUP16) +#endif + +#if CONFIG_XT_INTERRUPT_LEVEL_2 +#define IRQ_NUM_SOFTWARE1 22 /* level 2 */ +#define IRQ_NUM_EXT_LEVEL09 9 /* Level 2 */ +#define IRQ_NUM_EXT_LEVEL24 24 /* Level 2 */ +#define IRQ_MASK_SOFTWARE1 BIT(IRQ_NUM_SOFTWARE1) +#define IRQ_MASK_GROUP17 BIT(IRQ_NUM_GROUP17) +#endif + +/* platform irq information */ +#define IRQ_TYPE_EDGE_RISING 0x00000001 +#define IRQ_TYPE_EDGE_FALLING 0x00000002 +#define IRQ_TYPE_LEVEL_HIGH 0x00000004 +#define IRQ_TYPE_LEVEL_LOW 0x00000008 + +/* int level */ +#define IRQ_INVALID 0xff +#define IRQ_MASK 0xff +#define IRQ_EXT_DOMAIN1_MASK 0x3FFFFFF0 +#define IRQ_EXT_DOMAIN2_MASK 0xFFFF +#define GET_INTERRUPT_ID(n) ((n) & IRQ_MASK) +#define LEVEL_SHFIT 8 +#define LEVEL_MASK 0xff +#define INT_LEVEL(n) ((n) << LEVEL_SHFIT) +#define GET_INTLEVEL(irq) (((irq) >> LEVEL_SHFIT) & LEVEL_MASK) +#define IRQ_LEVEL0 0 +#define IRQ_LEVEL1 1 + +/* + * IRQ = 0xcc-dd + * cc = int level + * dd = irq + * LX_MODULEX_IRQX_B = ( (0xcc << 8 ) | 0xdd ) + * All irq dispatch to level0 default + */ +#define INTERRUPT_ID(ID) (ID) + +#define L1_INT_IRQ_B (INT_LEVEL(1) | IRQ_INVALID) +#define L23_INT_IRQ_B (INT_LEVEL(23) | IRQ_INVALID) +#define L1_DSP_TIMER_IRQ0_B (INT_LEVEL(2) | INTERRUPT_ID(0)) +#define L1_DSP_TIMER_IRQ1_B (INT_LEVEL(3) | INTERRUPT_ID(1)) +#define L1_DSP_TIMER_IRQ2_B (INT_LEVEL(4) | INTERRUPT_ID(2)) +#define L1_DSP_TIMER_IRQ3_B (INT_LEVEL(5) | INTERRUPT_ID(3)) + +#define LX_CQDMA_IRQ0_B (INT_LEVEL(1) | INTERRUPT_ID(4)) +#define LX_CQDMA_IRQ1_B (INT_LEVEL(1) | INTERRUPT_ID(5)) +#define LX_CQDMA_IRQ2_B (INT_LEVEL(1) | INTERRUPT_ID(6)) +#define LX_CQDMA_IRQ3_B (INT_LEVEL(1) | INTERRUPT_ID(7)) +#define LX_UART_IRQ_B (INT_LEVEL(1) | INTERRUPT_ID(8)) +#define LX_AFE_IRQ_B (INT_LEVEL(1) | INTERRUPT_ID(9)) +#define LX_MCU_IRQ_B (INT_LEVEL(1) | INTERRUPT_ID(10)) +#define LX_I2C_IRQ4_B (INT_LEVEL(1) | INTERRUPT_ID(11)) +#define LX_I2C_IRQ5_B (INT_LEVEL(1) | INTERRUPT_ID(12)) +#define LX_RSVD_IRQ1_B (INT_LEVEL(1) | INTERRUPT_ID(13)) +#define LX_RSVD_IRQ2_B (INT_LEVEL(1) | INTERRUPT_ID(14)) +#define LX_ASRC_IRQ0_B (INT_LEVEL(1) | INTERRUPT_ID(15)) +#define LX_ASRC_IRQ1_B (INT_LEVEL(1) | INTERRUPT_ID(16)) +#define LX_ASRC_IRQ2_B (INT_LEVEL(1) | INTERRUPT_ID(17)) +#define LX_ASRC_IRQ3_B (INT_LEVEL(1) | INTERRUPT_ID(18)) +#define LX_ASRC_IRQ4_B (INT_LEVEL(1) | INTERRUPT_ID(19)) +#define LX_ASRC_IRQ5_B (INT_LEVEL(1) | INTERRUPT_ID(20)) +#define LX_ASRC_IRQ6_B (INT_LEVEL(1) | INTERRUPT_ID(21)) +#define LX_ASRC_IRQ7_B (INT_LEVEL(1) | INTERRUPT_ID(22)) +#define LX_ASRC_IRQ8_B (INT_LEVEL(1) | INTERRUPT_ID(23)) +#define LX_ASRC_IRQ9_B (INT_LEVEL(1) | INTERRUPT_ID(24)) +#define LX_ASRC_IRQ10_B (INT_LEVEL(1) | INTERRUPT_ID(25)) +#define LX_ASRC_IRQ11_B (INT_LEVEL(1) | INTERRUPT_ID(26)) +#define LX_ASRC_IRQ15_IRQ12_B (INT_LEVEL(1) | INTERRUPT_ID(27)) +#define LX_SPM_IRQ_B (INT_LEVEL(1) | INTERRUPT_ID(28)) +#define LX_SCP_IRQ_B (INT_LEVEL(1) | INTERRUPT_ID(29)) +#define LX_MBOX_IRQ0_B (INT_LEVEL(23) | INTERRUPT_ID(32)) +#define LX_MBOX_IRQ1_B (INT_LEVEL(23) | INTERRUPT_ID(33)) +#define LX_MBOX_IRQ2_B (INT_LEVEL(23) | INTERRUPT_ID(34)) +#define LX_MBOX_IRQ3_B (INT_LEVEL(23) | INTERRUPT_ID(35)) +#define LX_MBOX_IRQ4_B (INT_LEVEL(23) | INTERRUPT_ID(36)) +#define LX_MISC_NNA0_IRQ0_B (INT_LEVEL(23) | INTERRUPT_ID(37)) +#define LX_MISC_NNA0_IRQ1_B (INT_LEVEL(23) | INTERRUPT_ID(38)) +#define LX_MISC_NNA0_IRQ2_B (INT_LEVEL(23) | INTERRUPT_ID(39)) +#define LX_MISC_NNA1_IRQ0_B (INT_LEVEL(23) | INTERRUPT_ID(40)) +#define LX_MISC_NNA1_IRQ1_B (INT_LEVEL(23) | INTERRUPT_ID(41)) +#define LX_MISC_NNA1_IRQ2_B (INT_LEVEL(23) | INTERRUPT_ID(42)) +#define LX_ADSP_TIMTER_IRQ0_B (INT_LEVEL(23) | INTERRUPT_ID(43)) +#define LX_ADSP_TIMTER_IRQ1_B (INT_LEVEL(23) | INTERRUPT_ID(44)) +#define LX_ADSP_TIMTER_IRQ2_B (INT_LEVEL(23) | INTERRUPT_ID(45)) +#define LX_ADSP_TIMTER_IRQ3_B (INT_LEVEL(23) | INTERRUPT_ID(46)) +#define LX_OS_TIMTER_IRQ_B (INT_LEVEL(23) | INTERRUPT_ID(47)) + +#define MAX_IRQ_NUM 64 +#define DOMAIN1_MAX_IRQ_NUM 32 +#define MAX_INT_LEVEL 24 +#define AUDIO_IRQn LX_AFE_IRQ_B +/* + * irq register information + * INT 23/24 + * + */ +#define DSP_IRQ_POL MTK_DSP_RG_DSP_IRQ_POL +#define DSP_IRQ_EN MTK_DSP_DSP_IRQ_EN +#define DSP_IRQ_LEVEL MTK_DSP_DSP_IRQ_LEVEL +#define DSP_IRQ_STATUS MTK_DSP_DSP_IRQ_STATUS + +/* + * irq register information + * INT 0~15 + * + */ +#define RG_DSP_IRQ_POL MTK_DSP_RG_INT_POL_CTL0 +#define RG_DSP_IRQ_EN MTK_DSP_RG_INT_EN_CTL0 +#define RG_DSP_IRQ_LEVEL MTK_DSP_RG_INT_LV_CTL0 +#define RG_DSP_IRQ_STATUS MTK_DSP_RG_INT_STATUS0 + +uint32_t mtk_get_irq_domain_id(int32_t irq); + +#endif /* __PLATFORM_DRIVERS_INTERRUPT_H__ */ + +#else + +#error "This file shouldn't be included from outside of sof/drivers/interrupt.h" + +#endif /* __SOF_DRIVERS_INTERRUPT_H__ */ diff --git a/src/platform/mt8195/include/platform/lib/clk.h b/src/platform/mt8195/include/platform/lib/clk.h new file mode 100644 index 000000000000..4b26b7cb9891 --- /dev/null +++ b/src/platform/mt8195/include/platform/lib/clk.h @@ -0,0 +1,35 @@ +// SPDX-License-Identifier: BSD-3-Clause +// +// Copyright(c) 2021 Mediatek +// +// Author: YC Hung + +#ifdef __SOF_LIB_CLK_H__ + +#ifndef __PLATFORM_LIB_CLK_H__ +#define __PLATFORM_LIB_CLK_H__ + +#include + +struct sof; + +#define CLK_CPU(x) (x) + +#define CPU_DEFAULT_IDX 4 + +#define CLK_DEFAULT_CPU_HZ 720000000 +#define CLK_MAX_CPU_HZ 720000000 + +#define NUM_CLOCKS 1 + +#define NUM_CPU_FREQ 5 + +void platform_clock_init(struct sof *sof); + +#endif /* __PLATFORM_LIB_CLK_H__ */ + +#else + +#error "This file shouldn't be included from outside of sof/lib/clk.h" + +#endif /* __SOF_LIB_CLK_H__ */ diff --git a/src/platform/mt8195/include/platform/lib/cpu.h b/src/platform/mt8195/include/platform/lib/cpu.h new file mode 100644 index 000000000000..561495db2159 --- /dev/null +++ b/src/platform/mt8195/include/platform/lib/cpu.h @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: BSD-3-Clause +// +// Copyright(c) 2021 Mediatek +// +// Author: YC Hung + +#ifdef __SOF_LIB_CPU_H__ + +#ifndef __PLATFORM_LIB_CPU_H__ +#define __PLATFORM_LIB_CPU_H__ + +/** \brief Id of primary DSP core */ +#define PLATFORM_PRIMARY_CORE_ID 0 + +#endif /* __PLATFORM_LIB_CPU_H__ */ + +#else + +#error "This file shouldn't be included from outside of sof/lib/cpu.h" + +#endif /* __SOF_LIB_CPU_H__ */ diff --git a/src/platform/mt8195/include/platform/lib/dai.h b/src/platform/mt8195/include/platform/lib/dai.h new file mode 100644 index 000000000000..9dc0b5eef0f9 --- /dev/null +++ b/src/platform/mt8195/include/platform/lib/dai.h @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: BSD-3-Clause +// +// Copyright(c) 2021 Mediatek +// +// Author: YC Hung + +#ifdef __SOF_LIB_DAI_H__ + +#ifndef __PLATFORM_LIB_DAI_H__ +#define __PLATFORM_LIB_DAI_H__ + +#endif /* __PLATFORM_LIB_DAI_H__ */ + +#else + +#error "This file shouldn't be included from outside of sof/lib/dai.h" + +#endif /* __SOF_LIB_DAI_H__ */ diff --git a/src/platform/mt8195/include/platform/lib/dma.h b/src/platform/mt8195/include/platform/lib/dma.h new file mode 100644 index 000000000000..7fd824c5213a --- /dev/null +++ b/src/platform/mt8195/include/platform/lib/dma.h @@ -0,0 +1,29 @@ +// SPDX-License-Identifier: BSD-3-Clause +// +// Copyright(c) 2021 Mediatek +// +// Author: Bo Pan + +#ifdef __SOF_LIB_DMA_H__ + +#ifndef __PLATFORM_LIB_DMA_H__ +#define __PLATFORM_LIB_DMA_H__ + +#define PLATFORM_NUM_DMACS 2 + +/* max number of supported DMA channels */ +#define PLATFORM_MAX_DMA_CHAN 32 + +#define DMA_ID_AFE_MEMIF 0 +#define DMA_ID_HOST 1 + +#define dma_chan_irq(dma, chan) dma_irq(dma) +#define dma_chan_irq_name(dma, chan) dma_irq_name(dma) + +#endif /* __PLATFORM_LIB_DMA_H__ */ + +#else + +#error "This file shouldn't be included from outside of sof/lib/dma.h" + +#endif /* __SOF_LIB_DMA_H__ */ diff --git a/src/platform/mt8195/include/platform/lib/mailbox.h b/src/platform/mt8195/include/platform/lib/mailbox.h new file mode 100644 index 000000000000..f15d525162d8 --- /dev/null +++ b/src/platform/mt8195/include/platform/lib/mailbox.h @@ -0,0 +1,74 @@ +// SPDX-License-Identifier: BSD-3-Clause +// +// Copyright(c) 2021 Mediatek +// +// Author: YC Hung + +#ifdef __SOF_LIB_MAILBOX_H__ + +#ifndef __PLATFORM_LIB_MAILBOX_H__ +#define __PLATFORM_LIB_MAILBOX_H__ + +#include +#include +#include + +/* + * The Window Region on MT8195 SRAM is organised like this :- + * +--------------------------------------------------------------------------+ + * | Offset | Region | Size | + * +---------------------+----------------+-----------------------------------+ + * | SRAM_TRACE_BASE | Trace Buffer | SRAM_TRACE_SIZE | + * +---------------------+----------------+-----------------------------------+ + * | SRAM_DEBUG_BASE | Debug data | SRAM_DEBUG_SIZE | + * +---------------------+----------------+-----------------------------------+ + * | SRAM_INBOX_BASE | Inbox | SRAM_INBOX_SIZE | + * +---------------------+----------------+-----------------------------------+ + * | SRAM_OUTBOX_BASE | Outbox | SRAM_MAILBOX_SIZE | + * +---------------------+----------------+-----------------------------------+ + */ + +#define MAILBOX_DSPBOX_SIZE SRAM_OUTBOX_SIZE +#define MAILBOX_DSPBOX_BASE SRAM_OUTBOX_BASE +#define MAILBOX_DSPBOX_OFFSET SRAM_OUTBOX_OFFSET + +#define MAILBOX_HOSTBOX_SIZE SRAM_INBOX_SIZE +#define MAILBOX_HOSTBOX_BASE SRAM_INBOX_BASE +#define MAILBOX_HOSTBOX_OFFSET SRAM_INBOX_OFFSET + +#define MAILBOX_DEBUG_SIZE SRAM_DEBUG_SIZE +#define MAILBOX_DEBUG_BASE SRAM_DEBUG_BASE +#define MAILBOX_DEBUG_OFFSET SRAM_DEBUG_OFFSET + +#define MAILBOX_TRACE_SIZE SRAM_TRACE_SIZE +#define MAILBOX_TRACE_BASE SRAM_TRACE_BASE +#define MAILBOX_TRACE_OFFSET SRAM_TRACE_OFFSET + +#define MAILBOX_EXCEPTION_SIZE SRAM_EXCEPT_SIZE +#define MAILBOX_EXCEPTION_BASE SRAM_EXCEPT_BASE +#define MAILBOX_EXCEPTION_OFFSET SRAM_EXCEPT_OFFSET + +#define MAILBOX_STREAM_SIZE SRAM_STREAM_SIZE +#define MAILBOX_STREAM_BASE SRAM_STREAM_BASE +#define MAILBOX_STREAM_OFFSET SRAM_STREAM_OFFSET + +static inline void mailbox_sw_reg_write(size_t offset, uint32_t src) +{ + volatile uint32_t *ptr; + + ptr = (volatile uint32_t *)(MAILBOX_DEBUG_BASE + offset); + *ptr = src; +} + +#define ADSP_IPI_OP_REQ 0x1 +#define ADSP_IPI_OP_RSP 0x2 +void trigger_irq_to_host_req(void); +void trigger_irq_to_host_rsp(void); + +#endif /* __PLATFORM_LIB_MAILBOX_H__ */ + +#else + +#error "This file shouldn't be included from outside of sof/lib/mailbox.h" + +#endif /* __SOF_LIB_MAILBOX_H__ */ diff --git a/src/platform/mt8195/include/platform/lib/pm_runtime.h b/src/platform/mt8195/include/platform/lib/pm_runtime.h new file mode 100644 index 000000000000..f177a623231f --- /dev/null +++ b/src/platform/mt8195/include/platform/lib/pm_runtime.h @@ -0,0 +1,65 @@ +// SPDX-License-Identifier: BSD-3-Clause +// +// Copyright(c) 2021 Mediatek +// +// Author: YC Hung + +#ifdef __SOF_LIB_PM_RUNTIME_H__ + +#ifndef __PLATFORM_LIB_PM_RUNTIME_H__ +#define __PLATFORM_LIB_PM_RUNTIME_H__ + +#include + +struct pm_runtime_data; + +/** + * \brief Initializes platform specific runtime power management. + * \param[in,out] prd Runtime power management data. + */ +static inline void platform_pm_runtime_init(struct pm_runtime_data *prd) +{ +} + +/** + * \brief Retrieves platform specific power management resource. + * + * \param[in] context Type of power management context. + * \param[in] index Index of the device. + * \param[in] flags Flags, set of RPM_... + */ +static inline void platform_pm_runtime_get(uint32_t context, uint32_t index, uint32_t flags) +{ +} + +/** + * \brief Releases platform specific power management resource. + * + * \param[in] context Type of power management context. + * \param[in] index Index of the device. + * \param[in] flags Flags, set of RPM_... + */ +static inline void platform_pm_runtime_put(uint32_t context, uint32_t index, uint32_t flags) +{ +} + +static inline void platform_pm_runtime_enable(uint32_t context, uint32_t index) +{ +} + +static inline void platform_pm_runtime_disable(uint32_t context, uint32_t index) +{ +} + +static inline bool platform_pm_runtime_is_active(uint32_t context, uint32_t index) +{ + return false; +} + +#endif /* __PLATFORM_LIB_PM_RUNTIME_H__ */ + +#else + +#error "This file shouldn't be included from outside of sof/lib/pm_runtime.h" + +#endif /* __SOF_LIB_PM_RUNTIME_H__ */ diff --git a/src/platform/mt8195/include/platform/platform.h b/src/platform/mt8195/include/platform/platform.h new file mode 100644 index 000000000000..7d27ccf3c08b --- /dev/null +++ b/src/platform/mt8195/include/platform/platform.h @@ -0,0 +1,97 @@ +// SPDX-License-Identifier: BSD-3-Clause +// +// Copyright(c) 2021 Mediatek +// +// Author: YC Hung + +#ifdef __SOF_PLATFORM_H__ + +#ifndef __PLATFORM_PLATFORM_H__ +#define __PLATFORM_PLATFORM_H__ + +#if !defined(__ASSEMBLER__) && !defined(LINKER) + +#include +#include +#include +#include +#include +#include + +struct ll_schedule_domain; +struct timer; + +#define PLATFORM_DEFAULT_CLOCK CLK_CPU(0) +#define LPSRAM_SIZE 16384 + +/*MTK_TODO : use correct ipc interrupt , mailbox int group 16 bit 0*/ +/* IPC Interrupt */ +#define PLATFORM_IPC_INTERRUPT IRQ_MASK_GROUP16 +#define PLATFORM_IPC_INTERRUPT_NAME NULL + +/* Host page size */ +#define HOST_PAGE_SIZE 4096 +#define PLATFORM_PAGE_TABLE_SIZE 256 + +/* pipeline IRQ */ +#define PLATFORM_SCHEDULE_IRQ IRQ_NUM_SOFTWARE0 +#define PLATFORM_SCHEDULE_IRQ_NAME NULL + +/* Platform stream capabilities */ +#define PLATFORM_MAX_CHANNELS 4 +#define PLATFORM_MAX_STREAMS 5 + +/* local buffer size of DMA tracing */ +#define DMA_TRACE_LOCAL_SIZE HOST_PAGE_SIZE + +/* trace bytes flushed during panic */ +#define DMA_FLUSH_TRACE_SIZE (MAILBOX_TRACE_SIZE >> 2) + +/* the interval of DMA trace copying */ +#define DMA_TRACE_PERIOD 500000 + +/* + * the interval of reschedule DMA trace copying in special case like half + * fullness of local DMA trace buffer + */ +#define DMA_TRACE_RESCHEDULE_TIME 100 + +/* DSP default delay in cycles */ +#define PLATFORM_DEFAULT_DELAY 12 + +#define SRAM_REG_FW_STATUS 0x4 + +/* Platform defined panic code */ +static inline void platform_panic(uint32_t p) +{ + /* Store the error code in the debug box so the + * application processor can pick it up. Takes up 4 bytes + * from the debug box. + */ + mailbox_sw_reg_write(SRAM_REG_FW_STATUS, p); + + /* Notify application processor */ + trigger_irq_to_host_req(); +} + +/** + * \brief Platform specific CPU entering idle. + * May be power-optimized using platform specific capabilities. + * @param level Interrupt level. + */ +static inline void platform_wait_for_interrupt(int level) +{ + arch_wait_for_interrupt(level); +} + +extern intptr_t _module_init_start; +extern intptr_t _module_init_end; +#endif + +#endif /* __PLATFORM_PLATFORM_H__ */ + +#else + +#error "This file shouldn't be included from outside of sof/platform.h" + +#endif /* __SOF_PLATFORM_H__ */ diff --git a/src/platform/mt8195/include/platform/trace/trace.h b/src/platform/mt8195/include/platform/trace/trace.h new file mode 100644 index 000000000000..1baea82919f9 --- /dev/null +++ b/src/platform/mt8195/include/platform/trace/trace.h @@ -0,0 +1,32 @@ +// SPDX-License-Identifier: BSD-3-Clause +// +// Copyright(c) 2021 Mediatek +// +// Author: Allen-KH Cheng + +#ifdef __SOF_TRACE_TRACE_H__ + +#ifndef __PLATFORM_TRACE_TRACE_H__ +#define __PLATFORM_TRACE_TRACE_H__ + +#include +#include +#include +#include + +#define ADSP_TRACE_POINT (0x2) + +/* Platform defined trace code */ +#define platform_trace_point(__x) \ + do { \ + io_reg_write(MTK_DSP_MBOX_OUT_CMD_MSG0(2), __x); \ + io_reg_write(MTK_DSP_MBOX_OUT_CMD(2), ADSP_TRACE_POINT);\ + } while (0) + +#endif /* __PLATFORM_TRACE_TRACE_H__ */ + +#else + +#error "This file shouldn't be included from outside of sof/trace/trace.h" + +#endif /* __SOF_TRACE_TRACE_H__ */ diff --git a/src/platform/mt8195/lib/clk.c b/src/platform/mt8195/lib/clk.c new file mode 100644 index 000000000000..707a392d9c38 --- /dev/null +++ b/src/platform/mt8195/lib/clk.c @@ -0,0 +1,48 @@ +// SPDX-License-Identifier: BSD-3-Clause +// +// Copyright(c) 2021 Mediatek +// +// Author: YC Hung + +#include +#include +#include +#include +#include +#include +#include + +/*Use DSP Internal timer*/ +const struct freq_table platform_cpu_freq[] = { + { 13000000, 13000}, + { 26000000, 26000}, + { 370000000, 370000}, + { 540000000, 540000}, + { 720000000, 720000}, //default : CPU_DEFAULT_IDX +}; + +STATIC_ASSERT(ARRAY_SIZE(platform_cpu_freq) == NUM_CPU_FREQ, + invalid_number_of_cpu_frequencies); + +static SHARED_DATA struct clock_info platform_clocks_info[NUM_CLOCKS]; + +void platform_clock_init(struct sof *sof) +{ + int i; + + sof->clocks = platform_clocks_info; + + for (i = 0; i < CONFIG_CORE_COUNT; i++) { + sof->clocks[i] = (struct clock_info){ + .freqs_num = NUM_CPU_FREQ, + .freqs = platform_cpu_freq, + .default_freq_idx = CPU_DEFAULT_IDX, + .current_freq_idx = CPU_DEFAULT_IDX, + .notification_id = NOTIFIER_ID_CPU_FREQ, + .notification_mask = NOTIFIER_TARGET_CORE_MASK(i), + .set_freq = NULL, + }; + + spinlock_init(&sof->clocks[i].lock); + } +} diff --git a/src/platform/mt8195/lib/dai.c b/src/platform/mt8195/lib/dai.c new file mode 100644 index 000000000000..978146d2d83e --- /dev/null +++ b/src/platform/mt8195/lib/dai.c @@ -0,0 +1,56 @@ +// SPDX-License-Identifier: BSD-3-Clause +// +// Copyright(c) 2021 Mediatek +// +// Author: YC Hung + +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +static int afe_dai_handshake[MT8195_DAI_NUM] = { + AFE_HANDSHAKE(MT8195_AFE_IO_ETDM2_OUT, MT8195_IRQ_13, MT8195_MEMIF_DL2), + AFE_HANDSHAKE(MT8195_AFE_IO_ETDM1_OUT, MT8195_IRQ_14, MT8195_MEMIF_DL3), + AFE_HANDSHAKE(MT8195_AFE_IO_UL_SRC1, MT8195_IRQ_21, MT8195_MEMIF_UL4), + AFE_HANDSHAKE(MT8195_AFE_IO_ETDM2_IN, MT8195_IRQ_22, MT8195_MEMIF_UL5), +}; + +static SHARED_DATA struct dai afe_dai[MT8195_DAI_NUM]; + +const struct dai_type_info dti[] = { + { + .type = SOF_DAI_MEDIATEK_AFE, + .dai_array = afe_dai, + .num_dais = ARRAY_SIZE(afe_dai), + }, +}; + +const struct dai_info lib_dai = { + .dai_type_array = dti, + .num_dai_types = ARRAY_SIZE(dti), +}; + +int dai_init(struct sof *sof) +{ + int i; + + /* initialize spin locks early to enable ref counting */ + for (i = 0; i < ARRAY_SIZE(afe_dai); i++) { + spinlock_init(&afe_dai[i].lock); + afe_dai[i].index = AFE_HS_GET_DAI(afe_dai_handshake[i]); + afe_dai[i].drv = &afe_dai_driver; + /* TODO, fifo[0] change to target playback or capture */ + afe_dai[i].plat_data.fifo[0].handshake = afe_dai_handshake[i]; + } + + sof->dai_info = &lib_dai; + + return 0; +} diff --git a/src/platform/mt8195/lib/dma.c b/src/platform/mt8195/lib/dma.c new file mode 100644 index 000000000000..3841a3badbbc --- /dev/null +++ b/src/platform/mt8195/lib/dma.c @@ -0,0 +1,55 @@ +// SPDX-License-Identifier: BSD-3-Clause +// +// Copyright(c) 2021 Mediatek +// +// Author: YC Hung + +#include +#include +#include +#include +#include +#include + +#include +#include + +extern struct dma_ops dummy_dma_ops; +extern struct dma_ops memif_ops; + +SHARED_DATA struct dma dma[PLATFORM_NUM_DMACS] = { +{ + .plat_data = { + .id = DMA_ID_HOST, + .dir = DMA_DIR_HMEM_TO_LMEM | DMA_DIR_LMEM_TO_HMEM, + .devs = DMA_DEV_HOST, + .channels = 16, + }, + .ops = &dummy_dma_ops, +}, +{ + .plat_data = { + .id = DMA_ID_AFE_MEMIF, + .dir = DMA_DIR_MEM_TO_DEV | DMA_DIR_DEV_TO_MEM, + .devs = DMA_DEV_AFE_MEMIF, + .base = AFE_BASE_ADDR, + .channels = MT8195_MEMIF_NUM, + }, + .ops = &memif_ops, +}, +}; + +const struct dma_info lib_dma = { .dma_array = dma, .num_dmas = ARRAY_SIZE(dma) }; + +int dmac_init(struct sof *sof) +{ + int i; + + /* early lock initialization for ref counting */ + for (i = 0; i < ARRAY_SIZE(dma); i++) + spinlock_init(&dma[i].lock); + + sof->dma_info = &lib_dma; + + return 0; +} diff --git a/src/platform/mt8195/platform.c b/src/platform/mt8195/platform.c new file mode 100644 index 000000000000..ba0b082e4347 --- /dev/null +++ b/src/platform/mt8195/platform.c @@ -0,0 +1,196 @@ +// SPDX-License-Identifier: BSD-3-Clause +// +// Copyright(c) 2021 Mediatek +// +// Author: YC Hung +// Allen-KH Cheng + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +struct sof; + +static const struct sof_ipc_fw_ready ready + __section(".fw_ready") = { + .hdr = { + .cmd = SOF_IPC_FW_READY, + .size = sizeof(struct sof_ipc_fw_ready), + }, + /* dspbox is for DSP initiated IPC, hostbox is for host initiated IPC */ + .version = { + .hdr.size = sizeof(struct sof_ipc_fw_version), + .micro = SOF_MICRO, + .minor = SOF_MINOR, + .major = SOF_MAJOR, + .tag = SOF_TAG, + .abi_version = SOF_ABI_VERSION, + .src_hash = SOF_SRC_HASH, + }, + .flags = DEBUG_SET_FW_READY_FLAGS, +}; + +#define NUM_IMX_WINDOWS 6 + +const struct ext_man_windows xsram_window + __aligned(EXT_MAN_ALIGN) __section(".fw_metadata") __unused = { + .hdr = { + .type = EXT_MAN_ELEM_WINDOW, + .elem_size = ALIGN_UP_COMPILE(sizeof(struct ext_man_windows), EXT_MAN_ALIGN), + }, + .window = { + .ext_hdr = { + .hdr.cmd = SOF_IPC_FW_READY, + .hdr.size = sizeof(struct sof_ipc_window), + .type = SOF_IPC_EXT_WINDOW, + }, + .num_windows = NUM_IMX_WINDOWS, + .window = { + { + .type = SOF_IPC_REGION_UPBOX, + .id = 0, /* map to host window 0 */ + .flags = 0, /* TODO: set later */ + .size = MAILBOX_DSPBOX_SIZE, + .offset = MAILBOX_DSPBOX_OFFSET, + }, + { + .type = SOF_IPC_REGION_DOWNBOX, + .id = 0, /* map to host window 0 */ + .flags = 0, /* TODO: set later */ + .size = MAILBOX_HOSTBOX_SIZE, + .offset = MAILBOX_HOSTBOX_OFFSET, + }, + { + .type = SOF_IPC_REGION_DEBUG, + .id = 0, /* map to host window 0 */ + .flags = 0, /* TODO: set later */ + .size = MAILBOX_DEBUG_SIZE, + .offset = MAILBOX_DEBUG_OFFSET, + }, + { + .type = SOF_IPC_REGION_TRACE, + .id = 0, /* map to host window 0 */ + .flags = 0, /* TODO: set later */ + .size = MAILBOX_TRACE_SIZE, + .offset = MAILBOX_TRACE_OFFSET, + }, + { + .type = SOF_IPC_REGION_STREAM, + .id = 0, /* map to host window 0 */ + .flags = 0, /* TODO: set later */ + .size = MAILBOX_STREAM_SIZE, + .offset = MAILBOX_STREAM_OFFSET, + }, + { + .type = SOF_IPC_REGION_EXCEPTION, + .id = 0, /* map to host window 0 */ + .flags = 0, /* TODO: set later */ + .size = MAILBOX_EXCEPTION_SIZE, + .offset = MAILBOX_EXCEPTION_OFFSET, + }, + }, + } +}; + +static SHARED_DATA struct timer timer = { + .id = TIMER0, + .irq = IRQ_NUM_TIMER0, +}; + + +int platform_boot_complete(uint32_t boot_message) +{ + mailbox_dspbox_write(0, &ready, sizeof(ready)); + + /* now interrupt host to tell it we are done booting */ + trigger_irq_to_host_req(); + + /* boot now complete so we can relax the CPU */ + /* For now skip this to gain more processing performance + * for SRC component. + */ + clock_set_freq(CLK_CPU(cpu_get_id()), CLK_DEFAULT_CPU_HZ); + + return 0; +} + +int platform_init(struct sof *sof) +{ + int ret; + + sof->platform_timer = &timer; + sof->cpu_timers = &timer; + + platform_interrupt_init(); + platform_clock_init(sof); + scheduler_init_edf(); + + /* init low latency domains and schedulers */ + sof->platform_timer_domain = timer_domain_init(sof->platform_timer, PLATFORM_DEFAULT_CLOCK); + scheduler_init_ll(sof->platform_timer_domain); + + platform_timer_start(sof->platform_timer); + sa_init(sof, CONFIG_SYSTICK_PERIOD); + + clock_set_freq(CLK_CPU(cpu_get_id()), CLK_MAX_CPU_HZ); + + /* init DMA */ + ret = dmac_init(sof); + if (ret < 0) + return -ENODEV; + + /* Init platform domain */ + sof->platform_dma_domain = dma_multi_chan_domain_init(&sof->dma_info->dma_array[0], 1, + PLATFORM_DEFAULT_CLOCK, false); + scheduler_init_ll(sof->platform_dma_domain); + + /* initialize the host IPC mechanims */ + ipc_init(sof); + + ret = dai_init(sof); + if (ret < 0) + return -ENODEV; + +#if CONFIG_TRACE + /* Initialize DMA for Trace*/ + trace_point(TRACE_BOOT_PLATFORM_DMA_TRACE); + dma_trace_init_complete(sof->dmat); +#endif + + /* show heap status */ + heap_trace_all(1); + + return 0; +} + +int platform_context_save(struct sof *sof) +{ + return 0; +} From abcc6d6439b93541fa5a312a05012d859b6b2db6 Mon Sep 17 00:00:00 2001 From: Allen-KH Cheng Date: Fri, 3 Sep 2021 18:16:56 +0800 Subject: [PATCH 06/15] mt8195: add compile support for mt8195 Add mt8195 driver and platform compile support. Signed-off-by: YC Hung Signed-off-by: Allen-KH Cheng --- src/drivers/CMakeLists.txt | 4 ++++ src/drivers/mediatek/CMakeLists.txt | 5 +++++ src/drivers/mediatek/mt8195/CMakeLists.txt | 6 ++++++ src/platform/CMakeLists.txt | 2 ++ src/platform/mt8195/CMakeLists.txt | 6 ++++++ src/platform/mt8195/lib/CMakeLists.txt | 8 ++++++++ 6 files changed, 31 insertions(+) create mode 100644 src/drivers/mediatek/CMakeLists.txt create mode 100644 src/drivers/mediatek/mt8195/CMakeLists.txt create mode 100644 src/platform/mt8195/CMakeLists.txt create mode 100644 src/platform/mt8195/lib/CMakeLists.txt diff --git a/src/drivers/CMakeLists.txt b/src/drivers/CMakeLists.txt index 01b40d7b6c98..5195a5e777fd 100644 --- a/src/drivers/CMakeLists.txt +++ b/src/drivers/CMakeLists.txt @@ -12,6 +12,10 @@ if(CONFIG_RENOIR) add_subdirectory(amd) endif() +if(CONFIG_MEDIATEK) + add_subdirectory(mediatek) +endif() + if(CONFIG_LIBRARY) add_subdirectory(host) return() diff --git a/src/drivers/mediatek/CMakeLists.txt b/src/drivers/mediatek/CMakeLists.txt new file mode 100644 index 000000000000..c55da9994fdb --- /dev/null +++ b/src/drivers/mediatek/CMakeLists.txt @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: BSD-3-Clause + +if(CONFIG_MT8195) + add_subdirectory(mt8195) +endif() diff --git a/src/drivers/mediatek/mt8195/CMakeLists.txt b/src/drivers/mediatek/mt8195/CMakeLists.txt new file mode 100644 index 000000000000..d4fafaf25d08 --- /dev/null +++ b/src/drivers/mediatek/mt8195/CMakeLists.txt @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: BSD-3-Clause + +add_local_sources(sof ipc.c timer.c + interrupt.c +) + diff --git a/src/platform/CMakeLists.txt b/src/platform/CMakeLists.txt index 875d299cd427..a2dc238f1a2a 100644 --- a/src/platform/CMakeLists.txt +++ b/src/platform/CMakeLists.txt @@ -27,6 +27,8 @@ elseif(CONFIG_IMX8ULP) add_subdirectory(imx8ulp) elseif(CONFIG_RENOIR) add_subdirectory(amd) +elseif(CONFIG_MT8195) + add_subdirectory(mt8195) endif() if(CONFIG_CAVS) diff --git a/src/platform/mt8195/CMakeLists.txt b/src/platform/mt8195/CMakeLists.txt new file mode 100644 index 000000000000..3d3806b32bf0 --- /dev/null +++ b/src/platform/mt8195/CMakeLists.txt @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: BSD-3-Clause + +add_subdirectory(lib) + +add_local_sources(sof platform.c) +target_include_directories(sof_options INTERFACE ${PROJECT_SOURCE_DIR}/src/platform/mt8195/include/platform) diff --git a/src/platform/mt8195/lib/CMakeLists.txt b/src/platform/mt8195/lib/CMakeLists.txt new file mode 100644 index 000000000000..ef71f8eea6cd --- /dev/null +++ b/src/platform/mt8195/lib/CMakeLists.txt @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: BSD-3-Clause + +add_local_sources(sof + clk.c + dma.c + memory.c + dai.c +) From 96123ad14d200181e42d535de8ce819febb243ac Mon Sep 17 00:00:00 2001 From: Allen-KH Cheng Date: Fri, 27 Aug 2021 19:31:19 +0800 Subject: [PATCH 07/15] drivers: mtk: add afe driver for mtk mt8195 Add afe driver for memif/sinegen. Add afe-dai.c/afe-drv.c/afe-memif.c for afe common driver AFE : Audio Front End The audio front-end essentially consists of voice and audio data paths. frontend (memif) : memory interface, UL (uplink for capture), DL(downlink for playback) backend: TDM In, TMD out, DMIC, GASRC, etc interconn: inter-connection, connect frontends backends as DSP path Note: TEST_SGEN macro define is just for test Signed-off-by: YC Hung Signed-off-by: Allen-KH Cheng --- src/drivers/mediatek/mt8195/afe-dai.c | 116 ++++ src/drivers/mediatek/mt8195/afe-drv.c | 414 ++++++++++++++ src/drivers/mediatek/mt8195/afe-memif.c | 732 ++++++++++++++++++++++++ src/include/ipc/dai-mediatek.h | 25 + src/include/ipc/dai.h | 5 +- src/include/sof/drivers/afe-dai.h | 29 + src/include/sof/drivers/afe-drv.h | 169 ++++++ src/include/sof/drivers/afe-memif.h | 24 + src/include/sof/lib/dma.h | 1 + src/ipc/ipc3/dai.c | 8 + 10 files changed, 1522 insertions(+), 1 deletion(-) create mode 100644 src/drivers/mediatek/mt8195/afe-dai.c create mode 100644 src/drivers/mediatek/mt8195/afe-drv.c create mode 100644 src/drivers/mediatek/mt8195/afe-memif.c create mode 100644 src/include/ipc/dai-mediatek.h create mode 100644 src/include/sof/drivers/afe-dai.h create mode 100644 src/include/sof/drivers/afe-drv.h create mode 100644 src/include/sof/drivers/afe-memif.h diff --git a/src/drivers/mediatek/mt8195/afe-dai.c b/src/drivers/mediatek/mt8195/afe-dai.c new file mode 100644 index 000000000000..110c9b528a3e --- /dev/null +++ b/src/drivers/mediatek/mt8195/afe-dai.c @@ -0,0 +1,116 @@ +// SPDX-License-Identifier: BSD-3-Clause +// +// Copyright(c) 2021 Mediatek +// +// Author: Bo Pan +// YC Hung + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* 30290c76-6a05-4784-8464-c21f09cee87e */ +DECLARE_SOF_UUID("afe-dai", afe_dai_uuid, 0x30290c76, 0x6a05, 0x4784, + 0x84, 0x64, 0xc2, 0x1f, 0x09, 0xce, 0xe8, 0x7e); + +DECLARE_TR_CTX(afe_dai_tr, SOF_UUID(afe_dai_uuid), LOG_LEVEL_INFO); + +static int afe_dai_drv_trigger(struct dai *dai, int cmd, int direction) +{ + return 0; +} + +static int afe_dai_drv_set_config(struct dai *dai, struct ipc_config_dai *common_config, + void *spec_config) +{ + struct sof_ipc_dai_config *config = spec_config; + struct mtk_base_afe *afe = dai_get_drvdata(dai); + + afe_dai_set_config(afe, + dai->index, + config->afe.dai_channels, + config->afe.dai_rate, + config->afe.dai_format); + return 0; +} + +/* get HDA hw params */ +static int afe_dai_drv_get_hw_params(struct dai *dai, struct sof_ipc_stream_params *params, int dir) +{ + struct mtk_base_afe *afe = dai_get_drvdata(dai); + unsigned int channel, rate, format; + + afe_dai_get_config(afe, dai->index, &channel, &rate, &format); + params->rate = rate; + params->channels = channel; + params->buffer_fmt = format; + params->frame_fmt = format; + + return 0; +} + +static int afe_dai_drv_probe(struct dai *dai) +{ + struct mtk_base_afe *afe = afe_get(); + + dai_info(dai, "afe_dai_probe()"); + + if (dai_get_drvdata(dai)) + return -EEXIST; + + dai_set_drvdata(dai, afe); + + return 0; +} + +static int afe_dai_drv_remove(struct dai *dai) +{ + dai_info(dai, "afe_dai_remove()"); + + return 0; +} + +static int afe_dai_drv_dummy(struct dai *dai) +{ + return 0; +} + +static int afe_dai_drv_get_handshake(struct dai *dai, int direction, int stream_id) +{ + return (int)dai->plat_data.fifo[0].handshake; +} + +static int afe_dai_drv_get_fifo(struct dai *dai, int direction, int stream_id) +{ + return 0; +} + +const struct dai_driver afe_dai_driver = { + .type = SOF_DAI_MEDIATEK_AFE, + .uid = SOF_UUID(afe_dai_uuid), + .tctx = &afe_dai_tr, + .dma_dev = DMA_DEV_AFE_MEMIF, + .ops = { + .trigger = afe_dai_drv_trigger, + .set_config = afe_dai_drv_set_config, + .pm_context_store = afe_dai_drv_dummy, + .pm_context_restore = afe_dai_drv_dummy, + .get_hw_params = afe_dai_drv_get_hw_params, + .get_handshake = afe_dai_drv_get_handshake, + .get_fifo = afe_dai_drv_get_fifo, + .probe = afe_dai_drv_probe, + .remove = afe_dai_drv_remove, + }, +}; diff --git a/src/drivers/mediatek/mt8195/afe-drv.c b/src/drivers/mediatek/mt8195/afe-drv.c new file mode 100644 index 000000000000..3ae30e718c1b --- /dev/null +++ b/src/drivers/mediatek/mt8195/afe-drv.c @@ -0,0 +1,414 @@ +// SPDX-License-Identifier: BSD-3-Clause +// +// Copyright(c) 2021 Mediatek +// +// Author: Bo Pan +// YC Hung + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/*#define AFE_DRV_LOG*/ +static struct mtk_base_afe mtk_afe; + +#ifndef AFE_DRV_LOG +#undef printf +#define printf(format, ...) +#endif + +DECLARE_SOF_UUID("afedrv", afedrv_uuid, 0x4e8f16d1, 0xe935, 0x41f4, + 0xb9, 0x9e, 0x42, 0xc5, 0x7e, 0x74, 0x57, 0x84); + +DECLARE_TR_CTX(afedrv_tr, SOF_UUID(afedrv_uuid), LOG_LEVEL_INFO); + +static inline void afe_reg_read(struct mtk_base_afe *afe, uint32_t reg, uint32_t *value) +{ + *value = io_reg_read((uint32_t)((char *)afe->base + reg)); + tr_dbg(&afedrv_tr, "r_reg:0x%x, value:0x%x\n", reg, *value); +} + +static inline void afe_reg_write(struct mtk_base_afe *afe, uint32_t reg, uint32_t value) +{ + io_reg_write((uint32_t)((char *)afe->base + reg), value); + tr_dbg(&afedrv_tr, "w_reg:0x%x, value:0x%x\n", reg, value); +} + +static inline void afe_reg_update_bits(struct mtk_base_afe *afe, uint32_t reg, uint32_t mask, + uint32_t value) +{ + io_reg_update_bits((uint32_t)((char *)afe->base + reg), mask, value); + tr_dbg(&afedrv_tr, "u_reg:0x%x, value:0x%x\n", reg, value); +} + +static int afe_memif_set_channel(struct mtk_base_afe *afe, int id, unsigned int channel) +{ + struct mtk_base_afe_memif *memif = &afe->memif[id]; + unsigned int mono; + + if (memif->data->mono_shift < 0) + return 0; + + if (memif->data->ch_num_reg >= 0) { + afe_reg_update_bits(afe, memif->data->ch_num_reg, + memif->data->ch_num_maskbit << memif->data->ch_num_shift, + channel << memif->data->ch_num_shift); + } + + if (memif->data->quad_ch_mask) { + unsigned int quad_ch = channel == 4; + + afe_reg_update_bits(afe, memif->data->quad_ch_reg, + memif->data->quad_ch_mask << memif->data->quad_ch_shift, + quad_ch << memif->data->quad_ch_shift); + } + + mono = (bool)memif->data->mono_invert ^ (channel == 1); + afe_reg_update_bits(afe, memif->data->mono_reg, 1 << memif->data->mono_shift, + mono << memif->data->mono_shift); + return 0; +} + +static int afe_memif_set_rate(struct mtk_base_afe *afe, int id, unsigned int rate) +{ + struct mtk_base_afe_memif *memif = &afe->memif[id]; + int fs; + + fs = afe->afe_fs(rate, memif->data->id); + if (fs < 0) + return -EINVAL; + + afe_reg_update_bits(afe, memif->data->fs_reg, + memif->data->fs_maskbit << memif->data->fs_shift, + fs << memif->data->fs_shift); + + return 0; +} + +static int afe_memif_set_format(struct mtk_base_afe *afe, int id, unsigned int format) +{ + struct mtk_base_afe_memif *memif = &afe->memif[id]; + int hd_audio; + int memif_32bit_supported = afe->memif_32bit_supported; + + /* set hd mode */ + switch (format) { + case SOF_IPC_FRAME_S16_LE: + hd_audio = 0; + break; + case SOF_IPC_FRAME_S32_LE: + case SOF_IPC_FRAME_S24_4LE: + if (memif_32bit_supported) + hd_audio = 2; + else + hd_audio = 1; + break; + default: + return -EINVAL; + } + + afe_reg_update_bits(afe, memif->data->hd_reg, 0x3 << memif->data->hd_shift, + hd_audio << memif->data->hd_shift); + return 0; +} + +int afe_memif_set_params(struct mtk_base_afe *afe, int id, unsigned int channel, unsigned int rate, + unsigned int format) +{ + int ret; + + ret = afe_memif_set_channel(afe, id, channel); + if (ret < 0) + return ret; + ret = afe_memif_set_rate(afe, id, rate); + if (ret < 0) + return ret; + ret = afe_memif_set_format(afe, id, format); + if (ret < 0) + return ret; + /* TODO IRQ direction, irq format setting ? */ + + return ret; +} + +int afe_memif_set_addr(struct mtk_base_afe *afe, int id, unsigned int dma_addr, + unsigned int dma_bytes) +{ + struct mtk_base_afe_memif *memif = &afe->memif[id]; + int msb_at_bit33 = 0; /* for dsp side only support 32bit address */ + unsigned int phys_buf_addr; + unsigned int phys_buf_addr_upper_32 = 0; /* for dsp side only support 32bit address */ + + memif->dma_addr = dma_addr; + + /* convert adsp address to afe address */ + if (afe->adsp2afe_addr) + dma_addr = afe->adsp2afe_addr(dma_addr); + + phys_buf_addr = dma_addr; + + memif->afe_addr = phys_buf_addr; + memif->buffer_size = dma_bytes; + tr_dbg(&afedrv_tr, "dma_addr:%u, size:%u\n", dma_addr, dma_bytes); + /* start */ + afe_reg_write(afe, memif->data->reg_ofs_base, phys_buf_addr); + /* end */ + if (memif->data->reg_ofs_end) + afe_reg_write(afe, memif->data->reg_ofs_end, phys_buf_addr + dma_bytes - 1); + else + afe_reg_write(afe, memif->data->reg_ofs_base + afe->base_end_offset, + phys_buf_addr + dma_bytes - 1); + + /* set start, end, upper 32 bits */ + if (memif->data->reg_ofs_base_msb) { + afe_reg_write(afe, memif->data->reg_ofs_base_msb, phys_buf_addr_upper_32); + afe_reg_write(afe, memif->data->reg_ofs_end_msb, phys_buf_addr_upper_32); + } + + /* set MSB to 33-bit */ + if (memif->data->msb_reg >= 0) + afe_reg_update_bits(afe, memif->data->msb_reg, 1 << memif->data->msb_shift, + msb_at_bit33 << memif->data->msb_shift); + + /* set MSB to 33-bit, for memif end address */ + if (memif->data->msb2_reg >= 0) + afe_reg_update_bits(afe, memif->data->msb2_reg, 1 << memif->data->msb2_shift, + msb_at_bit33 << memif->data->msb2_shift); + + return 0; +} + +int afe_memif_set_enable(struct mtk_base_afe *afe, int id, int enable) +{ + const struct mtk_base_memif_data *memif_data = afe->memif[id].data; + + if (memif_data->enable_shift < 0) + return 0; + + /* enable agent */ + /* TODO: enable/disable should in different sequence? */ + if (memif_data->agent_disable_reg > 0) { + afe_reg_update_bits(afe, memif_data->agent_disable_reg, + 1 << memif_data->agent_disable_shift, + (!enable) << memif_data->agent_disable_shift); + } + + afe_reg_update_bits(afe, memif_data->enable_reg, 1 << memif_data->enable_shift, + enable << memif_data->enable_shift); + + return 0; +} + +int afe_memif_get_direction(struct mtk_base_afe *afe, int id) +{ + const struct mtk_base_memif_data *memif_data = afe->memif[id].data; + + if (memif_data->id >= 0 && memif_data->id < afe->memif_dl_num) + return MEM_DIR_PLAYBACK; + return MEM_DIR_CAPTURE; +} + +unsigned int afe_memif_get_cur_position(struct mtk_base_afe *afe, int id) +{ + const struct mtk_base_memif_data *memif_data = afe->memif[id].data; + unsigned int hw_ptr; + + if (memif_data->reg_ofs_cur < 0) + return 0; + afe_reg_read(afe, memif_data->reg_ofs_cur, &hw_ptr); + + /* convert afe address to adsp address */ + if (afe->afe2adsp_addr) + hw_ptr = afe->afe2adsp_addr(hw_ptr); + return hw_ptr; +} + +int afe_dai_set_config(struct mtk_base_afe *afe, int id, unsigned int channel, unsigned int rate, + unsigned int format) +{ + struct mtk_base_afe_dai *dai = &afe->dais[id]; + + /* TODO 1. if need use dai->id to search target dai */ + /* TODO 1. if need a status to control the dai status */ + + if (id >= afe->dais_size) + return -EINVAL; + + tr_info(&afedrv_tr, "afe_dai_set_config, id:%d\n", id); + + dai = &afe->dais[id]; + dai->channel = channel; + dai->format = format; + dai->rate = rate; + + tr_info(&afedrv_tr, "dai:%d set: format:%d, rate:%d, channel:%d\n", id, format, rate, + channel); + + return 0; +} + +int afe_dai_get_config(struct mtk_base_afe *afe, int id, unsigned int *channel, unsigned int *rate, + unsigned int *format) +{ + struct mtk_base_afe_dai *dai = &afe->dais[id]; + + /* TODO 1. if need use dai->id to search target dai */ + /* TODO 1. if need a status to control the dai status */ + tr_info(&afedrv_tr, "afe_dai_get_config, id:%d\n", id); + + if (id >= afe->dais_size || id < 0) { + tr_err(&afedrv_tr, "afe_dai_get_config , invalid id:%d\n", id); + return -EINVAL; + } + dai = &afe->dais[id]; + + *channel = dai->channel; + *rate = dai->rate; + *format = dai->format; + + tr_info(&afedrv_tr, "dai:%d get: format:%d, rate:%d, channel:%d\n", id, *format, *rate, + *channel); + + return 0; +} + +/* TODO, IRQ common register name need use config? */ +int afe_irq_get_status(struct mtk_base_afe *afe, int id) +{ + return 0; +} + +int afe_irq_clear(struct mtk_base_afe *afe, int id) +{ + return 0; +} + +int afe_irq_config(struct mtk_base_afe *afe, int id, unsigned int rate, unsigned int period) +{ + struct mtk_base_afe_irq *irq = &afe->irqs[id]; + unsigned int fs; + + afe_reg_update_bits(afe, irq->irq_data->irq_cnt_reg, + irq->irq_data->irq_cnt_maskbit << irq->irq_data->irq_cnt_shift, + period << irq->irq_data->irq_cnt_shift); + + /* set irq fs */ + fs = afe->irq_fs(rate); + + if (fs < 0) + return -EINVAL; + + afe_reg_update_bits(afe, irq->irq_data->irq_fs_reg, + irq->irq_data->irq_fs_maskbit << irq->irq_data->irq_fs_shift, + fs << irq->irq_data->irq_fs_shift); + return 0; +} + +/* TODO, for dma based scheduler*/ +int afe_irq_enable(struct mtk_base_afe *afe, int id) +{ + return 0; +} + +int afe_irq_disable(struct mtk_base_afe *afe, int id) +{ + return 0; +} + +struct mtk_base_afe *afe_get(void) +{ + return &mtk_afe; +} + +int afe_probe(struct mtk_base_afe *afe) +{ + int i; + struct mtk_base_afe_platform *platform = &mtk_afe_platform; + + /* mtk afe already init done */ + if (afe->ref_count > 0) { + afe->ref_count++; + return 0; + } + + afe->platform_priv = platform; + afe->base = platform->base_addr; + afe->memif_32bit_supported = platform->memif_32bit_supported; + afe->memif_dl_num = platform->memif_dl_num; + + afe->base_end_offset = platform->base_end_offset; + afe->adsp2afe_addr = platform->adsp2afe_addr; + afe->afe2adsp_addr = platform->afe2adsp_addr; + afe->afe_fs = platform->afe_fs; /* must be */ + afe->irq_fs = platform->irq_fs; + if (!afe->afe_fs) + return -EINVAL; + tr_dbg(&afedrv_tr, "afe_base:0x%x\n", afe->base); + /* TODO how to get the memif number, how to sync with dmac lib */ + afe->memifs_size = platform->memif_size; + afe->memif = rzalloc(SOF_MEM_ZONE_RUNTIME_SHARED, 0, SOF_MEM_CAPS_RAM, + sizeof(struct mtk_base_afe_memif) * afe->memifs_size); + if (!afe->memif) + return -ENOMEM; + + for (i = 0; i < afe->memifs_size; i++) + afe->memif[i].data = &platform->memif_datas[i]; + + /* TODO how to get the dai number, how to sync with dai lib*/ + afe->dais_size = platform->dais_size; + afe->dais = rzalloc(SOF_MEM_ZONE_RUNTIME_SHARED, 0, SOF_MEM_CAPS_RAM, + sizeof(struct mtk_base_afe_dai) * afe->dais_size); + if (!afe->dais) + goto err_alloc_memif; + + /* TODO how to get the irq number */ + afe->irqs_size = platform->irqs_size; + afe->irqs = rzalloc(SOF_MEM_ZONE_RUNTIME_SHARED, 0, SOF_MEM_CAPS_RAM, + sizeof(struct mtk_base_afe_irq) * afe->irqs_size); + if (!afe->irqs) + goto err_alloc_dais; + + for (i = 0; i < afe->irqs_size; i++) + afe->irqs[i].irq_data = &platform->irq_datas[i]; + + afe->ref_count++; + + return 0; +err_alloc_dais: + rfree(afe->dais); +err_alloc_memif: + rfree(afe->memif); + + return -ENOMEM; +} + +int afe_remove(struct mtk_base_afe *afe) +{ + afe->ref_count--; + + if (afe->ref_count > 0) + return 0; + + if (afe->ref_count < 0) { + afe->ref_count = 0; + tr_dbg(&afedrv_tr, "afe ref_count < 0, :%d\n", afe->ref_count); + return 0; + } + + rfree(afe->memif); + afe->memif = NULL; + + rfree(afe->dais); + afe->dais = NULL; + + rfree(afe->irqs); + afe->irqs = NULL; + + return 0; +} diff --git a/src/drivers/mediatek/mt8195/afe-memif.c b/src/drivers/mediatek/mt8195/afe-memif.c new file mode 100644 index 000000000000..feaf80563bed --- /dev/null +++ b/src/drivers/mediatek/mt8195/afe-memif.c @@ -0,0 +1,732 @@ +// SPDX-License-Identifier: BSD-3-Clause +// +// Copyright(c) 2021 Mediatek +// +// Author: Bo Pan +// YC Hung + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* df5e94d7-fd93-42e9-bb94-ab40becc7151 */ +DECLARE_SOF_UUID("memif", memif_uuid, 0xdf5e94d7, 0xfd93, 0x42e9, + 0xbb, 0x94, 0xab, 0x40, 0xbe, 0xcc, 0x71, 0x51); + +DECLARE_TR_CTX(memif_tr, SOF_UUID(memif_uuid), LOG_LEVEL_INFO); + +/* + * Note: TEST_SGEN for test only + * Define this TEST_SGEN to enable sine tone generator + * then output data to audio memory interface(memif), + * you can set TEST_SGEN_ID to choose output to which memif. + * e.g. set TEST_SGEN as '1' and TEST_SGEN_ID as "MT8195_MEMIF_DL2", + * the data source of DL2 will from sine generator. + */ + +#define TEST_SGEN (0) +#if TEST_SGEN +#include +#include +#define TEST_SGEN_ID MT8195_MEMIF_DL2 +#define AUDIO_TML_PD_MASK 1 +#define AUDIO_TML_PD_SHIFT 27 + +#define AFE_SGEN_FREQ_DIV_CH1_MASK 0x1f +#define AFE_SGEN_FREQ_DIV_CH1_SHIFT 0 +#define AFE_SGEN_FREQ_DIV_CH2_MASK 0x1f +#define AFE_SGEN_FREQ_DIV_CH2_SHIFT 12 +#define AFE_SGEN_AMP_DIV_CH1_MASK 0x7 +#define AFE_SGEN_AMP_DIV_CH1_SHIFT 5 +#define AFE_SGEN_AMP_DIV_CH2_MASK 0x7 +#define AFE_SGEN_AMP_DIV_CH2_SHIFT 17 +#define AFE_SGEN_MUTE_CH1_MASK 0x1 +#define AFE_SGEN_MUTE_CH1_SHIFT 24 +#define AFE_SGEN_MUTE_CH2_MASK 0x1 +#define AFE_SGEN_MUTE_CH2_SHIFT 25 +#define AFE_SGEN_ENABLE_MASK 0x1 +#define AFE_SGEN_ENABLE_SHIFT 26 + +#define AFE_SINEGEN_CON1_TIMING_CH1_MASK 0x1f +#define AFE_SINEGEN_CON1_TIMING_CH1_SHIFT 16 +#define AFE_SINEGEN_CON1_TIMING_CH2_MASK 0x1f +#define AFE_SINEGEN_CON1_TIMING_CH2_SHIFT 21 + +#define AFE_SINEGEN_LB_MODE_MSK 0xff +#define AFE_SINEGEN_LB_MODE_SHIFT 24 + +enum { + MT8195_SGEN_UL5 = 0x18, + MT8195_SGEN_UL4 = 0x1f, + MT8195_SGEN_DL3 = 0x47, + MT8195_SGEN_DL2 = 0x60, +}; + +/*sgen freq div*/ +enum { + SGEN_FREQ_64D1 = 1, + SGEN_FREQ_64D2 = 2, + SGEN_FREQ_64D3 = 3, + SGEN_FREQ_64D4 = 4, + SGEN_FREQ_64D5 = 5, + SGEN_FREQ_64D6 = 6, + SGEN_FREQ_64D7 = 7, + SGEN_FREQ_64D8 = 8, +}; + +/*sgen amp div*/ +enum { + SGEN_AMP_D1 = 0, + SGEN_AMP_D2 = 1, + SGEN_AMP_D4 = 2, + SGEN_AMP_D8 = 3, + SGEN_AMP_D16 = 4, + SGEN_AMP_D32 = 5, + SGEN_AMP_D64 = 6, + SGEN_AMP_D128 = 7, +}; + +enum { + SGEN_CH_TIMING_8K = 0, + SGEN_CH_TIMING_12K = 1, + SGEN_CH_TIMING_16K = 2, + SGEN_CH_TIMING_24K = 3, + SGEN_CH_TIMING_32K = 4, + SGEN_CH_TIMING_48K = 5, + SGEN_CH_TIMING_96K = 6, + SGEN_CH_TIMING_192K = 7, + SGEN_CH_TIMING_384K = 8, + SGEN_CH_TIMING_7P35K = 16, + SGEN_CH_TIMING_11P025K = 17, + SGEN_CH_TIMING_14P7K = 18, + SGEN_CH_TIMING_22P05K = 19, + SGEN_CH_TIMING_29P4K = 20, + SGEN_CH_TIMING_44P1K = 21, + SGEN_CH_TIMING_88P2K = 22, + SGEN_CH_TIMING_176P4K = 23, + SGEN_CH_TIMING_352P8K = 24, +}; +#endif + +struct afe_memif_dma { + int direction; /* 1 downlink, 0 uplink */ + + int memif_id; + int dai_id; + int irq_id; + struct mtk_base_afe *afe; + + uint32_t dma_base; + uint32_t dma_size; + uint32_t rptr; + uint32_t wptr; + + uint32_t period_size; + + unsigned int channel; + unsigned int rate; + unsigned int format; +}; + +/* acquire the specific DMA channel */ +static struct dma_chan_data *memif_channel_get(struct dma *dma, unsigned int req_chan) +{ + uint32_t flags; + struct dma_chan_data *channel; + + tr_dbg(&memif_tr, "MEMIF: channel_get(%d)", req_chan); + + spin_lock_irq(&dma->lock, flags); + if (req_chan >= dma->plat_data.channels) { + spin_unlock_irq(&dma->lock, flags); + tr_err(&memif_tr, "MEMIF: Channel %d out of range", req_chan); + return NULL; + } + + channel = &dma->chan[req_chan]; + if (channel->status != COMP_STATE_INIT) { + spin_unlock_irq(&dma->lock, flags); + tr_err(&memif_tr, "MEMIF: Cannot reuse channel %d", req_chan); + return NULL; + } + + atomic_add(&dma->num_channels_busy, 1); + channel->status = COMP_STATE_READY; + spin_unlock_irq(&dma->lock, flags); + + return channel; +} + +/* channel must not be running when this is called */ +static void memif_channel_put(struct dma_chan_data *channel) +{ + uint32_t flags; + + /* Assuming channel is stopped, we thus don't need hardware to + * do anything right now + */ + tr_info(&memif_tr, "MEMIF: channel_put(%d)", channel->index); + + notifier_unregister_all(NULL, channel); + + spin_lock_irq(&channel->dma->lock, flags); + channel->status = COMP_STATE_INIT; + atomic_sub(&channel->dma->num_channels_busy, 1); + spin_unlock_irq(&channel->dma->lock, flags); +} + +#if TEST_SGEN +static uint32_t mt8195_sinegen_timing(uint32_t rate) +{ + uint32_t sinegen_timing; + + switch (rate) { + case 8000: + sinegen_timing = SGEN_CH_TIMING_8K; + break; + case 12000: + sinegen_timing = SGEN_CH_TIMING_12K; + break; + case 16000: + sinegen_timing = SGEN_CH_TIMING_16K; + break; + case 24000: + sinegen_timing = SGEN_CH_TIMING_24K; + break; + case 32000: + sinegen_timing = SGEN_CH_TIMING_32K; + break; + case 48000: + sinegen_timing = SGEN_CH_TIMING_48K; + break; + case 96000: + sinegen_timing = SGEN_CH_TIMING_96K; + break; + case 192000: + sinegen_timing = SGEN_CH_TIMING_192K; + break; + case 384000: + sinegen_timing = SGEN_CH_TIMING_384K; + break; + case 7350: + sinegen_timing = SGEN_CH_TIMING_7P35K; + break; + case 11025: + sinegen_timing = SGEN_CH_TIMING_11P025K; + break; + case 14700: + sinegen_timing = SGEN_CH_TIMING_14P7K; + break; + case 22050: + sinegen_timing = SGEN_CH_TIMING_22P05K; + break; + case 29400: + sinegen_timing = SGEN_CH_TIMING_29P4K; + break; + case 44100: + sinegen_timing = SGEN_CH_TIMING_44P1K; + break; + case 88200: + sinegen_timing = SGEN_CH_TIMING_88P2K; + break; + case 176400: + sinegen_timing = SGEN_CH_TIMING_176P4K; + break; + case 352800: + sinegen_timing = SGEN_CH_TIMING_352P8K; + break; + default: + sinegen_timing = SGEN_CH_TIMING_48K; + tr_err(&memif_tr, "invalid rate %d, set default 48k ", rate); + } + tr_dbg(&memif_tr, "rate %d, sinegen_timing %d ", rate, sinegen_timing); + return sinegen_timing; +} + +static void mtk_afe_reg_update_bits(uint32_t addr_offset, uint32_t mask, uint32_t val, int shift) +{ + io_reg_update_bits(AFE_BASE_ADDR + addr_offset, mask << shift, val << shift); +} + +static uint32_t mtk_afe_reg_read(uint32_t addr_offset) +{ + return io_reg_read(AFE_BASE_ADDR + addr_offset); +} + +static void mt8195_afe_sinegen_enable(uint32_t sgen_id, uint32_t rate, int enable) +{ + uint32_t loopback_mode, reg_1, reg_2, sinegen_timing; + + tr_dbg(&memif_tr, "sgen_id %d, enable %d", sgen_id, enable); + + sinegen_timing = mt8195_sinegen_timing(rate); + + if (enable == 1) { + /* set loopback mode */ + switch (sgen_id) { + case MT8195_MEMIF_UL4: + loopback_mode = MT8195_SGEN_UL4; + break; + case MT8195_MEMIF_UL5: + loopback_mode = MT8195_SGEN_UL5; + break; + case MT8195_MEMIF_DL2: + loopback_mode = MT8195_SGEN_DL2; + break; + case MT8195_MEMIF_DL3: + loopback_mode = MT8195_SGEN_DL3; + break; + default: + tr_err(ctx, fmt, ...)(&memif_tr, "invalid sgen_id", sgen_id); + return; + } + /* enable sinegen clock*/ + mtk_afe_reg_update_bits(AUDIO_TOP_CON0, AUDIO_TML_PD_MASK, 0, AUDIO_TML_PD_SHIFT); + + /*loopback source*/ + mtk_afe_reg_update_bits(AFE_SINEGEN_CON2, AFE_SINEGEN_LB_MODE_MSK, loopback_mode, + AFE_SINEGEN_LB_MODE_SHIFT); + + /* sine gen timing*/ + mtk_afe_reg_update_bits(AFE_SINEGEN_CON1, AFE_SINEGEN_CON1_TIMING_CH1_MASK, + sinegen_timing, AFE_SINEGEN_CON1_TIMING_CH1_SHIFT); + mtk_afe_reg_update_bits(AFE_SINEGEN_CON1, AFE_SINEGEN_CON1_TIMING_CH2_MASK, + sinegen_timing, AFE_SINEGEN_CON1_TIMING_CH2_SHIFT); + + /*freq div*/ + mtk_afe_reg_update_bits(AFE_SINEGEN_CON0, AFE_SGEN_FREQ_DIV_CH1_MASK, + SGEN_FREQ_64D1, AFE_SGEN_FREQ_DIV_CH1_SHIFT); + mtk_afe_reg_update_bits(AFE_SINEGEN_CON0, AFE_SGEN_FREQ_DIV_CH2_MASK, + SGEN_FREQ_64D2, AFE_SGEN_FREQ_DIV_CH2_SHIFT); + + /*amp div*/ + mtk_afe_reg_update_bits(AFE_SINEGEN_CON0, AFE_SGEN_AMP_DIV_CH1_MASK, SGEN_AMP_D2, + AFE_SGEN_AMP_DIV_CH1_SHIFT); + mtk_afe_reg_update_bits(AFE_SINEGEN_CON0, AFE_SGEN_AMP_DIV_CH2_MASK, SGEN_AMP_D2, + AFE_SGEN_AMP_DIV_CH2_SHIFT); + /* enable sgen*/ + mtk_afe_reg_update_bits(AFE_SINEGEN_CON0, AFE_SGEN_ENABLE_MASK, 1, + AFE_SGEN_ENABLE_SHIFT); + } else { + /* disable sgen*/ + mtk_afe_reg_update_bits(AFE_SINEGEN_CON0, AFE_SGEN_ENABLE_MASK, 0, + AFE_SGEN_ENABLE_SHIFT); + + /* disable sgen clock */ + mtk_afe_reg_update_bits(AUDIO_TOP_CON0, AUDIO_TML_PD_MASK, 1, AUDIO_TML_PD_SHIFT); + } + + reg_1 = mtk_afe_reg_read(AFE_SINEGEN_CON0); + reg_2 = mtk_afe_reg_read(AFE_SINEGEN_CON2); + tr_dbg(&memif_tr, "AFE_SINEGEN_CON0 0x%x, AFE_SINEGEN_CON2 0x%x", reg_1, reg_2); +} +#endif +static int memif_start(struct dma_chan_data *channel) +{ + struct afe_memif_dma *memif = dma_chan_get_data(channel); + + tr_info(&memif_tr, "MEMIF:%d start(%d), channel_status:%d", memif->memif_id, channel->index, + channel->status); + + if (channel->status != COMP_STATE_PREPARE && channel->status != COMP_STATE_SUSPEND) + return -EINVAL; + + channel->status = COMP_STATE_ACTIVE; +#if TEST_SGEN + mt8195_afe_sinegen_enable(TEST_SGEN_ID, 48000, 1); +#endif + /* Do the HW start of the DMA */ + afe_memif_set_enable(memif->afe, memif->memif_id, 1); + + return 0; +} + +static int memif_release(struct dma_chan_data *channel) +{ + struct afe_memif_dma *memif = dma_chan_get_data(channel); + + /* TODO actually handle pause/release properly? */ + tr_info(&memif_tr, "MEMIF: release(%d)", channel->index); + + if (channel->status != COMP_STATE_PAUSED) + return -EINVAL; + + channel->status = COMP_STATE_ACTIVE; + afe_memif_set_enable(memif->afe, memif->memif_id, 0); +#if TEST_SGEN + mt8195_afe_sinegen_enable(TEST_SGEN_ID, 48000, 0); +#endif + + return 0; +} + +static int memif_pause(struct dma_chan_data *channel) +{ + struct afe_memif_dma *memif = dma_chan_get_data(channel); + + /* TODO actually handle pause/release properly? */ + tr_info(&memif_tr, "MEMIF: pause(%d)", channel->index); + + if (channel->status != COMP_STATE_ACTIVE) + return -EINVAL; + + channel->status = COMP_STATE_PAUSED; + + /* Disable HW requests */ + afe_memif_set_enable(memif->afe, memif->memif_id, 0); + + return 0; +} + +static int memif_stop(struct dma_chan_data *channel) +{ + struct afe_memif_dma *memif = dma_chan_get_data(channel); + + tr_info(&memif_tr, "MEMIF: stop(%d)", channel->index); + /* Validate state */ + /* TODO: Should we? */ + switch (channel->status) { + case COMP_STATE_READY: + case COMP_STATE_PREPARE: + return 0; /* do not try to stop multiple times */ + case COMP_STATE_PAUSED: + case COMP_STATE_ACTIVE: + break; + default: + return -EINVAL; + } + channel->status = COMP_STATE_READY; + /* Disable channel */ + afe_memif_set_enable(memif->afe, memif->memif_id, 0); + return 0; +} + +static int memif_copy(struct dma_chan_data *channel, int bytes, uint32_t flags) +{ + struct afe_memif_dma *memif = dma_chan_get_data(channel); + struct dma_cb_data next = { + .channel = channel, + .elem.size = bytes, + }; + + /* TODO XRUN check, update hw ptr */ + /* TODO TBD Playback first data check */ + + /* update user hwptr */ + if (memif->direction) + memif->wptr = (memif->wptr + bytes) % memif->dma_size; + else + memif->rptr = (memif->rptr + bytes) % memif->dma_size; + tr_dbg(&memif_tr, "memif_copy: wptr:%u, rptr:%u", memif->wptr, memif->rptr); + + notifier_event(channel, NOTIFIER_ID_DMA_COPY, NOTIFIER_TARGET_CORE_LOCAL, &next, + sizeof(next)); + + return 0; +} + +static int memif_status(struct dma_chan_data *channel, struct dma_chan_status *status, + uint8_t direction) +{ + struct afe_memif_dma *memif = dma_chan_get_data(channel); + unsigned int hw_ptr; + + status->state = channel->status; + status->flags = 0; + + /* update current hw point */ + hw_ptr = afe_memif_get_cur_position(memif->afe, memif->memif_id); + hw_ptr -= memif->dma_base; + if (memif->direction) + memif->rptr = hw_ptr; + else + memif->wptr = hw_ptr; + + status->r_pos = memif->rptr + memif->dma_base; + status->w_pos = memif->wptr + memif->dma_base; + status->timestamp = timer_get_system(timer_get()); + return 0; +} + +/* set the DMA channel configuration, source/target address, buffer sizes */ +static int memif_set_config(struct dma_chan_data *channel, struct dma_sg_config *config) +{ + struct afe_memif_dma *memif = dma_chan_get_data(channel); + int ret; + int dai_id; + int irq_id; + unsigned int dma_addr; + int dma_size = 0; + int direction; + int i; + + channel->is_scheduling_source = config->is_scheduling_source; + channel->direction = config->direction; + + direction = afe_memif_get_direction(memif->afe, memif->memif_id); + tr_info(&memif_tr, "memif_set_config, direction:%d, afe_dir:%d", config->direction, + direction); + + switch (config->direction) { + case DMA_DIR_MEM_TO_DEV: + if (direction != MEM_DIR_PLAYBACK) { + ret = -EINVAL; + break; + } + dai_id = (int)AFE_HS_GET_DAI(config->dest_dev); + irq_id = (int)AFE_HS_GET_IRQ(config->dest_dev); + dma_addr = (int)config->elem_array.elems[0].src; + break; + case DMA_DIR_DEV_TO_MEM: + if (direction != MEM_DIR_CAPTURE) { + ret = -EINVAL; + break; + } + dai_id = (int)AFE_HS_GET_DAI(config->src_dev); + irq_id = (int)AFE_HS_GET_IRQ(config->src_dev); + dma_addr = (int)config->elem_array.elems[0].dest; + tr_dbg(&memif_tr, "capture: dai_id:%d, dma_addr:%u\n", dai_id, dma_addr); + break; + default: + tr_err(&memif_tr, "afe_memif_set_config() unsupported config direction"); + return -EINVAL; + } + + for (i = 0; i < config->elem_array.count; i++) + dma_size += (int)config->elem_array.elems[i].size; + + if (!config->cyclic) { + tr_err(&memif_tr, "afe-memif: Only cyclic configurations are supported!"); + return -EINVAL; + } + if (config->scatter) { + tr_err(&memif_tr, "afe-memif: scatter enabled, that is not supported for now!"); + return -EINVAL; + } + + memif->dai_id = dai_id; + memif->irq_id = irq_id; + memif->dma_base = dma_addr; + memif->dma_size = dma_size; + memif->direction = direction; + /* TODO risk, it may has sync problems with DAI comp */ + memif->rptr = 0; + memif->wptr = 0; + memif->period_size = config->elem_array.elems[0].size; + + /* get dai's config setting from afe driver */ + afe_dai_get_config(memif->afe, dai_id, &memif->channel, &memif->rate, &memif->format); + /* set the afe memif parameters */ + afe_memif_set_params(memif->afe, memif->memif_id, memif->channel, memif->rate, + memif->format); + afe_memif_set_addr(memif->afe, memif->memif_id, memif->dma_base, memif->dma_size); + channel->status = COMP_STATE_PREPARE; + + return 0; +} + +/* restore DMA context after leaving D3 */ +static int memif_pm_context_restore(struct dma *dma) +{ + /* External to the DSP, won't lose power */ + return 0; +} + +/* store DMA context after leaving D3 */ +static int memif_pm_context_store(struct dma *dma) +{ + /* External to the DSP, won't lose power */ + return 0; +} + +static int memif_probe(struct dma *dma) +{ + int channel; + int ret; + struct mtk_base_afe *afe = afe_get(); + struct afe_memif_dma *memif; + + if (!dma || dma->chan) { + tr_err(&memif_tr, "MEMIF: Repeated probe"); + return -EEXIST; + } + + /* do afe driver probe */ + ret = afe_probe(afe); + if (ret < 0) { + tr_err(&memif_tr, "MEMIF: afe_probe fail:%d", ret); + return ret; + } + + dma->chan = rzalloc(SOF_MEM_ZONE_RUNTIME, 0, SOF_MEM_CAPS_RAM, + dma->plat_data.channels * sizeof(struct dma_chan_data)); + if (!dma->chan) { + tr_err(&memif_tr, "MEMIF: Probe failure, unable to allocate channel descriptors"); + return -ENOMEM; + } + + for (channel = 0; channel < dma->plat_data.channels; channel++) { + dma->chan[channel].dma = dma; + /* TODO need divide to UL and DL for different index */ + dma->chan[channel].index = channel; + + memif = rzalloc(SOF_MEM_ZONE_SYS_RUNTIME, 0, SOF_MEM_CAPS_RAM, + sizeof(struct afe_memif_dma)); + if (!memif) { + tr_err(&memif_tr, "afe-memif: %d channel %d private data alloc failed", + dma->plat_data.id, channel); + goto out; + } + + memif->afe = afe; + memif->memif_id = channel; + dma_chan_set_data(&dma->chan[channel], memif); + } + return 0; + +out: + if (dma->chan) { + for (channel = 0; channel < dma->plat_data.channels; channel++) + rfree(dma_chan_get_data(&dma->chan[channel])); + rfree(dma->chan); + dma->chan = NULL; + } + + afe_remove(afe); + + return -ENOMEM; +} + +static int memif_remove(struct dma *dma) +{ + int channel; + struct mtk_base_afe *afe = afe_get(); + + if (!dma->chan) { + tr_err(&memif_tr, "MEMIF: remove called without probe, it's a no-op"); + return 0; + } + for (channel = 0; channel < dma->plat_data.channels; channel++) { + /* TODO Disable HW requests for this channel */ + + rfree(dma_chan_get_data(&dma->chan[channel])); + } + rfree(dma->chan); + dma->chan = NULL; + + afe_remove(afe); + + return 0; +} + +static int memif_interrupt(struct dma_chan_data *channel, enum dma_irq_cmd cmd) +{ + struct mtk_base_afe *afe = afe_get(); + struct afe_memif_dma *memif = dma_chan_get_data(channel); + unsigned int sample_size = + ((memif->format == SOF_IPC_FRAME_S16_LE) ? 2 : 4) * memif->channel; + unsigned int period = memif->period_size / sample_size; + + if (channel->status == COMP_STATE_INIT) + return 0; + + switch (cmd) { + case DMA_IRQ_STATUS_GET: + return afe_irq_get_status(afe, memif->irq_id); + case DMA_IRQ_CLEAR: + afe_irq_clear(afe, memif->irq_id); + return 0; + case DMA_IRQ_MASK: + afe_irq_disable(afe, memif->irq_id); + case DMA_IRQ_UNMASK: + afe_irq_config(afe, memif->irq_id, memif->rate, period); + afe_irq_enable(afe, memif->irq_id); + return 0; + default: + return -EINVAL; + } + + return 0; +} + +/* TODO need convert number to platform MACRO */ +static int memif_get_attribute(struct dma *dma, uint32_t type, uint32_t *value) +{ + switch (type) { + case DMA_ATTR_BUFFER_ALIGNMENT: + case DMA_ATTR_COPY_ALIGNMENT: + *value = 4; + break; + case DMA_ATTR_BUFFER_ADDRESS_ALIGNMENT: + *value = 16; + break; + case DMA_ATTR_BUFFER_PERIOD_COUNT: + *value = 4; + break; + default: + return -ENOENT; + } + return 0; +} + +static int memif_get_data_size(struct dma_chan_data *channel, uint32_t *avail, uint32_t *free) +{ + struct afe_memif_dma *memif = dma_chan_get_data(channel); + uint32_t hw_ptr; + + /* update hw pointer from afe memif */ + hw_ptr = afe_memif_get_cur_position(memif->afe, memif->memif_id); + tr_dbg(&memif_tr, "get_pos:0x%x, base:0x%x, dir:%d", hw_ptr, memif->dma_base, + memif->direction); + tr_dbg(&memif_tr, "dma_size:%u, period_size:%d", memif->dma_size, memif->period_size); + hw_ptr -= memif->dma_base; + + if (memif->direction) + memif->rptr = hw_ptr; + else + memif->wptr = hw_ptr; + + *avail = (memif->wptr + memif->dma_size - memif->rptr) % memif->dma_size; + /* TODO, check if need alignment the available and free size to 1 period */ + if (memif->direction) + *avail = DIV_ROUND_UP(*avail, memif->period_size) * memif->period_size; + else + *avail = *avail / memif->period_size * memif->period_size; + + *free = memif->dma_size - *avail; + tr_dbg(&memif_tr, "r:0x%x, w:0x%x, avail:%u, free:%u ", memif->wptr, *avail, *free); + + return 0; +} + +const struct dma_ops memif_ops = { + .channel_get = memif_channel_get, + .channel_put = memif_channel_put, + .start = memif_start, + .stop = memif_stop, + .pause = memif_pause, + .release = memif_release, + .copy = memif_copy, + .status = memif_status, + .set_config = memif_set_config, + .pm_context_restore = memif_pm_context_restore, + .pm_context_store = memif_pm_context_store, + .probe = memif_probe, + .remove = memif_remove, + .interrupt = memif_interrupt, + .get_attribute = memif_get_attribute, + .get_data_size = memif_get_data_size, +}; diff --git a/src/include/ipc/dai-mediatek.h b/src/include/ipc/dai-mediatek.h new file mode 100644 index 000000000000..d170e3bcc86f --- /dev/null +++ b/src/include/ipc/dai-mediatek.h @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: BSD-3-Clause +// +// Copyright(c) 2021 Mediatek +// +// Author: Bo Pan + +#ifndef __IPC_DAI_MEDIATEK_H__ +#define __IPC_DAI_MEDIATEK_H__ + +#include +#include + +/* AFE Configuration Request - SOF_DAI_MEDIATEK_AFE */ +struct sof_ipc_dai_afe_params { + uint32_t reserved0; + + uint32_t dai_channels; + uint32_t dai_rate; + uint32_t dai_format; + uint32_t stream_id; + uint32_t reserved[4]; /* reserve for future */ +} __attribute__((packed)); + +#endif /* __IPC_DAI_MEDIATEK_H__ */ + diff --git a/src/include/ipc/dai.h b/src/include/ipc/dai.h index 94937bf2b9ba..230446f2285d 100644 --- a/src/include/ipc/dai.h +++ b/src/include/ipc/dai.h @@ -18,6 +18,7 @@ #include #include +#include #include #include @@ -70,7 +71,8 @@ enum sof_ipc_dai_type { SOF_DAI_IMX_ESAI, /**< i.MX ESAI */ SOF_DAI_AMD_BT, /**< Amd BT */ SOF_DAI_AMD_SP, /**< Amd SP */ - SOF_DAI_AMD_DMIC /**< Amd DMIC */ + SOF_DAI_AMD_DMIC, /**< Amd DMIC */ + SOF_DAI_MEDIATEK_AFE /**< Mtk AFE */ }; /* general purpose DAI configuration */ @@ -95,6 +97,7 @@ struct sof_ipc_dai_config { struct sof_ipc_dai_alh_params alh; struct sof_ipc_dai_esai_params esai; struct sof_ipc_dai_sai_params sai; + struct sof_ipc_dai_afe_params afe; }; } __attribute__((packed, aligned(4))); diff --git a/src/include/sof/drivers/afe-dai.h b/src/include/sof/drivers/afe-dai.h new file mode 100644 index 000000000000..c87b8958b9d1 --- /dev/null +++ b/src/include/sof/drivers/afe-dai.h @@ -0,0 +1,29 @@ +// SPDX-License-Identifier: BSD-3-Clause +// +// Copyright(c) 2021 Mediatek +// +// Author: Bo Pan +// YC Hung + +#ifndef __SOF_DRIVERS_AFE_DAI_H__ +#define __SOF_DRIVERS_AFE_DAI_H__ + +#include +#include +#include +#include +#include +#include + +#define AFE_HS_GET_DAI(hs) (((hs) & MASK(7, 0)) >> 0) +#define AFE_HS_SET_DAI(dai) SET_BITS(7, 0, dai) +#define AFE_HS_GET_IRQ(hs) (((hs) & MASK(15, 8)) >> 8) +#define AFE_HS_SET_IRQ(irq) SET_BITS(15, 8, irq) +#define AFE_HS_GET_CHAN(hs) (((hs) & MASK(23, 16)) >> 16) +#define AFE_HS_SET_CHAN(chan) SET_BITS(23, 16, chan) +#define AFE_HANDSHAKE(dai, irq, channel)\ + (AFE_HS_SET_DAI(dai) | AFE_HS_SET_CHAN(channel) | AFE_HS_SET_IRQ(irq)) + +extern const struct dai_driver afe_dai_driver; +#endif /* __SOF_DRIVERS_AFE_MEMIF_H__ */ + diff --git a/src/include/sof/drivers/afe-drv.h b/src/include/sof/drivers/afe-drv.h new file mode 100644 index 000000000000..f0825a3634ae --- /dev/null +++ b/src/include/sof/drivers/afe-drv.h @@ -0,0 +1,169 @@ +// SPDX-License-Identifier: BSD-3-Clause +// +// Copyright(c) 2021 Mediatek +// +// Author: Bo Pan +// YC Hung + +#ifndef __SOF_DRIVERS_AFE_DRV_H__ +#define __SOF_DRIVERS_AFE_DRV_H__ + +struct mtk_base_memif_data { + int id; + const char *name; + int reg_ofs_base; + int reg_ofs_cur; + int reg_ofs_end; + int reg_ofs_base_msb; + int reg_ofs_cur_msb; + int reg_ofs_end_msb; + int fs_reg; + int fs_shift; + int fs_maskbit; + int mono_reg; + int mono_shift; + int mono_invert; + int quad_ch_reg; + int quad_ch_mask; + int quad_ch_shift; + int enable_reg; + int enable_shift; + int hd_reg; + int hd_shift; + int hd_align_reg; + int hd_align_mshift; + int msb_reg; + int msb_shift; + int msb2_reg; + int msb2_shift; + int agent_disable_reg; + int agent_disable_shift; + int ch_num_reg; + int ch_num_shift; + int ch_num_maskbit; + /* playback memif only */ + int pbuf_reg; + int pbuf_mask; + int pbuf_shift; + int minlen_reg; + int minlen_mask; + int minlen_shift; +}; + +struct mtk_base_irq_data { + int id; + int irq_cnt_reg; + int irq_cnt_shift; + int irq_cnt_maskbit; + int irq_fs_reg; + int irq_fs_shift; + int irq_fs_maskbit; + int irq_en_reg; + int irq_en_shift; + int irq_clr_reg; + int irq_clr_shift; + int irq_ap_en_reg; + int irq_ap_en_shift; + int irq_scp_en_reg; + int irq_scp_en_shift; +}; + +struct mtk_base_afe_memif { + unsigned int dma_addr; + unsigned int afe_addr; + unsigned int buffer_size; + + const struct mtk_base_memif_data *data; + int irq_usage; +}; + +struct mtk_base_afe_dai { + int id; + unsigned int channel; + unsigned int rate; + unsigned int format; + /* other? */ +}; + +struct mtk_base_afe_irq { + const struct mtk_base_irq_data *irq_data; + int mask; + int irq_occupyed; +}; + +struct mtk_base_afe { + int ref_count; + unsigned int base; + + struct mtk_base_afe_memif *memif; + int memifs_size; + int memif_32bit_supported; + int memif_dl_num; + + struct mtk_base_afe_irq *irqs; + int irqs_size; + + struct mtk_base_afe_dai *dais; + int dais_size; + + unsigned int (*afe2adsp_addr)(unsigned int addr); + unsigned int (*adsp2afe_addr)(unsigned int addr); + unsigned int (*afe_fs)(unsigned int rate, int aud_blk); + unsigned int (*irq_fs)(unsigned int rate); + + int base_end_offset; + + void *platform_priv; +}; + +/* platform information */ +struct mtk_base_afe_platform { + unsigned int base_addr; + const struct mtk_base_memif_data *memif_datas; + int memif_size; + int memif_32bit_supported; + int memif_dl_num; + + struct mtk_base_irq_data *irq_datas; + int irqs_size; + int dais_size; + + int base_end_offset; + + /* misc */ + unsigned int (*afe2adsp_addr)(unsigned int addr); + unsigned int (*adsp2afe_addr)(unsigned int addr); + unsigned int (*afe_fs)(unsigned int rate, int aud_blk); + unsigned int (*irq_fs)(unsigned int rate); +}; + +extern struct mtk_base_afe_platform mtk_afe_platform; + +struct mtk_base_afe *afe_get(void); +int afe_probe(struct mtk_base_afe *afe); +int afe_remove(struct mtk_base_afe *afe); + +/* dai operation */ +int afe_dai_get_config(struct mtk_base_afe *afe, int id, unsigned int *channel, unsigned int *rate, + unsigned int *format); +int afe_dai_set_config(struct mtk_base_afe *afe, int id, unsigned int channel, unsigned int rate, + unsigned int format); + +/* memif operation */ +int afe_memif_set_params(struct mtk_base_afe *afe, int id, unsigned int channel, unsigned int rate, + unsigned int format); +int afe_memif_set_addr(struct mtk_base_afe *afe, int id, unsigned int dma_addr, + unsigned int dma_bytes); +int afe_memif_set_enable(struct mtk_base_afe *afe, int id, int enable); +unsigned int afe_memif_get_cur_position(struct mtk_base_afe *afe, int id); +int afe_memif_get_direction(struct mtk_base_afe *afe, int id); + +/* irq opeartion */ +int afe_irq_get_status(struct mtk_base_afe *afe, int id); +int afe_irq_clear(struct mtk_base_afe *afe, int id); +int afe_irq_config(struct mtk_base_afe *afe, int id, unsigned int rate, unsigned int period); +int afe_irq_enable(struct mtk_base_afe *afe, int id); +int afe_irq_disable(struct mtk_base_afe *afe, int id); + +#endif /* __SOF_DRIVERS_AFE_DRV_H__ */ + diff --git a/src/include/sof/drivers/afe-memif.h b/src/include/sof/drivers/afe-memif.h new file mode 100644 index 000000000000..5e7376dc1b82 --- /dev/null +++ b/src/include/sof/drivers/afe-memif.h @@ -0,0 +1,24 @@ +// SPDX-License-Identifier: BSD-3-Clause +// +// Copyright(c) 2021 Mediatek +// +// Author: Bo Pan +// YC Hung + +#ifndef __SOF_DRIVERS_AFE_MEMIF_H__ +#define __SOF_DRIVERS_AFE_MEMIF_H__ + +#include +#include +#include +#include +#include +#include + +enum { + MEM_DIR_CAPTURE = 0, + MEM_DIR_PLAYBACK, +}; + +#endif /* __SOF_DRIVERS_AFE_MEMIF_H__ */ + diff --git a/src/include/sof/lib/dma.h b/src/include/sof/lib/dma.h index 95525c6cbfa4..43726b52441c 100644 --- a/src/include/sof/lib/dma.h +++ b/src/include/sof/lib/dma.h @@ -63,6 +63,7 @@ struct comp_buffer; #define DMA_DEV_ESAI BIT(7) /**< connectable to ESAI fifo */ #define DMA_DEV_BT BIT(8) /**< connectable to ACP BT I2S */ #define DMA_DEV_SP BIT(9) /**< connectable to ACP SP I2S */ +#define DMA_DEV_AFE_MEMIF BIT(10) /**< connectable to AFE fifo */ /* DMA access privilege flag */ #define DMA_ACCESS_EXCLUSIVE 1 diff --git a/src/ipc/ipc3/dai.c b/src/ipc/ipc3/dai.c index 888e84a5cd84..7d1628f742ce 100644 --- a/src/ipc/ipc3/dai.c +++ b/src/ipc/ipc3/dai.c @@ -13,6 +13,7 @@ #include #include #include +#include #include #include #include @@ -69,6 +70,11 @@ int dai_config_dma_channel(struct comp_dev *dev, void *spec_config) channel = dai_get_handshake(dd->dai, dai->direction, dd->stream_id); break; + case SOF_DAI_MEDIATEK_AFE: + handshake = dai_get_handshake(dd->dai, dai->direction, + dd->stream_id); + channel = AFE_HS_GET_CHAN(handshake); + break; default: /* other types of DAIs not handled for now */ comp_err(dev, "dai_config_dma_channel(): Unknown dai type %d", @@ -155,6 +161,8 @@ int ipc_dai_data_config(struct comp_dev *dev) dev->ipc_config.frame_fmt = SOF_IPC_FRAME_S32_LE; dd->dma_buffer->stream.frame_fmt = dev->ipc_config.frame_fmt; break; + case SOF_DAI_MEDIATEK_AFE: + break; default: /* other types of DAIs not handled for now */ comp_warn(dev, "dai_data_config(): Unknown dai type %d", From 11ec0cd5c4d1244480eb95bb52e0f69b95ca7d1e Mon Sep 17 00:00:00 2001 From: Allen-KH Cheng Date: Fri, 27 Aug 2021 19:32:32 +0800 Subject: [PATCH 08/15] platform: mt8195: add afe-platform support Add memif data for afe Add common and regs header for afe Add afe platform for mt8195 audio/dsp AFE: the abbreviation for Audio Front End Signed-off-by: YC Hung Signed-off-by: Allen-KH Cheng --- src/platform/mt8195/afe-platform.c | 255 ++ .../include/platform/mt8195-afe-common.h | 68 + .../mt8195/include/platform/mt8195-afe-regs.h | 2789 +++++++++++++++++ 3 files changed, 3112 insertions(+) create mode 100644 src/platform/mt8195/afe-platform.c create mode 100644 src/platform/mt8195/include/platform/mt8195-afe-common.h create mode 100644 src/platform/mt8195/include/platform/mt8195-afe-regs.h diff --git a/src/platform/mt8195/afe-platform.c b/src/platform/mt8195/afe-platform.c new file mode 100644 index 000000000000..38e5b36015de --- /dev/null +++ b/src/platform/mt8195/afe-platform.c @@ -0,0 +1,255 @@ +// SPDX-License-Identifier: BSD-3-Clause +// +// Copyright(c) 2021 Mediatek +// +// Author: YC Hung + +#include +#include +#include +#include +#include + +/* + * AFE: Audio Front-End + * + * frontend (memif): + * memory interface + * UL (uplink for capture) + * DL (downlink for playback) + * backend: + * TDM In + * TMD out + * DMIC + * GASRC + * etc. + * interconn: + * inter-connection, + * connect frontends and backends as DSP path + */ + +static const struct mtk_base_memif_data memif_data[MT8195_MEMIF_NUM] = { + [MT8195_MEMIF_DL2] = { + .name = "DL2", + .id = MT8195_MEMIF_DL2, + .reg_ofs_base = AFE_DL2_BASE, + .reg_ofs_cur = AFE_DL2_CUR, + .reg_ofs_end = AFE_DL2_END, + .fs_reg = AFE_MEMIF_AGENT_FS_CON0, + .fs_shift = 10, + .fs_maskbit = 0x1f, + .mono_reg = -1, + .mono_shift = -1, + .enable_reg = AFE_DAC_CON0, + .enable_shift = 18, + .hd_reg = AFE_DL2_CON0, + .hd_shift = 5, + .agent_disable_reg = AUDIO_TOP_CON5, + .agent_disable_shift = 18, + .ch_num_reg = AFE_DL2_CON0, + .ch_num_shift = 0, + .ch_num_maskbit = 0x1f, + .msb_reg = AFE_NORMAL_BASE_ADR_MSB, + .msb_shift = 18, + .msb2_reg = AFE_NORMAL_END_ADR_MSB, + .msb2_shift = 18, + }, + [MT8195_MEMIF_DL3] = { + .name = "DL3", + .id = MT8195_MEMIF_DL3, + .reg_ofs_base = AFE_DL3_BASE, + .reg_ofs_cur = AFE_DL3_CUR, + .reg_ofs_end = AFE_DL3_END, + .fs_reg = AFE_MEMIF_AGENT_FS_CON0, + .fs_shift = 15, + .fs_maskbit = 0x1f, + .mono_reg = -1, + .mono_shift = -1, + .enable_reg = AFE_DAC_CON0, + .enable_shift = 19, + .hd_reg = AFE_DL3_CON0, + .hd_shift = 5, + .agent_disable_reg = AUDIO_TOP_CON5, + .agent_disable_shift = 19, + .ch_num_reg = AFE_DL3_CON0, + .ch_num_shift = 0, + .ch_num_maskbit = 0x1f, + .msb_reg = AFE_NORMAL_BASE_ADR_MSB, + .msb_shift = 19, + .msb2_reg = AFE_NORMAL_END_ADR_MSB, + .msb2_shift = 19, + }, + [MT8195_MEMIF_UL4] = { + .name = "UL4", + .id = MT8195_MEMIF_UL4, + .reg_ofs_base = AFE_UL4_BASE, + .reg_ofs_cur = AFE_UL4_CUR, + .reg_ofs_end = AFE_UL4_END, + .fs_reg = AFE_MEMIF_AGENT_FS_CON2, + .fs_shift = 15, + .fs_maskbit = 0x1f, + .mono_reg = AFE_UL4_CON0, + .mono_shift = 1, + .enable_reg = AFE_DAC_CON0, + .enable_shift = 4, + .hd_reg = AFE_UL4_CON0, + .hd_shift = 5, + .agent_disable_reg = AUDIO_TOP_CON5, + .agent_disable_shift = 3, + .ch_num_reg = -1, + .ch_num_shift = 0, + .ch_num_maskbit = 0, + .msb_reg = AFE_NORMAL_BASE_ADR_MSB, + .msb_shift = 3, + .msb2_reg = AFE_NORMAL_END_ADR_MSB, + .msb2_shift = 3, + }, + [MT8195_MEMIF_UL5] = { + .name = "UL5", + .id = MT8195_MEMIF_UL5, + .reg_ofs_base = AFE_UL5_BASE, + .reg_ofs_cur = AFE_UL5_CUR, + .reg_ofs_end = AFE_UL5_END, + .fs_reg = AFE_MEMIF_AGENT_FS_CON2, + .fs_shift = 20, + .fs_maskbit = 0x1f, + .mono_reg = AFE_UL5_CON0, + .mono_shift = 1, + .enable_reg = AFE_DAC_CON0, + .enable_shift = 5, + .hd_reg = AFE_UL5_CON0, + .hd_shift = 5, + .agent_disable_reg = AUDIO_TOP_CON5, + .agent_disable_shift = 4, + .ch_num_reg = -1, + .ch_num_shift = 0, + .ch_num_maskbit = 0, + .msb_reg = AFE_NORMAL_BASE_ADR_MSB, + .msb_shift = 4, + .msb2_reg = AFE_NORMAL_END_ADR_MSB, + .msb2_shift = 4, + } +}; + +struct mt8195_afe_rate { + unsigned int rate; + unsigned int reg_value; +}; + +static const struct mt8195_afe_rate mt8195_afe_rates[] = { + { + .rate = 8000, + .reg_value = 0, + }, + { + .rate = 12000, + .reg_value = 1, + }, + { + .rate = 16000, + .reg_value = 2, + }, + { + .rate = 24000, + .reg_value = 3, + }, + { + .rate = 32000, + .reg_value = 4, + }, + { + .rate = 48000, + .reg_value = 5, + }, + { + .rate = 96000, + .reg_value = 6, + }, + { + .rate = 192000, + .reg_value = 7, + }, + { + .rate = 384000, + .reg_value = 8, + }, + { + .rate = 7350, + .reg_value = 16, + }, + { + .rate = 11025, + .reg_value = 17, + }, + { + .rate = 14700, + .reg_value = 18, + }, + { + .rate = 22050, + .reg_value = 19, + }, + { + .rate = 29400, + .reg_value = 20, + }, + { + .rate = 44100, + .reg_value = 21, + }, + { + .rate = 88200, + .reg_value = 22, + }, + { + .rate = 176400, + .reg_value = 23, + }, + { + .rate = 352800, + .reg_value = 24, + }, +}; + +static unsigned int mt8195_afe_fs_timing(unsigned int rate) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(mt8195_afe_rates); i++) + if (mt8195_afe_rates[i].rate == rate) + return mt8195_afe_rates[i].reg_value; + + return -EINVAL; +} + +static unsigned int mt8195_afe_fs(unsigned int rate, int aud_blk) +{ + return mt8195_afe_fs_timing(rate); +} + +static unsigned int mt8195_afe2adsp_addr(unsigned int addr) +{ + /*TODO : Need apply the address remap */ + return addr; +} + +static unsigned int mt8195_adsp2afe_addr(unsigned int addr) +{ + /* TODO : Need apply the address remap */ + return addr; +} + +struct mtk_base_afe_platform mtk_afe_platform = { + .base_addr = AFE_BASE_ADDR, + .memif_datas = memif_data, + .memif_size = MT8195_MEMIF_NUM, + .memif_dl_num = MT8195_MEMIF_DL_NUM, + .memif_32bit_supported = 0, + .irq_datas = NULL, + .irqs_size = 0, + .dais_size = MT8195_DAI_NUM, + .afe2adsp_addr = mt8195_afe2adsp_addr, + .adsp2afe_addr = mt8195_adsp2afe_addr, + .afe_fs = mt8195_afe_fs, + .irq_fs = mt8195_afe_fs_timing, +}; diff --git a/src/platform/mt8195/include/platform/mt8195-afe-common.h b/src/platform/mt8195/include/platform/mt8195-afe-common.h new file mode 100644 index 000000000000..4a85301b0e5b --- /dev/null +++ b/src/platform/mt8195/include/platform/mt8195-afe-common.h @@ -0,0 +1,68 @@ +// SPDX-License-Identifier: BSD-3-Clause +// +// Copyright(c) 2021 Mediatek +// +// Author: YC Hung + +#ifndef _MT_8195_AFE_COMMON_H_ +#define _MT_8195_AFE_COMMON_H_ + +/* AFE: the abbreviation for Audio Front End */ + +enum { + MT8195_MEMIF_START, + MT8195_MEMIF_DL_START = MT8195_MEMIF_START, + MT8195_MEMIF_DL2 = MT8195_MEMIF_DL_START, + MT8195_MEMIF_DL3, + MT8195_MEMIF_DL_END, + MT8195_MEMIF_UL_START = MT8195_MEMIF_DL_END, + MT8195_MEMIF_UL4 = MT8195_MEMIF_UL_START, + MT8195_MEMIF_UL5, + MT8195_MEMIF_UL_END, + MT8195_MEMIF_END = MT8195_MEMIF_UL_END, + MT8195_MEMIF_DL_NUM = (MT8195_MEMIF_DL_END - MT8195_MEMIF_DL_START), + MT8195_MEMIF_UL_NUM = (MT8195_MEMIF_UL_END - MT8195_MEMIF_UL_START), + MT8195_MEMIF_NUM = (MT8195_MEMIF_END - MT8195_MEMIF_START), +}; + +enum { + MT8195_IRQ_0, + MT8195_IRQ_1, + MT8195_IRQ_2, + MT8195_IRQ_3, + MT8195_IRQ_4, + MT8195_IRQ_5, + MT8195_IRQ_6, + MT8195_IRQ_7, + MT8195_IRQ_8, + MT8195_IRQ_9, + MT8195_IRQ_10, + MT8195_IRQ_11, + MT8195_IRQ_12, + MT8195_IRQ_13, + MT8195_IRQ_14, + MT8195_IRQ_15, + MT8195_IRQ_16, + MT8195_IRQ_17, + MT8195_IRQ_18, + MT8195_IRQ_19, + MT8195_IRQ_20, + MT8195_IRQ_21, + MT8195_IRQ_22, + MT8195_IRQ_23, + MT8195_IRQ_24, + MT8195_IRQ_25, + MT8195_IRQ_26, + MT8195_IRQ_31, /* used only for TDM */ + MT8195_IRQ_NUM, +}; + +enum { + MT8195_AFE_IO_ETDM2_OUT, + MT8195_AFE_IO_ETDM1_OUT, + MT8195_AFE_IO_UL_SRC1, + MT8195_AFE_IO_ETDM2_IN, + MT8195_DAI_NUM, +}; + +#endif diff --git a/src/platform/mt8195/include/platform/mt8195-afe-regs.h b/src/platform/mt8195/include/platform/mt8195-afe-regs.h new file mode 100644 index 000000000000..6e8f9f6312d9 --- /dev/null +++ b/src/platform/mt8195/include/platform/mt8195-afe-regs.h @@ -0,0 +1,2789 @@ +// SPDX-License-Identifier: BSD-3-Clause +// +// Copyright(c) 2021 Mediatek +// +// Author: YC Hung + +#ifndef _MT8195_REG_H_ +#define _MT8195_REG_H_ + +#define AFE_SRAM_BASE 0x10880000 +#define AFE_SRAM_SIZE 0x10000 +#define AFE_BASE_ADDR 0x10890000 + +#define AUDIO_TOP_CON0 0x0000 +#define AUDIO_TOP_CON1 0x0004 +#define AUDIO_TOP_CON2 0x0008 +#define AUDIO_TOP_CON3 0x000c +#define AUDIO_TOP_CON4 0x0010 +#define AUDIO_TOP_CON5 0x0014 +#define AUDIO_TOP_CON6 0x0018 +#define AFE_MAS_HADDR_MSB 0x0020 +#define PWR1_ASM_CON1 0x0108 +#define ASYS_IRQ_CONFIG 0x0110 +#define ASYS_IRQ1_CON 0x0114 +#define ASYS_IRQ2_CON 0x0118 +#define ASYS_IRQ3_CON 0x011c +#define ASYS_IRQ4_CON 0x0120 +#define ASYS_IRQ5_CON 0x0124 +#define ASYS_IRQ6_CON 0x0128 +#define ASYS_IRQ7_CON 0x012c +#define ASYS_IRQ8_CON 0x0130 +#define ASYS_IRQ9_CON 0x0134 +#define ASYS_IRQ10_CON 0x0138 +#define ASYS_IRQ11_CON 0x013c +#define ASYS_IRQ12_CON 0x0140 +#define ASYS_IRQ13_CON 0x0144 +#define ASYS_IRQ14_CON 0x0148 +#define ASYS_IRQ15_CON 0x014c +#define ASYS_IRQ16_CON 0x0150 +#define ASYS_IRQ_CLR 0x0154 +#define ASYS_IRQ_STATUS 0x0158 +#define ASYS_IRQ_MON1 0x015c +#define ASYS_IRQ_MON2 0x0160 +#define AFE_IRQ1_CON 0x0164 +#define AFE_IRQ2_CON 0x0168 +#define AFE_IRQ3_CON 0x016c +#define AFE_IRQ_MCU_CLR 0x0170 +#define AFE_IRQ_STATUS 0x0174 +#define AFE_IRQ_MASK 0x0178 +#define ASYS_IRQ_MASK 0x017c +#define AFE_IRQ3_CON_MON 0x01b0 +#define AFE_IRQ_MCU_MON2 0x01b4 +#define AFE_IRQ8_CON 0x01b8 +#define AFE_IRQ9_CON 0x01bc +#define AFE_IRQ10_CON 0x01c0 +#define AFE_IRQ9_CON_MON 0x01c4 +#define ADSP_IRQ_MASK 0x01c8 +#define ADSP_IRQ_STATUS 0x01cc +#define AFE_SINEGEN_CON0 0x01f0 +#define AFE_SINEGEN_CON1 0x01f4 +#define AFE_SINEGEN_CON2 0x01f8 +#define AFE_SINEGEN_CON3 0x01fc +#define AFE_SPDIF_OUT_CON0 0x0380 +#define AFE_TDMOUT_CONN0 0x0390 +#define PWR1_ASM_CON2 0x03b0 +#define PWR1_ASM_CON3 0x03b4 +#define PWR1_ASM_CON4 0x03b8 +#define AFE_APLL_TUNER_CFG 0x03f8 +#define AFE_APLL_TUNER_CFG1 0x03fc +#define AUDIO_TOP_STA0 0x0400 +#define AUDIO_TOP_STA1 0x0404 +#define AFE_GAIN1_CON0 0x0410 +#define AFE_GAIN1_CON1 0x0414 +#define AFE_GAIN1_CON2 0x0418 +#define AFE_GAIN1_CON3 0x041c +#define AFE_GAIN1_CUR 0x0424 +#define AFE_GAIN2_CON0 0x0428 +#define AFE_GAIN2_CON1 0x042c +#define AFE_GAIN2_CON2 0x0430 +#define AFE_GAIN2_CON3 0x0434 +#define AFE_GAIN2_CUR 0x043c +#define AFE_IEC_CFG 0x0480 +#define AFE_IEC_NSNUM 0x0484 +#define AFE_IEC_BURST_INFO 0x0488 +#define AFE_IEC_BURST_LEN 0x048c +#define AFE_IEC_NSADR 0x0490 +#define AFE_IEC_CHL_STAT0 0x04a0 +#define AFE_IEC_CHL_STAT1 0x04a4 +#define AFE_IEC_CHR_STAT0 0x04a8 +#define AFE_IEC_CHR_STAT1 0x04ac +#define AFE_SPDIFIN_CFG0 0x0500 +#define AFE_SPDIFIN_CFG1 0x0504 +#define AFE_SPDIFIN_CHSTS1 0x0508 +#define AFE_SPDIFIN_CHSTS2 0x050c +#define AFE_SPDIFIN_CHSTS3 0x0510 +#define AFE_SPDIFIN_CHSTS4 0x0514 +#define AFE_SPDIFIN_CHSTS5 0x0518 +#define AFE_SPDIFIN_CHSTS6 0x051c +#define AFE_SPDIFIN_DEBUG1 0x0520 +#define AFE_SPDIFIN_DEBUG2 0x0524 +#define AFE_SPDIFIN_DEBUG3 0x0528 +#define AFE_SPDIFIN_DEBUG4 0x052c +#define AFE_SPDIFIN_EC 0x0530 +#define AFE_SPDIFIN_CKLOCK_CFG 0x0534 +#define AFE_SPDIFIN_BR 0x053c +#define AFE_SPDIFIN_BR_DBG1 0x0540 +#define AFE_SPDIFIN_CKFBDIV 0x0544 +#define AFE_SPDIFIN_INT_EXT 0x0548 +#define AFE_SPDIFIN_INT_EXT2 0x054c +#define SPDIFIN_FREQ_INFO 0x0550 +#define SPDIFIN_FREQ_INFO_2 0x0554 +#define SPDIFIN_FREQ_INFO_3 0x0558 +#define SPDIFIN_FREQ_STATUS 0x055c +#define SPDIFIN_USERCODE1 0x0560 +#define SPDIFIN_USERCODE2 0x0564 +#define SPDIFIN_USERCODE3 0x0568 +#define SPDIFIN_USERCODE4 0x056c +#define SPDIFIN_USERCODE5 0x0570 +#define SPDIFIN_USERCODE6 0x0574 +#define SPDIFIN_USERCODE7 0x0578 +#define SPDIFIN_USERCODE8 0x057c +#define SPDIFIN_USERCODE9 0x0580 +#define SPDIFIN_USERCODE10 0x0584 +#define SPDIFIN_USERCODE11 0x0588 +#define SPDIFIN_USERCODE12 0x058c +#define AFE_SPDIFIN_APLL_TUNER_CFG 0x0594 +#define AFE_SPDIFIN_APLL_TUNER_CFG1 0x0598 +#define ASYS_TOP_CON 0x0600 +#define AFE_LINEIN_APLL_TUNER_CFG 0x0610 +#define AFE_LINEIN_APLL_TUNER_MON 0x0614 +#define AFE_EARC_APLL_TUNER_CFG 0x0618 +#define AFE_EARC_APLL_TUNER_MON 0x061c +#define PWR2_TOP_CON0 0x0634 +#define PWR2_TOP_CON1 0x0638 +#define PCM_INTF_CON1 0x063c +#define PCM_INTF_CON2 0x0640 +#define AFE_CM0_CON 0x0660 +#define AFE_CM1_CON 0x0664 +#define AFE_CM2_CON 0x0668 +#define AFE_CM0_MON 0x0670 +#define AFE_CM1_MON 0x0674 +#define AFE_CM2_MON 0x0678 +#define AFE_MPHONE_MULTI_CON0 0x06a4 +#define AFE_MPHONE_MULTI_CON1 0x06a8 +#define AFE_MPHONE_MULTI_CON2 0x06ac +#define AFE_MPHONE_MULTI_MON 0x06b0 +#define AFE_MPHONE_MULTI_DET_REG_CON0 0x06b4 +#define AFE_MPHONE_MULTI_DET_REG_CON1 0x06b8 +#define AFE_MPHONE_MULTI_DET_REG_CON2 0x06bc +#define AFE_MPHONE_MULTI_DET_REG_CON3 0x06c0 +#define AFE_MPHONE_MULTI_DET_MON0 0x06c4 +#define AFE_MPHONE_MULTI_DET_MON1 0x06c8 +#define AFE_MPHONE_MULTI_DET_MON2 0x06d0 +#define AFE_MPHONE_MULTI2_CON0 0x06d4 +#define AFE_MPHONE_MULTI2_CON1 0x06d8 +#define AFE_MPHONE_MULTI2_CON2 0x06dc +#define AFE_MPHONE_MULTI2_MON 0x06e0 +#define AFE_MPHONE_MULTI2_DET_REG_CON0 0x06e4 +#define AFE_MPHONE_MULTI2_DET_REG_CON1 0x06e8 +#define AFE_MPHONE_MULTI2_DET_REG_CON2 0x06ec +#define AFE_MPHONE_MULTI2_DET_REG_CON3 0x06f0 +#define AFE_MPHONE_MULTI2_DET_MON0 0x06f4 +#define AFE_MPHONE_MULTI2_DET_MON1 0x06f8 +#define AFE_MPHONE_MULTI2_DET_MON2 0x06fc +#define AFE_ADDA_IIR_COEF_02_01 0x0700 +#define AFE_ADDA_IIR_COEF_04_03 0x0704 +#define AFE_ADDA_IIR_COEF_06_05 0x0708 +#define AFE_ADDA_IIR_COEF_08_07 0x070c +#define AFE_ADDA_IIR_COEF_10_09 0x0710 +#define AFE_ADDA_ULCF_CFG_02_01 0x0714 +#define AFE_ADDA_ULCF_CFG_04_03 0x0718 +#define AFE_ADDA_ULCF_CFG_06_05 0x071c +#define AFE_ADDA_ULCF_CFG_08_07 0x0720 +#define AFE_ADDA_ULCF_CFG_10_09 0x0724 +#define AFE_ADDA_ULCF_CFG_12_11 0x0728 +#define AFE_ADDA_ULCF_CFG_14_13 0x072c +#define AFE_ADDA_ULCF_CFG_16_15 0x0730 +#define AFE_ADDA_ULCF_CFG_18_17 0x0734 +#define AFE_ADDA_ULCF_CFG_20_19 0x0738 +#define AFE_ADDA_ULCF_CFG_22_21 0x073c +#define AFE_ADDA_ULCF_CFG_24_23 0x0740 +#define AFE_ADDA_ULCF_CFG_26_25 0x0744 +#define AFE_ADDA_ULCF_CFG_28_27 0x0748 +#define AFE_ADDA_ULCF_CFG_30_29 0x074c +#define AFE_ADDA6_IIR_COEF_02_01 0x0750 +#define AFE_ADDA6_IIR_COEF_04_03 0x0754 +#define AFE_ADDA6_IIR_COEF_06_05 0x0758 +#define AFE_ADDA6_IIR_COEF_08_07 0x075c +#define AFE_ADDA6_IIR_COEF_10_09 0x0760 +#define AFE_ADDA6_ULCF_CFG_02_01 0x0764 +#define AFE_ADDA6_ULCF_CFG_04_03 0x0768 +#define AFE_ADDA6_ULCF_CFG_06_05 0x076c +#define AFE_ADDA6_ULCF_CFG_08_07 0x0770 +#define AFE_ADDA6_ULCF_CFG_10_09 0x0774 +#define AFE_ADDA6_ULCF_CFG_12_11 0x0778 +#define AFE_ADDA6_ULCF_CFG_14_13 0x077c +#define AFE_ADDA6_ULCF_CFG_16_15 0x0780 +#define AFE_ADDA6_ULCF_CFG_18_17 0x0784 +#define AFE_ADDA6_ULCF_CFG_20_19 0x0788 +#define AFE_ADDA6_ULCF_CFG_22_21 0x078c +#define AFE_ADDA6_ULCF_CFG_24_23 0x0790 +#define AFE_ADDA6_ULCF_CFG_26_25 0x0794 +#define AFE_ADDA6_ULCF_CFG_28_27 0x0798 +#define AFE_ADDA6_ULCF_CFG_30_29 0x079c +#define AFE_ADDA_MTKAIF_CFG0 0x07a0 +#define AFE_ADDA_MTKAIF_SYNCWORD_CFG 0x07a8 +#define AFE_ADDA_MTKAIF_RX_CFG0 0x07b4 +#define AFE_ADDA_MTKAIF_RX_CFG1 0x07b8 +#define AFE_ADDA_MTKAIF_RX_CFG2 0x07bc +#define AFE_ADDA_MTKAIF_MON0 0x07c8 +#define AFE_ADDA_MTKAIF_MON1 0x07cc +#define AFE_AUD_PAD_TOP 0x07d4 +#define AFE_ADDA6_MTKAIF_MON0 0x07d8 +#define AFE_ADDA6_MTKAIF_MON1 0x07dc +#define AFE_ADDA6_MTKAIF_CFG0 0x07e0 +#define AFE_ADDA6_MTKAIF_RX_CFG0 0x07e4 +#define AFE_ADDA6_MTKAIF_RX_CFG1 0x07e8 +#define AFE_ADDA6_MTKAIF_RX_CFG2 0x07ec +#define AFE_ADDA6_TOP_CON0 0x07f0 +#define AFE_ADDA6_UL_SRC_CON0 0x07f4 +#define AFE_ADDA6_UL_SRC_CON1 0x07f8 +#define AFE_ADDA6_SRC_DEBUG 0x0800 +#define AFE_ADDA6_SRC_DEBUG_MON0 0x0804 +#define AFE_ADDA6_UL_SRC_MON0 0x0818 +#define AFE_ADDA6_UL_SRC_MON1 0x081c +#define AFE_CONN0_5 0x0830 +#define AFE_CONN1_5 0x0834 +#define AFE_CONN2_5 0x0838 +#define AFE_CONN3_5 0x083c +#define AFE_CONN4_5 0x0840 +#define AFE_CONN5_5 0x0844 +#define AFE_CONN6_5 0x0848 +#define AFE_CONN7_5 0x084c +#define AFE_CONN8_5 0x0850 +#define AFE_CONN9_5 0x0854 +#define AFE_CONN10_5 0x0858 +#define AFE_CONN11_5 0x085c +#define AFE_CONN12_5 0x0860 +#define AFE_CONN13_5 0x0864 +#define AFE_CONN14_5 0x0868 +#define AFE_CONN15_5 0x086c +#define AFE_CONN16_5 0x0870 +#define AFE_CONN17_5 0x0874 +#define AFE_CONN18_5 0x0878 +#define AFE_CONN19_5 0x087c +#define AFE_CONN20_5 0x0880 +#define AFE_CONN21_5 0x0884 +#define AFE_CONN22_5 0x0888 +#define AFE_CONN23_5 0x088c +#define AFE_CONN24_5 0x0890 +#define AFE_CONN25_5 0x0894 +#define AFE_CONN26_5 0x0898 +#define AFE_CONN27_5 0x089c +#define AFE_CONN28_5 0x08a0 +#define AFE_CONN29_5 0x08a4 +#define AFE_CONN30_5 0x08a8 +#define AFE_CONN31_5 0x08ac +#define AFE_CONN32_5 0x08b0 +#define AFE_CONN33_5 0x08b4 +#define AFE_CONN34_5 0x08b8 +#define AFE_CONN35_5 0x08bc +#define AFE_CONN36_5 0x08c0 +#define AFE_CONN37_5 0x08c4 +#define AFE_CONN38_5 0x08c8 +#define AFE_CONN39_5 0x08cc +#define AFE_CONN40_5 0x08d0 +#define AFE_CONN41_5 0x08d4 +#define AFE_CONN42_5 0x08d8 +#define AFE_CONN43_5 0x08dc +#define AFE_CONN44_5 0x08e0 +#define AFE_CONN45_5 0x08e4 +#define AFE_CONN46_5 0x08e8 +#define AFE_CONN47_5 0x08ec +#define AFE_CONN48_5 0x08f0 +#define AFE_CONN49_5 0x08f4 +#define AFE_CONN50_5 0x08f8 +#define AFE_CONN51_5 0x08fc +#define AFE_CONN52_5 0x0900 +#define AFE_CONN53_5 0x0904 +#define AFE_CONN54_5 0x0908 +#define AFE_CONN55_5 0x090c +#define AFE_CONN56_5 0x0910 +#define AFE_CONN57_5 0x0914 +#define AFE_CONN58_5 0x0918 +#define AFE_CONN59_5 0x091c +#define AFE_CONN60_5 0x0920 +#define AFE_CONN61_5 0x0924 +#define AFE_CONN62_5 0x0928 +#define AFE_CONN63_5 0x092c +#define AFE_CONN64_5 0x0930 +#define AFE_CONN65_5 0x0934 +#define AFE_CONN66_5 0x0938 +#define AFE_CONN67_5 0x093c +#define AFE_CONN68_5 0x0940 +#define AFE_CONN69_5 0x0944 +#define AFE_CONN70_5 0x0948 +#define AFE_CONN71_5 0x094c +#define AFE_CONN72_5 0x0950 +#define AFE_CONN73_5 0x0954 +#define AFE_CONN74_5 0x0958 +#define AFE_CONN75_5 0x095c +#define AFE_CONN76_5 0x0960 +#define AFE_CONN77_5 0x0964 +#define AFE_CONN78_5 0x0968 +#define AFE_CONN79_5 0x096c +#define AFE_CONN80_5 0x0970 +#define AFE_CONN81_5 0x0974 +#define AFE_CONN82_5 0x0978 +#define AFE_CONN83_5 0x097c +#define AFE_CONN84_5 0x0980 +#define AFE_CONN85_5 0x0984 +#define AFE_CONN86_5 0x0988 +#define AFE_CONN87_5 0x098c +#define AFE_CONN88_5 0x0990 +#define AFE_CONN89_5 0x0994 +#define AFE_CONN90_5 0x0998 +#define AFE_CONN91_5 0x099c +#define AFE_CONN92_5 0x09a0 +#define AFE_CONN93_5 0x09a4 +#define AFE_CONN94_5 0x09a8 +#define AFE_CONN95_5 0x09ac +#define AFE_CONN96_5 0x09b0 +#define AFE_CONN97_5 0x09b4 +#define AFE_CONN98_5 0x09b8 +#define AFE_CONN99_5 0x09bc +#define AFE_CONN100_5 0x09c0 +#define AFE_CONN101_5 0x09c4 +#define AFE_CONN102_5 0x09c8 +#define AFE_CONN103_5 0x09cc +#define AFE_CONN104_5 0x09d0 +#define AFE_CONN105_5 0x09d4 +#define AFE_CONN106_5 0x09d8 +#define AFE_CONN107_5 0x09dc +#define AFE_CONN108_5 0x09e0 +#define AFE_CONN109_5 0x09e4 +#define AFE_CONN110_5 0x09e8 +#define AFE_CONN111_5 0x09ec +#define AFE_CONN112_5 0x09f0 +#define AFE_CONN113_5 0x09f4 +#define AFE_CONN114_5 0x09f8 +#define AFE_CONN115_5 0x09fc +#define AFE_CONN116_5 0x0a00 +#define AFE_CONN117_5 0x0a04 +#define AFE_CONN118_5 0x0a08 +#define AFE_CONN119_5 0x0a0c +#define AFE_CONN120_5 0x0a10 +#define AFE_CONN121_5 0x0a14 +#define AFE_CONN122_5 0x0a18 +#define AFE_CONN123_5 0x0a1c +#define AFE_CONN124_5 0x0a20 +#define AFE_CONN125_5 0x0a24 +#define AFE_CONN126_5 0x0a28 +#define AFE_CONN127_5 0x0a2c +#define AFE_CONN128_5 0x0a30 +#define AFE_CONN129_5 0x0a34 +#define AFE_CONN130_5 0x0a38 +#define AFE_CONN131_5 0x0a3c +#define AFE_CONN132_5 0x0a40 +#define AFE_CONN133_5 0x0a44 +#define AFE_CONN134_5 0x0a48 +#define AFE_CONN135_5 0x0a4c +#define AFE_CONN136_5 0x0a50 +#define AFE_CONN137_5 0x0a54 +#define AFE_CONN138_5 0x0a58 +#define AFE_CONN139_5 0x0a5c +#define AFE_CONN_RS_5 0x0a60 +#define AFE_CONN_DI_5 0x0a64 +#define AFE_CONN_16BIT_5 0x0a68 +#define AFE_CONN_24BIT_5 0x0a6c +#define AFE_ASRC11_NEW_CON0 0x0d80 +#define AFE_ASRC11_NEW_CON1 0x0d84 +#define AFE_ASRC11_NEW_CON2 0x0d88 +#define AFE_ASRC11_NEW_CON3 0x0d8c +#define AFE_ASRC11_NEW_CON4 0x0d90 +#define AFE_ASRC11_NEW_CON5 0x0d94 +#define AFE_ASRC11_NEW_CON6 0x0d98 +#define AFE_ASRC11_NEW_CON7 0x0d9c +#define AFE_ASRC11_NEW_CON8 0x0da0 +#define AFE_ASRC11_NEW_CON9 0x0da4 +#define AFE_ASRC11_NEW_CON10 0x0da8 +#define AFE_ASRC11_NEW_CON11 0x0dac +#define AFE_ASRC11_NEW_CON13 0x0db4 +#define AFE_ASRC11_NEW_CON14 0x0db8 +#define AFE_ASRC12_NEW_CON0 0x0dc0 +#define AFE_ASRC12_NEW_CON1 0x0dc4 +#define AFE_ASRC12_NEW_CON2 0x0dc8 +#define AFE_ASRC12_NEW_CON3 0x0dcc +#define AFE_ASRC12_NEW_CON4 0x0dd0 +#define AFE_ASRC12_NEW_CON5 0x0dd4 +#define AFE_ASRC12_NEW_CON6 0x0dd8 +#define AFE_ASRC12_NEW_CON7 0x0ddc +#define AFE_ASRC12_NEW_CON8 0x0de0 +#define AFE_ASRC12_NEW_CON9 0x0de4 +#define AFE_ASRC12_NEW_CON10 0x0de8 +#define AFE_ASRC12_NEW_CON11 0x0dec +#define AFE_ASRC12_NEW_CON13 0x0df4 +#define AFE_ASRC12_NEW_CON14 0x0df8 +#define AFE_LRCK_CNT 0x1018 +#define AFE_DAC_CON0 0x1200 +#define AFE_DAC_CON1 0x1204 +#define AFE_DAC_CON2 0x1208 +#define AFE_DAC_MON0 0x1218 +#define AFE_DL2_BASE 0x1250 +#define AFE_DL2_CUR 0x1254 +#define AFE_DL2_END 0x1258 +#define AFE_DL2_CON0 0x125c +#define AFE_DL3_BASE 0x1260 +#define AFE_DL3_CUR 0x1264 +#define AFE_DL3_END 0x1268 +#define AFE_DL3_CON0 0x126c +#define AFE_DL6_BASE 0x1290 +#define AFE_DL6_CUR 0x1294 +#define AFE_DL6_END 0x1298 +#define AFE_DL6_CON0 0x129c +#define AFE_DL7_BASE 0x12a0 +#define AFE_DL7_CUR 0x12a4 +#define AFE_DL7_END 0x12a8 +#define AFE_DL7_CON0 0x12ac +#define AFE_DL8_BASE 0x12b0 +#define AFE_DL8_CUR 0x12b4 +#define AFE_DL8_END 0x12b8 +#define AFE_DL8_CON0 0x12bc +#define AFE_DL10_BASE 0x12d0 +#define AFE_DL10_CUR 0x12d4 +#define AFE_DL10_END 0x12d8 +#define AFE_DL10_CON0 0x12dc +#define AFE_DL11_BASE 0x12e0 +#define AFE_DL11_CUR 0x12e4 +#define AFE_DL11_END 0x12e8 +#define AFE_DL11_CON0 0x12ec +#define AFE_UL1_BASE 0x1300 +#define AFE_UL1_CUR 0x1304 +#define AFE_UL1_END 0x1308 +#define AFE_UL1_CON0 0x130c +#define AFE_UL2_BASE 0x1310 +#define AFE_UL2_CUR 0x1314 +#define AFE_UL2_END 0x1318 +#define AFE_UL2_CON0 0x131c +#define AFE_UL3_BASE 0x1320 +#define AFE_UL3_CUR 0x1324 +#define AFE_UL3_END 0x1328 +#define AFE_UL3_CON0 0x132c +#define AFE_UL4_BASE 0x1330 +#define AFE_UL4_CUR 0x1334 +#define AFE_UL4_END 0x1338 +#define AFE_UL4_CON0 0x133c +#define AFE_UL5_BASE 0x1340 +#define AFE_UL5_CUR 0x1344 +#define AFE_UL5_END 0x1348 +#define AFE_UL5_CON0 0x134c +#define AFE_UL6_BASE 0x1350 +#define AFE_UL6_CUR 0x1354 +#define AFE_UL6_END 0x1358 +#define AFE_UL6_CON0 0x135c +#define AFE_UL8_BASE 0x1370 +#define AFE_UL8_CUR 0x1374 +#define AFE_UL8_END 0x1378 +#define AFE_UL8_CON0 0x137c +#define AFE_UL9_BASE 0x1380 +#define AFE_UL9_CUR 0x1384 +#define AFE_UL9_END 0x1388 +#define AFE_UL9_CON0 0x138c +#define AFE_UL10_BASE 0x13d0 +#define AFE_UL10_CUR 0x13d4 +#define AFE_UL10_END 0x13d8 +#define AFE_UL10_CON0 0x13dc +#define AFE_DL8_CHK_SUM1 0x1400 +#define AFE_DL8_CHK_SUM2 0x1404 +#define AFE_DL8_CHK_SUM3 0x1408 +#define AFE_DL8_CHK_SUM4 0x140c +#define AFE_DL8_CHK_SUM5 0x1410 +#define AFE_DL8_CHK_SUM6 0x1414 +#define AFE_DL10_CHK_SUM1 0x1418 +#define AFE_DL10_CHK_SUM2 0x141c +#define AFE_DL10_CHK_SUM3 0x1420 +#define AFE_DL10_CHK_SUM4 0x1424 +#define AFE_DL10_CHK_SUM5 0x1428 +#define AFE_DL10_CHK_SUM6 0x142c +#define AFE_DL11_CHK_SUM1 0x1430 +#define AFE_DL11_CHK_SUM2 0x1434 +#define AFE_DL11_CHK_SUM3 0x1438 +#define AFE_DL11_CHK_SUM4 0x143c +#define AFE_DL11_CHK_SUM5 0x1440 +#define AFE_DL11_CHK_SUM6 0x1444 +#define AFE_UL1_CHK_SUM1 0x1450 +#define AFE_UL1_CHK_SUM2 0x1454 +#define AFE_UL2_CHK_SUM1 0x1458 +#define AFE_UL2_CHK_SUM2 0x145c +#define AFE_UL3_CHK_SUM1 0x1460 +#define AFE_UL3_CHK_SUM2 0x1464 +#define AFE_UL4_CHK_SUM1 0x1468 +#define AFE_UL4_CHK_SUM2 0x146c +#define AFE_UL5_CHK_SUM1 0x1470 +#define AFE_UL5_CHK_SUM2 0x1474 +#define AFE_UL6_CHK_SUM1 0x1478 +#define AFE_UL6_CHK_SUM2 0x147c +#define AFE_UL8_CHK_SUM1 0x1488 +#define AFE_UL8_CHK_SUM2 0x148c +#define AFE_DL2_CHK_SUM1 0x14a0 +#define AFE_DL2_CHK_SUM2 0x14a4 +#define AFE_DL3_CHK_SUM1 0x14b0 +#define AFE_DL3_CHK_SUM2 0x14b4 +#define AFE_DL6_CHK_SUM1 0x14e0 +#define AFE_DL6_CHK_SUM2 0x14e4 +#define AFE_DL7_CHK_SUM1 0x14f0 +#define AFE_DL7_CHK_SUM2 0x14f4 +#define AFE_UL9_CHK_SUM1 0x1528 +#define AFE_UL9_CHK_SUM2 0x152c +#define AFE_BUS_MON1 0x1540 +#define UL1_MOD2AGT_CNT_LAT 0x1568 +#define UL2_MOD2AGT_CNT_LAT 0x156c +#define UL3_MOD2AGT_CNT_LAT 0x1570 +#define UL4_MOD2AGT_CNT_LAT 0x1574 +#define UL5_MOD2AGT_CNT_LAT 0x1578 +#define UL6_MOD2AGT_CNT_LAT 0x157c +#define UL8_MOD2AGT_CNT_LAT 0x1588 +#define UL9_MOD2AGT_CNT_LAT 0x158c +#define UL10_MOD2AGT_CNT_LAT 0x1590 +#define AFE_MEMIF_AGENT_FS_CON0 0x15a0 +#define AFE_MEMIF_AGENT_FS_CON1 0x15a4 +#define AFE_MEMIF_AGENT_FS_CON2 0x15a8 +#define AFE_MEMIF_AGENT_FS_CON3 0x15ac +#define AFE_MEMIF_BURST_CFG 0x1600 +#define AFE_MEMIF_BUF_FULL_MON 0x1610 +#define AFE_MEMIF_BUF_MON1 0x161c +#define AFE_MEMIF_BUF_MON3 0x1624 +#define AFE_MEMIF_BUF_MON4 0x1628 +#define AFE_MEMIF_BUF_MON5 0x162c +#define AFE_MEMIF_BUF_MON6 0x1630 +#define AFE_MEMIF_BUF_MON7 0x1634 +#define AFE_MEMIF_BUF_MON8 0x1638 +#define AFE_MEMIF_BUF_MON9 0x163c +#define AFE_MEMIF_BUF_MON10 0x1640 +#define DL2_AGENT2MODULE_CNT 0x1678 +#define DL3_AGENT2MODULE_CNT 0x167c +#define DL6_AGENT2MODULE_CNT 0x1688 +#define DL7_AGENT2MODULE_CNT 0x168c +#define DL8_AGENT2MODULE_CNT 0x1690 +#define DL10_AGENT2MODULE_CNT 0x1698 +#define DL11_AGENT2MODULE_CNT 0x169c +#define UL1_MODULE2AGENT_CNT 0x16a0 +#define UL2_MODULE2AGENT_CNT 0x16a4 +#define UL3_MODULE2AGENT_CNT 0x16a8 +#define UL4_MODULE2AGENT_CNT 0x16ac +#define UL5_MODULE2AGENT_CNT 0x16b0 +#define UL6_MODULE2AGENT_CNT 0x16b4 +#define UL8_MODULE2AGENT_CNT 0x16bc +#define UL9_MODULE2AGENT_CNT 0x16c0 +#define UL10_MODULE2AGENT_CNT 0x16c4 +#define AFE_SECURE_CON2 0x1798 +#define AFE_SECURE_CON1 0x179c +#define AFE_SECURE_CON 0x17a0 +#define AFE_SRAM_BOUND 0x17a4 +#define AFE_SE_SECURE_CON 0x17a8 +#define AFE_SECURE_MASK_LOOPBACK 0x17bc +#define AFE_SECURE_SIDEBAND0 0x1908 +#define AFE_SECURE_SIDEBAND1 0x190c +#define AFE_SECURE_SIDEBAND2 0x1910 +#define AFE_SECURE_SIDEBAND3 0x1914 +#define AFE_SECURE_MASK_BASE_ADR_MSB 0x1920 +#define AFE_SECURE_MASK_END_ADR_MSB 0x1924 +#define AFE_NORMAL_BASE_ADR_MSB 0x192c +#define AFE_NORMAL_END_ADR_MSB 0x1930 +#define AFE_SECURE_MASK_LOOPBACK0 0x1940 +#define AFE_SECURE_MASK_LOOPBACK1 0x1944 +#define AFE_SECURE_MASK_LOOPBACK2 0x1948 +#define AFE_LOOPBACK_CFG0 0x1950 +#define AFE_LOOPBACK_CFG1 0x1954 +#define AFE_LOOPBACK_CFG2 0x1958 +#define AFE_DMIC0_UL_SRC_CON0 0x1a00 +#define AFE_DMIC0_UL_SRC_CON1 0x1a04 +#define AFE_DMIC0_SRC_DEBUG 0x1a08 +#define AFE_DMIC0_SRC_DEBUG_MON0 0x1a0c +#define AFE_DMIC0_UL_SRC_MON0 0x1a10 +#define AFE_DMIC0_UL_SRC_MON1 0x1a14 +#define AFE_DMIC0_IIR_COEF_02_01 0x1a18 +#define AFE_DMIC0_IIR_COEF_04_03 0x1a1c +#define AFE_DMIC0_IIR_COEF_06_05 0x1a20 +#define AFE_DMIC0_IIR_COEF_08_07 0x1a24 +#define AFE_DMIC0_IIR_COEF_10_09 0x1a28 +#define AFE_DMIC1_UL_SRC_CON0 0x1a68 +#define AFE_DMIC1_UL_SRC_CON1 0x1a6c +#define AFE_DMIC1_SRC_DEBUG 0x1a70 +#define AFE_DMIC1_SRC_DEBUG_MON0 0x1a74 +#define AFE_DMIC1_UL_SRC_MON0 0x1a78 +#define AFE_DMIC1_UL_SRC_MON1 0x1a7c +#define AFE_DMIC1_IIR_COEF_02_01 0x1a80 +#define AFE_DMIC1_IIR_COEF_04_03 0x1a84 +#define AFE_DMIC1_IIR_COEF_06_05 0x1a88 +#define AFE_DMIC1_IIR_COEF_08_07 0x1a8c +#define AFE_DMIC1_IIR_COEF_10_09 0x1a90 +#define AFE_DMIC2_UL_SRC_CON0 0x1ad0 +#define AFE_DMIC2_UL_SRC_CON1 0x1ad4 +#define AFE_DMIC2_SRC_DEBUG 0x1ad8 +#define AFE_DMIC2_SRC_DEBUG_MON0 0x1adc +#define AFE_DMIC2_UL_SRC_MON0 0x1ae0 +#define AFE_DMIC2_UL_SRC_MON1 0x1ae4 +#define AFE_DMIC2_IIR_COEF_02_01 0x1ae8 +#define AFE_DMIC2_IIR_COEF_04_03 0x1aec +#define AFE_DMIC2_IIR_COEF_06_05 0x1af0 +#define AFE_DMIC2_IIR_COEF_08_07 0x1af4 +#define AFE_DMIC2_IIR_COEF_10_09 0x1af8 +#define AFE_DMIC3_UL_SRC_CON0 0x1b38 +#define AFE_DMIC3_UL_SRC_CON1 0x1b3c +#define AFE_DMIC3_SRC_DEBUG 0x1b40 +#define AFE_DMIC3_SRC_DEBUG_MON0 0x1b44 +#define AFE_DMIC3_UL_SRC_MON0 0x1b48 +#define AFE_DMIC3_UL_SRC_MON1 0x1b4c +#define AFE_DMIC3_IIR_COEF_02_01 0x1b50 +#define AFE_DMIC3_IIR_COEF_04_03 0x1b54 +#define AFE_DMIC3_IIR_COEF_06_05 0x1b58 +#define AFE_DMIC3_IIR_COEF_08_07 0x1b5c +#define AFE_DMIC3_IIR_COEF_10_09 0x1b60 +#define DMIC_BYPASS_HW_GAIN 0x1bf0 +#define DMIC_GAIN1_CON0 0x1c00 +#define DMIC_GAIN1_CON1 0x1c04 +#define DMIC_GAIN1_CON2 0x1c08 +#define DMIC_GAIN1_CON3 0x1c0c +#define DMIC_GAIN1_CUR 0x1c10 +#define DMIC_GAIN2_CON0 0x1c20 +#define DMIC_GAIN2_CON1 0x1c24 +#define DMIC_GAIN2_CON2 0x1c28 +#define DMIC_GAIN2_CON3 0x1c2c +#define DMIC_GAIN2_CUR 0x1c30 +#define DMIC_GAIN3_CON0 0x1c40 +#define DMIC_GAIN3_CON1 0x1c44 +#define DMIC_GAIN3_CON2 0x1c48 +#define DMIC_GAIN3_CON3 0x1c4c +#define DMIC_GAIN3_CUR 0x1c50 +#define DMIC_GAIN4_CON0 0x1c60 +#define DMIC_GAIN4_CON1 0x1c64 +#define DMIC_GAIN4_CON2 0x1c68 +#define DMIC_GAIN4_CON3 0x1c6c +#define DMIC_GAIN4_CUR 0x1c70 +#define ETDM_OUT1_DSD_FADE_CON 0x2260 +#define ETDM_OUT1_DSD_FADE_CON1 0x2264 +#define ETDM_OUT3_DSD_FADE_CON 0x2280 +#define ETDM_OUT3_DSD_FADE_CON1 0x2284 +#define ETDM_IN1_AFIFO_CON 0x2294 +#define ETDM_IN2_AFIFO_CON 0x2298 +#define ETDM_IN1_MONITOR 0x22c0 +#define ETDM_IN2_MONITOR 0x22c4 +#define ETDM_OUT1_MONITOR 0x22d0 +#define ETDM_OUT2_MONITOR 0x22d4 +#define ETDM_OUT3_MONITOR 0x22d8 +#define ETDM_COWORK_SEC_CON0 0x22e0 +#define ETDM_COWORK_SEC_CON1 0x22e4 +#define ETDM_COWORK_SEC_CON2 0x22e8 +#define ETDM_COWORK_SEC_CON3 0x22ec +#define ETDM_COWORK_CON0 0x22f0 +#define ETDM_COWORK_CON1 0x22f4 +#define ETDM_COWORK_CON2 0x22f8 +#define ETDM_COWORK_CON3 0x22fc +#define ETDM_IN1_CON0 0x2300 +#define ETDM_IN1_CON1 0x2304 +#define ETDM_IN1_CON2 0x2308 +#define ETDM_IN1_CON3 0x230c +#define ETDM_IN1_CON4 0x2310 +#define ETDM_IN1_CON5 0x2314 +#define ETDM_IN1_CON6 0x2318 +#define ETDM_IN1_CON7 0x231c +#define ETDM_IN2_CON0 0x2320 +#define ETDM_IN2_CON1 0x2324 +#define ETDM_IN2_CON2 0x2328 +#define ETDM_IN2_CON3 0x232c +#define ETDM_IN2_CON4 0x2330 +#define ETDM_IN2_CON5 0x2334 +#define ETDM_IN2_CON6 0x2338 +#define ETDM_IN2_CON7 0x233c +#define ETDM_OUT1_CON0 0x2380 +#define ETDM_OUT1_CON1 0x2384 +#define ETDM_OUT1_CON2 0x2388 +#define ETDM_OUT1_CON3 0x238c +#define ETDM_OUT1_CON4 0x2390 +#define ETDM_OUT1_CON5 0x2394 +#define ETDM_OUT1_CON6 0x2398 +#define ETDM_OUT1_CON7 0x239c +#define ETDM_OUT2_CON0 0x23a0 +#define ETDM_OUT2_CON1 0x23a4 +#define ETDM_OUT2_CON2 0x23a8 +#define ETDM_OUT2_CON3 0x23ac +#define ETDM_OUT2_CON4 0x23b0 +#define ETDM_OUT2_CON5 0x23b4 +#define ETDM_OUT2_CON6 0x23b8 +#define ETDM_OUT2_CON7 0x23bc +#define ETDM_OUT3_CON0 0x23c0 +#define ETDM_OUT3_CON1 0x23c4 +#define ETDM_OUT3_CON2 0x23c8 +#define ETDM_OUT3_CON3 0x23cc +#define ETDM_OUT3_CON4 0x23d0 +#define ETDM_OUT3_CON5 0x23d4 +#define ETDM_OUT3_CON6 0x23d8 +#define ETDM_OUT3_CON7 0x23dc +#define ETDM_OUT3_CON8 0x23e0 +#define ETDM_OUT1_CON8 0x23e4 +#define ETDM_OUT2_CON8 0x23e8 +#define GASRC_TIMING_CON0 0x2414 +#define GASRC_TIMING_CON1 0x2418 +#define GASRC_TIMING_CON2 0x241c +#define GASRC_TIMING_CON3 0x2420 +#define GASRC_TIMING_CON4 0x2424 +#define GASRC_TIMING_CON5 0x2428 +#define GASRC_TIMING_CON6 0x242c +#define GASRC_TIMING_CON7 0x2430 +#define A3_A4_TIMING_SEL0 0x2440 +#define A3_A4_TIMING_SEL1 0x2444 +#define A3_A4_TIMING_SEL2 0x2448 +#define A3_A4_TIMING_SEL3 0x244c +#define A3_A4_TIMING_SEL4 0x2450 +#define A3_A4_TIMING_SEL5 0x2454 +#define A3_A4_TIMING_SEL6 0x2458 +#define ASYS_TOP_DEBUG 0x2500 +#define AFE_DPTX_CON 0x2558 +#define AFE_DPTX_MON 0x255c +#define AFE_ADDA_DL_SRC2_CON0 0x2d00 +#define AFE_ADDA_DL_SRC2_CON1 0x2d04 +#define AFE_ADDA_TOP_CON0 0x2d0c +#define AFE_ADDA_UL_DL_CON0 0x2d10 +#define AFE_ADDA_SRC_DEBUG 0x2d14 +#define AFE_ADDA_SRC_DEBUG_MON0 0x2d18 +#define AFE_ADDA_SRC_DEBUG_MON1 0x2d20 +#define AFE_ADDA_PREDIS_CON0 0x2d24 +#define AFE_ADDA_PREDIS_CON1 0x2d28 +#define AFE_ADDA_PREDIS_CON2 0x2d2c +#define AFE_ADDA_PREDIS_CON3 0x2d30 +#define AFE_ADDA_DL_SDM_DCCOMP_CON 0x2d34 +#define AFE_ADDA_DL_SDM_TEST 0x2d38 +#define AFE_ADDA_DL_DC_COMP_CFG0 0x2d3c +#define AFE_ADDA_DL_DC_COMP_CFG1 0x2d40 +#define AFE_ADDA_DL_SDM_FIFO_MON 0x2d44 +#define AFE_ADDA_DL_SRC_LCH_MON 0x2d50 +#define AFE_ADDA_DL_SRC_RCH_MON 0x2d54 +#define AFE_ADDA_DL_SDM_OUT_MON 0x2d58 +#define AFE_ADDA_DL_SDM_DITHER_CON 0x2d5c +#define AFE_ADDA_DL_SDM_AUTO_RESET_CON 0x2d60 +#define AFE_ADDA_UL_SRC_CON0 0x2e3c +#define AFE_ADDA_UL_SRC_CON1 0x2e40 +#define AFE_CONN0 0x3000 +#define AFE_CONN0_1 0x3004 +#define AFE_CONN0_2 0x3008 +#define AFE_CONN0_3 0x300c +#define AFE_CONN0_4 0x3010 +#define AFE_CONN1 0x3014 +#define AFE_CONN1_1 0x3018 +#define AFE_CONN1_2 0x301c +#define AFE_CONN1_3 0x3020 +#define AFE_CONN1_4 0x3024 +#define AFE_CONN2 0x3028 +#define AFE_CONN2_1 0x302c +#define AFE_CONN2_2 0x3030 +#define AFE_CONN2_3 0x3034 +#define AFE_CONN2_4 0x3038 +#define AFE_CONN3 0x303c +#define AFE_CONN3_1 0x3040 +#define AFE_CONN3_2 0x3044 +#define AFE_CONN3_3 0x3048 +#define AFE_CONN3_4 0x304c +#define AFE_CONN4 0x3050 +#define AFE_CONN4_1 0x3054 +#define AFE_CONN4_2 0x3058 +#define AFE_CONN4_3 0x305c +#define AFE_CONN4_4 0x3060 +#define AFE_CONN5 0x3064 +#define AFE_CONN5_1 0x3068 +#define AFE_CONN5_2 0x306c +#define AFE_CONN5_3 0x3070 +#define AFE_CONN5_4 0x3074 +#define AFE_CONN6 0x3078 +#define AFE_CONN6_1 0x307c +#define AFE_CONN6_2 0x3080 +#define AFE_CONN6_3 0x3084 +#define AFE_CONN6_4 0x3088 +#define AFE_CONN7 0x308c +#define AFE_CONN7_1 0x3090 +#define AFE_CONN7_2 0x3094 +#define AFE_CONN7_3 0x3098 +#define AFE_CONN7_4 0x309c +#define AFE_CONN8 0x30a0 +#define AFE_CONN8_1 0x30a4 +#define AFE_CONN8_2 0x30a8 +#define AFE_CONN8_3 0x30ac +#define AFE_CONN8_4 0x30b0 +#define AFE_CONN9 0x30b4 +#define AFE_CONN9_1 0x30b8 +#define AFE_CONN9_2 0x30bc +#define AFE_CONN9_3 0x30c0 +#define AFE_CONN9_4 0x30c4 +#define AFE_CONN10 0x30c8 +#define AFE_CONN10_1 0x30cc +#define AFE_CONN10_2 0x30d0 +#define AFE_CONN10_3 0x30d4 +#define AFE_CONN10_4 0x30d8 +#define AFE_CONN11 0x30dc +#define AFE_CONN11_1 0x30e0 +#define AFE_CONN11_2 0x30e4 +#define AFE_CONN11_3 0x30e8 +#define AFE_CONN11_4 0x30ec +#define AFE_CONN12 0x30f0 +#define AFE_CONN12_1 0x30f4 +#define AFE_CONN12_2 0x30f8 +#define AFE_CONN12_3 0x30fc +#define AFE_CONN12_4 0x3100 +#define AFE_CONN13 0x3104 +#define AFE_CONN13_1 0x3108 +#define AFE_CONN13_2 0x310c +#define AFE_CONN13_3 0x3110 +#define AFE_CONN13_4 0x3114 +#define AFE_CONN14 0x3118 +#define AFE_CONN14_1 0x311c +#define AFE_CONN14_2 0x3120 +#define AFE_CONN14_3 0x3124 +#define AFE_CONN14_4 0x3128 +#define AFE_CONN15 0x312c +#define AFE_CONN15_1 0x3130 +#define AFE_CONN15_2 0x3134 +#define AFE_CONN15_3 0x3138 +#define AFE_CONN15_4 0x313c +#define AFE_CONN16 0x3140 +#define AFE_CONN16_1 0x3144 +#define AFE_CONN16_2 0x3148 +#define AFE_CONN16_3 0x314c +#define AFE_CONN16_4 0x3150 +#define AFE_CONN17 0x3154 +#define AFE_CONN17_1 0x3158 +#define AFE_CONN17_2 0x315c +#define AFE_CONN17_3 0x3160 +#define AFE_CONN17_4 0x3164 +#define AFE_CONN18 0x3168 +#define AFE_CONN18_1 0x316c +#define AFE_CONN18_2 0x3170 +#define AFE_CONN18_3 0x3174 +#define AFE_CONN18_4 0x3178 +#define AFE_CONN19 0x317c +#define AFE_CONN19_1 0x3180 +#define AFE_CONN19_2 0x3184 +#define AFE_CONN19_3 0x3188 +#define AFE_CONN19_4 0x318c +#define AFE_CONN20 0x3190 +#define AFE_CONN20_1 0x3194 +#define AFE_CONN20_2 0x3198 +#define AFE_CONN20_3 0x319c +#define AFE_CONN20_4 0x31a0 +#define AFE_CONN21 0x31a4 +#define AFE_CONN21_1 0x31a8 +#define AFE_CONN21_2 0x31ac +#define AFE_CONN21_3 0x31b0 +#define AFE_CONN21_4 0x31b4 +#define AFE_CONN22 0x31b8 +#define AFE_CONN22_1 0x31bc +#define AFE_CONN22_2 0x31c0 +#define AFE_CONN22_3 0x31c4 +#define AFE_CONN22_4 0x31c8 +#define AFE_CONN23 0x31cc +#define AFE_CONN23_1 0x31d0 +#define AFE_CONN23_2 0x31d4 +#define AFE_CONN23_3 0x31d8 +#define AFE_CONN23_4 0x31dc +#define AFE_CONN24 0x31e0 +#define AFE_CONN24_1 0x31e4 +#define AFE_CONN24_2 0x31e8 +#define AFE_CONN24_3 0x31ec +#define AFE_CONN24_4 0x31f0 +#define AFE_CONN25 0x31f4 +#define AFE_CONN25_1 0x31f8 +#define AFE_CONN25_2 0x31fc +#define AFE_CONN25_3 0x3200 +#define AFE_CONN25_4 0x3204 +#define AFE_CONN26 0x3208 +#define AFE_CONN26_1 0x320c +#define AFE_CONN26_2 0x3210 +#define AFE_CONN26_3 0x3214 +#define AFE_CONN26_4 0x3218 +#define AFE_CONN27 0x321c +#define AFE_CONN27_1 0x3220 +#define AFE_CONN27_2 0x3224 +#define AFE_CONN27_3 0x3228 +#define AFE_CONN27_4 0x322c +#define AFE_CONN28 0x3230 +#define AFE_CONN28_1 0x3234 +#define AFE_CONN28_2 0x3238 +#define AFE_CONN28_3 0x323c +#define AFE_CONN28_4 0x3240 +#define AFE_CONN29 0x3244 +#define AFE_CONN29_1 0x3248 +#define AFE_CONN29_2 0x324c +#define AFE_CONN29_3 0x3250 +#define AFE_CONN29_4 0x3254 +#define AFE_CONN30 0x3258 +#define AFE_CONN30_1 0x325c +#define AFE_CONN30_2 0x3260 +#define AFE_CONN30_3 0x3264 +#define AFE_CONN30_4 0x3268 +#define AFE_CONN31 0x326c +#define AFE_CONN31_1 0x3270 +#define AFE_CONN31_2 0x3274 +#define AFE_CONN31_3 0x3278 +#define AFE_CONN31_4 0x327c +#define AFE_CONN32 0x3280 +#define AFE_CONN32_1 0x3284 +#define AFE_CONN32_2 0x3288 +#define AFE_CONN32_3 0x328c +#define AFE_CONN32_4 0x3290 +#define AFE_CONN33 0x3294 +#define AFE_CONN33_1 0x3298 +#define AFE_CONN33_2 0x329c +#define AFE_CONN33_3 0x32a0 +#define AFE_CONN33_4 0x32a4 +#define AFE_CONN34 0x32a8 +#define AFE_CONN34_1 0x32ac +#define AFE_CONN34_2 0x32b0 +#define AFE_CONN34_3 0x32b4 +#define AFE_CONN34_4 0x32b8 +#define AFE_CONN35 0x32bc +#define AFE_CONN35_1 0x32c0 +#define AFE_CONN35_2 0x32c4 +#define AFE_CONN35_3 0x32c8 +#define AFE_CONN35_4 0x32cc +#define AFE_CONN36 0x32d0 +#define AFE_CONN36_1 0x32d4 +#define AFE_CONN36_2 0x32d8 +#define AFE_CONN36_3 0x32dc +#define AFE_CONN36_4 0x32e0 +#define AFE_CONN37 0x32e4 +#define AFE_CONN37_1 0x32e8 +#define AFE_CONN37_2 0x32ec +#define AFE_CONN37_3 0x32f0 +#define AFE_CONN37_4 0x32f4 +#define AFE_CONN38 0x32f8 +#define AFE_CONN38_1 0x32fc +#define AFE_CONN38_2 0x3300 +#define AFE_CONN38_3 0x3304 +#define AFE_CONN38_4 0x3308 +#define AFE_CONN39 0x330c +#define AFE_CONN39_1 0x3310 +#define AFE_CONN39_2 0x3314 +#define AFE_CONN39_3 0x3318 +#define AFE_CONN39_4 0x331c +#define AFE_CONN40 0x3320 +#define AFE_CONN40_1 0x3324 +#define AFE_CONN40_2 0x3328 +#define AFE_CONN40_3 0x332c +#define AFE_CONN40_4 0x3330 +#define AFE_CONN41 0x3334 +#define AFE_CONN41_1 0x3338 +#define AFE_CONN41_2 0x333c +#define AFE_CONN41_3 0x3340 +#define AFE_CONN41_4 0x3344 +#define AFE_CONN42 0x3348 +#define AFE_CONN42_1 0x334c +#define AFE_CONN42_2 0x3350 +#define AFE_CONN42_3 0x3354 +#define AFE_CONN42_4 0x3358 +#define AFE_CONN43 0x335c +#define AFE_CONN43_1 0x3360 +#define AFE_CONN43_2 0x3364 +#define AFE_CONN43_3 0x3368 +#define AFE_CONN43_4 0x336c +#define AFE_CONN44 0x3370 +#define AFE_CONN44_1 0x3374 +#define AFE_CONN44_2 0x3378 +#define AFE_CONN44_3 0x337c +#define AFE_CONN44_4 0x3380 +#define AFE_CONN45 0x3384 +#define AFE_CONN45_1 0x3388 +#define AFE_CONN45_2 0x338c +#define AFE_CONN45_3 0x3390 +#define AFE_CONN45_4 0x3394 +#define AFE_CONN46 0x3398 +#define AFE_CONN46_1 0x339c +#define AFE_CONN46_2 0x33a0 +#define AFE_CONN46_3 0x33a4 +#define AFE_CONN46_4 0x33a8 +#define AFE_CONN47 0x33ac +#define AFE_CONN47_1 0x33b0 +#define AFE_CONN47_2 0x33b4 +#define AFE_CONN47_3 0x33b8 +#define AFE_CONN47_4 0x33bc +#define AFE_CONN48 0x33c0 +#define AFE_CONN48_1 0x33c4 +#define AFE_CONN48_2 0x33c8 +#define AFE_CONN48_3 0x33cc +#define AFE_CONN48_4 0x33d0 +#define AFE_CONN49 0x33d4 +#define AFE_CONN49_1 0x33d8 +#define AFE_CONN49_2 0x33dc +#define AFE_CONN49_3 0x33e0 +#define AFE_CONN49_4 0x33e4 +#define AFE_CONN50 0x33e8 +#define AFE_CONN50_1 0x33ec +#define AFE_CONN50_2 0x33f0 +#define AFE_CONN50_3 0x33f4 +#define AFE_CONN50_4 0x33f8 +#define AFE_CONN51 0x33fc +#define AFE_CONN51_1 0x3400 +#define AFE_CONN51_2 0x3404 +#define AFE_CONN51_3 0x3408 +#define AFE_CONN51_4 0x340c +#define AFE_CONN52 0x3410 +#define AFE_CONN52_1 0x3414 +#define AFE_CONN52_2 0x3418 +#define AFE_CONN52_3 0x341c +#define AFE_CONN52_4 0x3420 +#define AFE_CONN53 0x3424 +#define AFE_CONN53_1 0x3428 +#define AFE_CONN53_2 0x342c +#define AFE_CONN53_3 0x3430 +#define AFE_CONN53_4 0x3434 +#define AFE_CONN54 0x3438 +#define AFE_CONN54_1 0x343c +#define AFE_CONN54_2 0x3440 +#define AFE_CONN54_3 0x3444 +#define AFE_CONN54_4 0x3448 +#define AFE_CONN55 0x344c +#define AFE_CONN55_1 0x3450 +#define AFE_CONN55_2 0x3454 +#define AFE_CONN55_3 0x3458 +#define AFE_CONN55_4 0x345c +#define AFE_CONN56 0x3460 +#define AFE_CONN56_1 0x3464 +#define AFE_CONN56_2 0x3468 +#define AFE_CONN56_3 0x346c +#define AFE_CONN56_4 0x3470 +#define AFE_CONN57 0x3474 +#define AFE_CONN57_1 0x3478 +#define AFE_CONN57_2 0x347c +#define AFE_CONN57_3 0x3480 +#define AFE_CONN57_4 0x3484 +#define AFE_CONN58 0x3488 +#define AFE_CONN58_1 0x348c +#define AFE_CONN58_2 0x3490 +#define AFE_CONN58_3 0x3494 +#define AFE_CONN58_4 0x3498 +#define AFE_CONN59 0x349c +#define AFE_CONN59_1 0x34a0 +#define AFE_CONN59_2 0x34a4 +#define AFE_CONN59_3 0x34a8 +#define AFE_CONN59_4 0x34ac +#define AFE_CONN60 0x34b0 +#define AFE_CONN60_1 0x34b4 +#define AFE_CONN60_2 0x34b8 +#define AFE_CONN60_3 0x34bc +#define AFE_CONN60_4 0x34c0 +#define AFE_CONN61 0x34c4 +#define AFE_CONN61_1 0x34c8 +#define AFE_CONN61_2 0x34cc +#define AFE_CONN61_3 0x34d0 +#define AFE_CONN61_4 0x34d4 +#define AFE_CONN62 0x34d8 +#define AFE_CONN62_1 0x34dc +#define AFE_CONN62_2 0x34e0 +#define AFE_CONN62_3 0x34e4 +#define AFE_CONN62_4 0x34e8 +#define AFE_CONN63 0x34ec +#define AFE_CONN63_1 0x34f0 +#define AFE_CONN63_2 0x34f4 +#define AFE_CONN63_3 0x34f8 +#define AFE_CONN63_4 0x34fc +#define AFE_CONN64 0x3500 +#define AFE_CONN64_1 0x3504 +#define AFE_CONN64_2 0x3508 +#define AFE_CONN64_3 0x350c +#define AFE_CONN64_4 0x3510 +#define AFE_CONN65 0x3514 +#define AFE_CONN65_1 0x3518 +#define AFE_CONN65_2 0x351c +#define AFE_CONN65_3 0x3520 +#define AFE_CONN65_4 0x3524 +#define AFE_CONN66 0x3528 +#define AFE_CONN66_1 0x352c +#define AFE_CONN66_2 0x3530 +#define AFE_CONN66_3 0x3534 +#define AFE_CONN66_4 0x3538 +#define AFE_CONN67 0x353c +#define AFE_CONN67_1 0x3540 +#define AFE_CONN67_2 0x3544 +#define AFE_CONN67_3 0x3548 +#define AFE_CONN67_4 0x354c +#define AFE_CONN68 0x3550 +#define AFE_CONN68_1 0x3554 +#define AFE_CONN68_2 0x3558 +#define AFE_CONN68_3 0x355c +#define AFE_CONN68_4 0x3560 +#define AFE_CONN69 0x3564 +#define AFE_CONN69_1 0x3568 +#define AFE_CONN69_2 0x356c +#define AFE_CONN69_3 0x3570 +#define AFE_CONN69_4 0x3574 +#define AFE_CONN70 0x3578 +#define AFE_CONN70_1 0x357c +#define AFE_CONN70_2 0x3580 +#define AFE_CONN70_3 0x3584 +#define AFE_CONN70_4 0x3588 +#define AFE_CONN71 0x358c +#define AFE_CONN71_1 0x3590 +#define AFE_CONN71_2 0x3594 +#define AFE_CONN71_3 0x3598 +#define AFE_CONN71_4 0x359c +#define AFE_CONN72 0x35a0 +#define AFE_CONN72_1 0x35a4 +#define AFE_CONN72_2 0x35a8 +#define AFE_CONN72_3 0x35ac +#define AFE_CONN72_4 0x35b0 +#define AFE_CONN73 0x35b4 +#define AFE_CONN73_1 0x35b8 +#define AFE_CONN73_2 0x35bc +#define AFE_CONN73_3 0x35c0 +#define AFE_CONN73_4 0x35c4 +#define AFE_CONN74 0x35c8 +#define AFE_CONN74_1 0x35cc +#define AFE_CONN74_2 0x35d0 +#define AFE_CONN74_3 0x35d4 +#define AFE_CONN74_4 0x35d8 +#define AFE_CONN75 0x35dc +#define AFE_CONN75_1 0x35e0 +#define AFE_CONN75_2 0x35e4 +#define AFE_CONN75_3 0x35e8 +#define AFE_CONN75_4 0x35ec +#define AFE_CONN76 0x35f0 +#define AFE_CONN76_1 0x35f4 +#define AFE_CONN76_2 0x35f8 +#define AFE_CONN76_3 0x35fc +#define AFE_CONN76_4 0x3600 +#define AFE_CONN77 0x3604 +#define AFE_CONN77_1 0x3608 +#define AFE_CONN77_2 0x360c +#define AFE_CONN77_3 0x3610 +#define AFE_CONN77_4 0x3614 +#define AFE_CONN78 0x3618 +#define AFE_CONN78_1 0x361c +#define AFE_CONN78_2 0x3620 +#define AFE_CONN78_3 0x3624 +#define AFE_CONN78_4 0x3628 +#define AFE_CONN79 0x362c +#define AFE_CONN79_1 0x3630 +#define AFE_CONN79_2 0x3634 +#define AFE_CONN79_3 0x3638 +#define AFE_CONN79_4 0x363c +#define AFE_CONN80 0x3640 +#define AFE_CONN80_1 0x3644 +#define AFE_CONN80_2 0x3648 +#define AFE_CONN80_3 0x364c +#define AFE_CONN80_4 0x3650 +#define AFE_CONN81 0x3654 +#define AFE_CONN81_1 0x3658 +#define AFE_CONN81_2 0x365c +#define AFE_CONN81_3 0x3660 +#define AFE_CONN81_4 0x3664 +#define AFE_CONN82 0x3668 +#define AFE_CONN82_1 0x366c +#define AFE_CONN82_2 0x3670 +#define AFE_CONN82_3 0x3674 +#define AFE_CONN82_4 0x3678 +#define AFE_CONN83 0x367c +#define AFE_CONN83_1 0x3680 +#define AFE_CONN83_2 0x3684 +#define AFE_CONN83_3 0x3688 +#define AFE_CONN83_4 0x368c +#define AFE_CONN84 0x3690 +#define AFE_CONN84_1 0x3694 +#define AFE_CONN84_2 0x3698 +#define AFE_CONN84_3 0x369c +#define AFE_CONN84_4 0x36a0 +#define AFE_CONN85 0x36a4 +#define AFE_CONN85_1 0x36a8 +#define AFE_CONN85_2 0x36ac +#define AFE_CONN85_3 0x36b0 +#define AFE_CONN85_4 0x36b4 +#define AFE_CONN86 0x36b8 +#define AFE_CONN86_1 0x36bc +#define AFE_CONN86_2 0x36c0 +#define AFE_CONN86_3 0x36c4 +#define AFE_CONN86_4 0x36c8 +#define AFE_CONN87 0x36cc +#define AFE_CONN87_1 0x36d0 +#define AFE_CONN87_2 0x36d4 +#define AFE_CONN87_3 0x36d8 +#define AFE_CONN87_4 0x36dc +#define AFE_CONN88 0x36e0 +#define AFE_CONN88_1 0x36e4 +#define AFE_CONN88_2 0x36e8 +#define AFE_CONN88_3 0x36ec +#define AFE_CONN88_4 0x36f0 +#define AFE_CONN89 0x36f4 +#define AFE_CONN89_1 0x36f8 +#define AFE_CONN89_2 0x36fc +#define AFE_CONN89_3 0x3700 +#define AFE_CONN89_4 0x3704 +#define AFE_CONN90 0x3708 +#define AFE_CONN90_1 0x370c +#define AFE_CONN90_2 0x3710 +#define AFE_CONN90_3 0x3714 +#define AFE_CONN90_4 0x3718 +#define AFE_CONN91 0x371c +#define AFE_CONN91_1 0x3720 +#define AFE_CONN91_2 0x3724 +#define AFE_CONN91_3 0x3728 +#define AFE_CONN91_4 0x372c +#define AFE_CONN92 0x3730 +#define AFE_CONN92_1 0x3734 +#define AFE_CONN92_2 0x3738 +#define AFE_CONN92_3 0x373c +#define AFE_CONN92_4 0x3740 +#define AFE_CONN93 0x3744 +#define AFE_CONN93_1 0x3748 +#define AFE_CONN93_2 0x374c +#define AFE_CONN93_3 0x3750 +#define AFE_CONN93_4 0x3754 +#define AFE_CONN94 0x3758 +#define AFE_CONN94_1 0x375c +#define AFE_CONN94_2 0x3760 +#define AFE_CONN94_3 0x3764 +#define AFE_CONN94_4 0x3768 +#define AFE_CONN95 0x376c +#define AFE_CONN95_1 0x3770 +#define AFE_CONN95_2 0x3774 +#define AFE_CONN95_3 0x3778 +#define AFE_CONN95_4 0x377c +#define AFE_CONN96 0x3780 +#define AFE_CONN96_1 0x3784 +#define AFE_CONN96_2 0x3788 +#define AFE_CONN96_3 0x378c +#define AFE_CONN96_4 0x3790 +#define AFE_CONN97 0x3794 +#define AFE_CONN97_1 0x3798 +#define AFE_CONN97_2 0x379c +#define AFE_CONN97_3 0x37a0 +#define AFE_CONN97_4 0x37a4 +#define AFE_CONN98 0x37a8 +#define AFE_CONN98_1 0x37ac +#define AFE_CONN98_2 0x37b0 +#define AFE_CONN98_3 0x37b4 +#define AFE_CONN98_4 0x37b8 +#define AFE_CONN99 0x37bc +#define AFE_CONN99_1 0x37c0 +#define AFE_CONN99_2 0x37c4 +#define AFE_CONN99_3 0x37c8 +#define AFE_CONN99_4 0x37cc +#define AFE_CONN100 0x37d0 +#define AFE_CONN100_1 0x37d4 +#define AFE_CONN100_2 0x37d8 +#define AFE_CONN100_3 0x37dc +#define AFE_CONN100_4 0x37e0 +#define AFE_CONN101 0x37e4 +#define AFE_CONN101_1 0x37e8 +#define AFE_CONN101_2 0x37ec +#define AFE_CONN101_3 0x37f0 +#define AFE_CONN101_4 0x37f4 +#define AFE_CONN102 0x37f8 +#define AFE_CONN102_1 0x37fc +#define AFE_CONN102_2 0x3800 +#define AFE_CONN102_3 0x3804 +#define AFE_CONN102_4 0x3808 +#define AFE_CONN103 0x380c +#define AFE_CONN103_1 0x3810 +#define AFE_CONN103_2 0x3814 +#define AFE_CONN103_3 0x3818 +#define AFE_CONN103_4 0x381c +#define AFE_CONN104 0x3820 +#define AFE_CONN104_1 0x3824 +#define AFE_CONN104_2 0x3828 +#define AFE_CONN104_3 0x382c +#define AFE_CONN104_4 0x3830 +#define AFE_CONN105 0x3834 +#define AFE_CONN105_1 0x3838 +#define AFE_CONN105_2 0x383c +#define AFE_CONN105_3 0x3840 +#define AFE_CONN105_4 0x3844 +#define AFE_CONN106 0x3848 +#define AFE_CONN106_1 0x384c +#define AFE_CONN106_2 0x3850 +#define AFE_CONN106_3 0x3854 +#define AFE_CONN106_4 0x3858 +#define AFE_CONN107 0x385c +#define AFE_CONN107_1 0x3860 +#define AFE_CONN107_2 0x3864 +#define AFE_CONN107_3 0x3868 +#define AFE_CONN107_4 0x386c +#define AFE_CONN108 0x3870 +#define AFE_CONN108_1 0x3874 +#define AFE_CONN108_2 0x3878 +#define AFE_CONN108_3 0x387c +#define AFE_CONN108_4 0x3880 +#define AFE_CONN109 0x3884 +#define AFE_CONN109_1 0x3888 +#define AFE_CONN109_2 0x388c +#define AFE_CONN109_3 0x3890 +#define AFE_CONN109_4 0x3894 +#define AFE_CONN110 0x3898 +#define AFE_CONN110_1 0x389c +#define AFE_CONN110_2 0x38a0 +#define AFE_CONN110_3 0x38a4 +#define AFE_CONN110_4 0x38a8 +#define AFE_CONN111 0x38ac +#define AFE_CONN111_1 0x38b0 +#define AFE_CONN111_2 0x38b4 +#define AFE_CONN111_3 0x38b8 +#define AFE_CONN111_4 0x38bc +#define AFE_CONN112 0x38c0 +#define AFE_CONN112_1 0x38c4 +#define AFE_CONN112_2 0x38c8 +#define AFE_CONN112_3 0x38cc +#define AFE_CONN112_4 0x38d0 +#define AFE_CONN113 0x38d4 +#define AFE_CONN113_1 0x38d8 +#define AFE_CONN113_2 0x38dc +#define AFE_CONN113_3 0x38e0 +#define AFE_CONN113_4 0x38e4 +#define AFE_CONN114 0x38e8 +#define AFE_CONN114_1 0x38ec +#define AFE_CONN114_2 0x38f0 +#define AFE_CONN114_3 0x38f4 +#define AFE_CONN114_4 0x38f8 +#define AFE_CONN115 0x38fc +#define AFE_CONN115_1 0x3900 +#define AFE_CONN115_2 0x3904 +#define AFE_CONN115_3 0x3908 +#define AFE_CONN115_4 0x390c +#define AFE_CONN116 0x3910 +#define AFE_CONN116_1 0x3914 +#define AFE_CONN116_2 0x3918 +#define AFE_CONN116_3 0x391c +#define AFE_CONN116_4 0x3920 +#define AFE_CONN117 0x3924 +#define AFE_CONN117_1 0x3928 +#define AFE_CONN117_2 0x392c +#define AFE_CONN117_3 0x3930 +#define AFE_CONN117_4 0x3934 +#define AFE_CONN118 0x3938 +#define AFE_CONN118_1 0x393c +#define AFE_CONN118_2 0x3940 +#define AFE_CONN118_3 0x3944 +#define AFE_CONN118_4 0x3948 +#define AFE_CONN119 0x394c +#define AFE_CONN119_1 0x3950 +#define AFE_CONN119_2 0x3954 +#define AFE_CONN119_3 0x3958 +#define AFE_CONN119_4 0x395c +#define AFE_CONN120 0x3960 +#define AFE_CONN120_1 0x3964 +#define AFE_CONN120_2 0x3968 +#define AFE_CONN120_3 0x396c +#define AFE_CONN120_4 0x3970 +#define AFE_CONN121 0x3974 +#define AFE_CONN121_1 0x3978 +#define AFE_CONN121_2 0x397c +#define AFE_CONN121_3 0x3980 +#define AFE_CONN121_4 0x3984 +#define AFE_CONN122 0x3988 +#define AFE_CONN122_1 0x398c +#define AFE_CONN122_2 0x3990 +#define AFE_CONN122_3 0x3994 +#define AFE_CONN122_4 0x3998 +#define AFE_CONN123 0x399c +#define AFE_CONN123_1 0x39a0 +#define AFE_CONN123_2 0x39a4 +#define AFE_CONN123_3 0x39a8 +#define AFE_CONN123_4 0x39ac +#define AFE_CONN124 0x39b0 +#define AFE_CONN124_1 0x39b4 +#define AFE_CONN124_2 0x39b8 +#define AFE_CONN124_3 0x39bc +#define AFE_CONN124_4 0x39c0 +#define AFE_CONN125 0x39c4 +#define AFE_CONN125_1 0x39c8 +#define AFE_CONN125_2 0x39cc +#define AFE_CONN125_3 0x39d0 +#define AFE_CONN125_4 0x39d4 +#define AFE_CONN126 0x39d8 +#define AFE_CONN126_1 0x39dc +#define AFE_CONN126_2 0x39e0 +#define AFE_CONN126_3 0x39e4 +#define AFE_CONN126_4 0x39e8 +#define AFE_CONN127 0x39ec +#define AFE_CONN127_1 0x39f0 +#define AFE_CONN127_2 0x39f4 +#define AFE_CONN127_3 0x39f8 +#define AFE_CONN127_4 0x39fc +#define AFE_CONN128 0x3a00 +#define AFE_CONN128_1 0x3a04 +#define AFE_CONN128_2 0x3a08 +#define AFE_CONN128_3 0x3a0c +#define AFE_CONN128_4 0x3a10 +#define AFE_CONN129 0x3a14 +#define AFE_CONN129_1 0x3a18 +#define AFE_CONN129_2 0x3a1c +#define AFE_CONN129_3 0x3a20 +#define AFE_CONN129_4 0x3a24 +#define AFE_CONN130 0x3a28 +#define AFE_CONN130_1 0x3a2c +#define AFE_CONN130_2 0x3a30 +#define AFE_CONN130_3 0x3a34 +#define AFE_CONN130_4 0x3a38 +#define AFE_CONN131 0x3a3c +#define AFE_CONN131_1 0x3a40 +#define AFE_CONN131_2 0x3a44 +#define AFE_CONN131_3 0x3a48 +#define AFE_CONN131_4 0x3a4c +#define AFE_CONN132 0x3a50 +#define AFE_CONN132_1 0x3a54 +#define AFE_CONN132_2 0x3a58 +#define AFE_CONN132_3 0x3a5c +#define AFE_CONN132_4 0x3a60 +#define AFE_CONN133 0x3a64 +#define AFE_CONN133_1 0x3a68 +#define AFE_CONN133_2 0x3a6c +#define AFE_CONN133_3 0x3a70 +#define AFE_CONN133_4 0x3a74 +#define AFE_CONN134 0x3a78 +#define AFE_CONN134_1 0x3a7c +#define AFE_CONN134_2 0x3a80 +#define AFE_CONN134_3 0x3a84 +#define AFE_CONN134_4 0x3a88 +#define AFE_CONN135 0x3a8c +#define AFE_CONN135_1 0x3a90 +#define AFE_CONN135_2 0x3a94 +#define AFE_CONN135_3 0x3a98 +#define AFE_CONN135_4 0x3a9c +#define AFE_CONN136 0x3aa0 +#define AFE_CONN136_1 0x3aa4 +#define AFE_CONN136_2 0x3aa8 +#define AFE_CONN136_3 0x3aac +#define AFE_CONN136_4 0x3ab0 +#define AFE_CONN137 0x3ab4 +#define AFE_CONN137_1 0x3ab8 +#define AFE_CONN137_2 0x3abc +#define AFE_CONN137_3 0x3ac0 +#define AFE_CONN137_4 0x3ac4 +#define AFE_CONN138 0x3ac8 +#define AFE_CONN138_1 0x3acc +#define AFE_CONN138_2 0x3ad0 +#define AFE_CONN138_3 0x3ad4 +#define AFE_CONN138_4 0x3ad8 +#define AFE_CONN139 0x3adc +#define AFE_CONN139_1 0x3ae0 +#define AFE_CONN139_2 0x3ae4 +#define AFE_CONN139_3 0x3ae8 +#define AFE_CONN139_4 0x3aec +#define AFE_CONN_RS 0x3af0 +#define AFE_CONN_RS_1 0x3af4 +#define AFE_CONN_RS_2 0x3af8 +#define AFE_CONN_RS_3 0x3afc +#define AFE_CONN_RS_4 0x3b00 +#define AFE_CONN_16BIT 0x3b04 +#define AFE_CONN_16BIT_1 0x3b08 +#define AFE_CONN_16BIT_2 0x3b0c +#define AFE_CONN_16BIT_3 0x3b10 +#define AFE_CONN_16BIT_4 0x3b14 +#define AFE_CONN_24BIT 0x3b18 +#define AFE_CONN_24BIT_1 0x3b1c +#define AFE_CONN_24BIT_2 0x3b20 +#define AFE_CONN_24BIT_3 0x3b24 +#define AFE_CONN_24BIT_4 0x3b28 +#define AFE_CONN_DI 0x3b2c +#define AFE_CONN_DI_1 0x3b30 +#define AFE_CONN_DI_2 0x3b34 +#define AFE_CONN_DI_3 0x3b38 +#define AFE_CONN_DI_4 0x3b3c +#define AFE_CONN176 0x3ea0 +#define AFE_CONN176_1 0x3ea4 +#define AFE_CONN176_2 0x3ea8 +#define AFE_CONN176_3 0x3eac +#define AFE_CONN176_4 0x3eb0 +#define AFE_CONN176_5 0x3eb4 +#define AFE_CONN177 0x3eb8 +#define AFE_CONN177_1 0x3ebc +#define AFE_CONN177_2 0x3ec0 +#define AFE_CONN177_3 0x3ec4 +#define AFE_CONN177_4 0x3ec8 +#define AFE_CONN177_5 0x3ecc +#define AFE_CONN182 0x3f30 +#define AFE_CONN182_1 0x3f34 +#define AFE_CONN182_2 0x3f38 +#define AFE_CONN182_3 0x3f3c +#define AFE_CONN182_4 0x3f40 +#define AFE_CONN182_5 0x3f44 +#define AFE_CONN183 0x3f48 +#define AFE_CONN183_1 0x3f4c +#define AFE_CONN183_2 0x3f50 +#define AFE_CONN183_3 0x3f54 +#define AFE_CONN183_4 0x3f58 +#define AFE_CONN183_5 0x3f5c +#define AFE_SECURE_MASK_CONN0 0x4000 +#define AFE_SECURE_MASK_CONN0_1 0x4004 +#define AFE_SECURE_MASK_CONN0_2 0x4008 +#define AFE_SECURE_MASK_CONN0_3 0x400c +#define AFE_SECURE_MASK_CONN0_4 0x4010 +#define AFE_SECURE_MASK_CONN1 0x4014 +#define AFE_SECURE_MASK_CONN1_1 0x4018 +#define AFE_SECURE_MASK_CONN1_2 0x401c +#define AFE_SECURE_MASK_CONN1_3 0x4020 +#define AFE_SECURE_MASK_CONN1_4 0x4024 +#define AFE_SECURE_MASK_CONN2 0x4028 +#define AFE_SECURE_MASK_CONN2_1 0x402c +#define AFE_SECURE_MASK_CONN2_2 0x4030 +#define AFE_SECURE_MASK_CONN2_3 0x4034 +#define AFE_SECURE_MASK_CONN2_4 0x4038 +#define AFE_SECURE_MASK_CONN3 0x403c +#define AFE_SECURE_MASK_CONN3_1 0x4040 +#define AFE_SECURE_MASK_CONN3_2 0x4044 +#define AFE_SECURE_MASK_CONN3_3 0x4048 +#define AFE_SECURE_MASK_CONN3_4 0x404c +#define AFE_SECURE_MASK_CONN4 0x4050 +#define AFE_SECURE_MASK_CONN4_1 0x4054 +#define AFE_SECURE_MASK_CONN4_2 0x4058 +#define AFE_SECURE_MASK_CONN4_3 0x405c +#define AFE_SECURE_MASK_CONN4_4 0x4060 +#define AFE_SECURE_MASK_CONN5 0x4064 +#define AFE_SECURE_MASK_CONN5_1 0x4068 +#define AFE_SECURE_MASK_CONN5_2 0x406c +#define AFE_SECURE_MASK_CONN5_3 0x4070 +#define AFE_SECURE_MASK_CONN5_4 0x4074 +#define AFE_SECURE_MASK_CONN6 0x4078 +#define AFE_SECURE_MASK_CONN6_1 0x407c +#define AFE_SECURE_MASK_CONN6_2 0x4080 +#define AFE_SECURE_MASK_CONN6_3 0x4084 +#define AFE_SECURE_MASK_CONN6_4 0x4088 +#define AFE_SECURE_MASK_CONN7 0x408c +#define AFE_SECURE_MASK_CONN7_1 0x4090 +#define AFE_SECURE_MASK_CONN7_2 0x4094 +#define AFE_SECURE_MASK_CONN7_3 0x4098 +#define AFE_SECURE_MASK_CONN7_4 0x409c +#define AFE_SECURE_MASK_CONN8 0x40a0 +#define AFE_SECURE_MASK_CONN8_1 0x40a4 +#define AFE_SECURE_MASK_CONN8_2 0x40a8 +#define AFE_SECURE_MASK_CONN8_3 0x40ac +#define AFE_SECURE_MASK_CONN8_4 0x40b0 +#define AFE_SECURE_MASK_CONN9 0x40b4 +#define AFE_SECURE_MASK_CONN9_1 0x40b8 +#define AFE_SECURE_MASK_CONN9_2 0x40bc +#define AFE_SECURE_MASK_CONN9_3 0x40c0 +#define AFE_SECURE_MASK_CONN9_4 0x40c4 +#define AFE_SECURE_MASK_CONN10 0x40c8 +#define AFE_SECURE_MASK_CONN10_1 0x40cc +#define AFE_SECURE_MASK_CONN10_2 0x40d0 +#define AFE_SECURE_MASK_CONN10_3 0x40d4 +#define AFE_SECURE_MASK_CONN10_4 0x40d8 +#define AFE_SECURE_MASK_CONN11 0x40dc +#define AFE_SECURE_MASK_CONN11_1 0x40e0 +#define AFE_SECURE_MASK_CONN11_2 0x40e4 +#define AFE_SECURE_MASK_CONN11_3 0x40e8 +#define AFE_SECURE_MASK_CONN11_4 0x40ec +#define AFE_SECURE_MASK_CONN12 0x40f0 +#define AFE_SECURE_MASK_CONN12_1 0x40f4 +#define AFE_SECURE_MASK_CONN12_2 0x40f8 +#define AFE_SECURE_MASK_CONN12_3 0x40fc +#define AFE_SECURE_MASK_CONN12_4 0x4100 +#define AFE_SECURE_MASK_CONN13 0x4104 +#define AFE_SECURE_MASK_CONN13_1 0x4108 +#define AFE_SECURE_MASK_CONN13_2 0x410c +#define AFE_SECURE_MASK_CONN13_3 0x4110 +#define AFE_SECURE_MASK_CONN13_4 0x4114 +#define AFE_SECURE_MASK_CONN14 0x4118 +#define AFE_SECURE_MASK_CONN14_1 0x411c +#define AFE_SECURE_MASK_CONN14_2 0x4120 +#define AFE_SECURE_MASK_CONN14_3 0x4124 +#define AFE_SECURE_MASK_CONN14_4 0x4128 +#define AFE_SECURE_MASK_CONN15 0x412c +#define AFE_SECURE_MASK_CONN15_1 0x4130 +#define AFE_SECURE_MASK_CONN15_2 0x4134 +#define AFE_SECURE_MASK_CONN15_3 0x4138 +#define AFE_SECURE_MASK_CONN15_4 0x413c +#define AFE_SECURE_MASK_CONN16 0x4140 +#define AFE_SECURE_MASK_CONN16_1 0x4144 +#define AFE_SECURE_MASK_CONN16_2 0x4148 +#define AFE_SECURE_MASK_CONN16_3 0x414c +#define AFE_SECURE_MASK_CONN16_4 0x4150 +#define AFE_SECURE_MASK_CONN17 0x4154 +#define AFE_SECURE_MASK_CONN17_1 0x4158 +#define AFE_SECURE_MASK_CONN17_2 0x415c +#define AFE_SECURE_MASK_CONN17_3 0x4160 +#define AFE_SECURE_MASK_CONN17_4 0x4164 +#define AFE_SECURE_MASK_CONN18 0x4168 +#define AFE_SECURE_MASK_CONN18_1 0x416c +#define AFE_SECURE_MASK_CONN18_2 0x4170 +#define AFE_SECURE_MASK_CONN18_3 0x4174 +#define AFE_SECURE_MASK_CONN18_4 0x4178 +#define AFE_SECURE_MASK_CONN19 0x417c +#define AFE_SECURE_MASK_CONN19_1 0x4180 +#define AFE_SECURE_MASK_CONN19_2 0x4184 +#define AFE_SECURE_MASK_CONN19_3 0x4188 +#define AFE_SECURE_MASK_CONN19_4 0x418c +#define AFE_SECURE_MASK_CONN20 0x4190 +#define AFE_SECURE_MASK_CONN20_1 0x4194 +#define AFE_SECURE_MASK_CONN20_2 0x4198 +#define AFE_SECURE_MASK_CONN20_3 0x419c +#define AFE_SECURE_MASK_CONN20_4 0x41a0 +#define AFE_SECURE_MASK_CONN21 0x41a4 +#define AFE_SECURE_MASK_CONN21_1 0x41a8 +#define AFE_SECURE_MASK_CONN21_2 0x41ac +#define AFE_SECURE_MASK_CONN21_3 0x41b0 +#define AFE_SECURE_MASK_CONN21_4 0x41b4 +#define AFE_SECURE_MASK_CONN22 0x41b8 +#define AFE_SECURE_MASK_CONN22_1 0x41bc +#define AFE_SECURE_MASK_CONN22_2 0x41c0 +#define AFE_SECURE_MASK_CONN22_3 0x41c4 +#define AFE_SECURE_MASK_CONN22_4 0x41c8 +#define AFE_SECURE_MASK_CONN23 0x41cc +#define AFE_SECURE_MASK_CONN23_1 0x41d0 +#define AFE_SECURE_MASK_CONN23_2 0x41d4 +#define AFE_SECURE_MASK_CONN23_3 0x41d8 +#define AFE_SECURE_MASK_CONN23_4 0x41dc +#define AFE_SECURE_MASK_CONN24 0x41e0 +#define AFE_SECURE_MASK_CONN24_1 0x41e4 +#define AFE_SECURE_MASK_CONN24_2 0x41e8 +#define AFE_SECURE_MASK_CONN24_3 0x41ec +#define AFE_SECURE_MASK_CONN24_4 0x41f0 +#define AFE_SECURE_MASK_CONN25 0x41f4 +#define AFE_SECURE_MASK_CONN25_1 0x41f8 +#define AFE_SECURE_MASK_CONN25_2 0x41fc +#define AFE_SECURE_MASK_CONN25_3 0x4200 +#define AFE_SECURE_MASK_CONN25_4 0x4204 +#define AFE_SECURE_MASK_CONN26 0x4208 +#define AFE_SECURE_MASK_CONN26_1 0x420c +#define AFE_SECURE_MASK_CONN26_2 0x4210 +#define AFE_SECURE_MASK_CONN26_3 0x4214 +#define AFE_SECURE_MASK_CONN26_4 0x4218 +#define AFE_SECURE_MASK_CONN27 0x421c +#define AFE_SECURE_MASK_CONN27_1 0x4220 +#define AFE_SECURE_MASK_CONN27_2 0x4224 +#define AFE_SECURE_MASK_CONN27_3 0x4228 +#define AFE_SECURE_MASK_CONN27_4 0x422c +#define AFE_SECURE_MASK_CONN28 0x4230 +#define AFE_SECURE_MASK_CONN28_1 0x4234 +#define AFE_SECURE_MASK_CONN28_2 0x4238 +#define AFE_SECURE_MASK_CONN28_3 0x423c +#define AFE_SECURE_MASK_CONN28_4 0x4240 +#define AFE_SECURE_MASK_CONN29 0x4244 +#define AFE_SECURE_MASK_CONN29_1 0x4248 +#define AFE_SECURE_MASK_CONN29_2 0x424c +#define AFE_SECURE_MASK_CONN29_3 0x4250 +#define AFE_SECURE_MASK_CONN29_4 0x4254 +#define AFE_SECURE_MASK_CONN30 0x4258 +#define AFE_SECURE_MASK_CONN30_1 0x425c +#define AFE_SECURE_MASK_CONN30_2 0x4260 +#define AFE_SECURE_MASK_CONN30_3 0x4264 +#define AFE_SECURE_MASK_CONN30_4 0x4268 +#define AFE_SECURE_MASK_CONN31 0x426c +#define AFE_SECURE_MASK_CONN31_1 0x4270 +#define AFE_SECURE_MASK_CONN31_2 0x4274 +#define AFE_SECURE_MASK_CONN31_3 0x4278 +#define AFE_SECURE_MASK_CONN31_4 0x427c +#define AFE_SECURE_MASK_CONN32 0x4280 +#define AFE_SECURE_MASK_CONN32_1 0x4284 +#define AFE_SECURE_MASK_CONN32_2 0x4288 +#define AFE_SECURE_MASK_CONN32_3 0x428c +#define AFE_SECURE_MASK_CONN32_4 0x4290 +#define AFE_SECURE_MASK_CONN33 0x4294 +#define AFE_SECURE_MASK_CONN33_1 0x4298 +#define AFE_SECURE_MASK_CONN33_2 0x429c +#define AFE_SECURE_MASK_CONN33_3 0x42a0 +#define AFE_SECURE_MASK_CONN33_4 0x42a4 +#define AFE_SECURE_MASK_CONN34 0x42a8 +#define AFE_SECURE_MASK_CONN34_1 0x42ac +#define AFE_SECURE_MASK_CONN34_2 0x42b0 +#define AFE_SECURE_MASK_CONN34_3 0x42b4 +#define AFE_SECURE_MASK_CONN34_4 0x42b8 +#define AFE_SECURE_MASK_CONN35 0x42bc +#define AFE_SECURE_MASK_CONN35_1 0x42c0 +#define AFE_SECURE_MASK_CONN35_2 0x42c4 +#define AFE_SECURE_MASK_CONN35_3 0x42c8 +#define AFE_SECURE_MASK_CONN35_4 0x42cc +#define AFE_SECURE_MASK_CONN36 0x42d0 +#define AFE_SECURE_MASK_CONN36_1 0x42d4 +#define AFE_SECURE_MASK_CONN36_2 0x42d8 +#define AFE_SECURE_MASK_CONN36_3 0x42dc +#define AFE_SECURE_MASK_CONN36_4 0x42e0 +#define AFE_SECURE_MASK_CONN37 0x42e4 +#define AFE_SECURE_MASK_CONN37_1 0x42e8 +#define AFE_SECURE_MASK_CONN37_2 0x42ec +#define AFE_SECURE_MASK_CONN37_3 0x42f0 +#define AFE_SECURE_MASK_CONN37_4 0x42f4 +#define AFE_SECURE_MASK_CONN38 0x42f8 +#define AFE_SECURE_MASK_CONN38_1 0x42fc +#define AFE_SECURE_MASK_CONN38_2 0x4300 +#define AFE_SECURE_MASK_CONN38_3 0x4304 +#define AFE_SECURE_MASK_CONN38_4 0x4308 +#define AFE_SECURE_MASK_CONN39 0x430c +#define AFE_SECURE_MASK_CONN39_1 0x4310 +#define AFE_SECURE_MASK_CONN39_2 0x4314 +#define AFE_SECURE_MASK_CONN39_3 0x4318 +#define AFE_SECURE_MASK_CONN39_4 0x431c +#define AFE_SECURE_MASK_CONN40 0x4320 +#define AFE_SECURE_MASK_CONN40_1 0x4324 +#define AFE_SECURE_MASK_CONN40_2 0x4328 +#define AFE_SECURE_MASK_CONN40_3 0x432c +#define AFE_SECURE_MASK_CONN40_4 0x4330 +#define AFE_SECURE_MASK_CONN41 0x4334 +#define AFE_SECURE_MASK_CONN41_1 0x4338 +#define AFE_SECURE_MASK_CONN41_2 0x433c +#define AFE_SECURE_MASK_CONN41_3 0x4340 +#define AFE_SECURE_MASK_CONN41_4 0x4344 +#define AFE_SECURE_MASK_CONN42 0x4348 +#define AFE_SECURE_MASK_CONN42_1 0x434c +#define AFE_SECURE_MASK_CONN42_2 0x4350 +#define AFE_SECURE_MASK_CONN42_3 0x4354 +#define AFE_SECURE_MASK_CONN42_4 0x4358 +#define AFE_SECURE_MASK_CONN43 0x435c +#define AFE_SECURE_MASK_CONN43_1 0x4360 +#define AFE_SECURE_MASK_CONN43_2 0x4364 +#define AFE_SECURE_MASK_CONN43_3 0x4368 +#define AFE_SECURE_MASK_CONN43_4 0x436c +#define AFE_SECURE_MASK_CONN44 0x4370 +#define AFE_SECURE_MASK_CONN44_1 0x4374 +#define AFE_SECURE_MASK_CONN44_2 0x4378 +#define AFE_SECURE_MASK_CONN44_3 0x437c +#define AFE_SECURE_MASK_CONN44_4 0x4380 +#define AFE_SECURE_MASK_CONN45 0x4384 +#define AFE_SECURE_MASK_CONN45_1 0x4388 +#define AFE_SECURE_MASK_CONN45_2 0x438c +#define AFE_SECURE_MASK_CONN45_3 0x4390 +#define AFE_SECURE_MASK_CONN45_4 0x4394 +#define AFE_SECURE_MASK_CONN46 0x4398 +#define AFE_SECURE_MASK_CONN46_1 0x439c +#define AFE_SECURE_MASK_CONN46_2 0x43a0 +#define AFE_SECURE_MASK_CONN46_3 0x43a4 +#define AFE_SECURE_MASK_CONN46_4 0x43a8 +#define AFE_SECURE_MASK_CONN47 0x43ac +#define AFE_SECURE_MASK_CONN47_1 0x43b0 +#define AFE_SECURE_MASK_CONN47_2 0x43b4 +#define AFE_SECURE_MASK_CONN47_3 0x43b8 +#define AFE_SECURE_MASK_CONN47_4 0x43bc +#define AFE_SECURE_MASK_CONN48 0x43c0 +#define AFE_SECURE_MASK_CONN48_1 0x43c4 +#define AFE_SECURE_MASK_CONN48_2 0x43c8 +#define AFE_SECURE_MASK_CONN48_3 0x43cc +#define AFE_SECURE_MASK_CONN48_4 0x43d0 +#define AFE_SECURE_MASK_CONN49 0x43d4 +#define AFE_SECURE_MASK_CONN49_1 0x43d8 +#define AFE_SECURE_MASK_CONN49_2 0x43dc +#define AFE_SECURE_MASK_CONN49_3 0x43e0 +#define AFE_SECURE_MASK_CONN49_4 0x43e4 +#define AFE_SECURE_MASK_CONN50 0x43e8 +#define AFE_SECURE_MASK_CONN50_1 0x43ec +#define AFE_SECURE_MASK_CONN50_2 0x43f0 +#define AFE_SECURE_MASK_CONN50_3 0x43f4 +#define AFE_SECURE_MASK_CONN50_4 0x43f8 +#define AFE_SECURE_MASK_CONN51 0x43fc +#define AFE_SECURE_MASK_CONN51_1 0x4400 +#define AFE_SECURE_MASK_CONN51_2 0x4404 +#define AFE_SECURE_MASK_CONN51_3 0x4408 +#define AFE_SECURE_MASK_CONN51_4 0x440c +#define AFE_SECURE_MASK_CONN52 0x4410 +#define AFE_SECURE_MASK_CONN52_1 0x4414 +#define AFE_SECURE_MASK_CONN52_2 0x4418 +#define AFE_SECURE_MASK_CONN52_3 0x441c +#define AFE_SECURE_MASK_CONN52_4 0x4420 +#define AFE_SECURE_MASK_CONN53 0x4424 +#define AFE_SECURE_MASK_CONN53_1 0x4428 +#define AFE_SECURE_MASK_CONN53_2 0x442c +#define AFE_SECURE_MASK_CONN53_3 0x4430 +#define AFE_SECURE_MASK_CONN53_4 0x4434 +#define AFE_SECURE_MASK_CONN54 0x4438 +#define AFE_SECURE_MASK_CONN54_1 0x443c +#define AFE_SECURE_MASK_CONN54_2 0x4440 +#define AFE_SECURE_MASK_CONN54_3 0x4444 +#define AFE_SECURE_MASK_CONN54_4 0x4448 +#define AFE_SECURE_MASK_CONN55 0x444c +#define AFE_SECURE_MASK_CONN55_1 0x4450 +#define AFE_SECURE_MASK_CONN55_2 0x4454 +#define AFE_SECURE_MASK_CONN55_3 0x4458 +#define AFE_SECURE_MASK_CONN55_4 0x445c +#define AFE_SECURE_MASK_CONN56 0x4460 +#define AFE_SECURE_MASK_CONN56_1 0x4464 +#define AFE_SECURE_MASK_CONN56_2 0x4468 +#define AFE_SECURE_MASK_CONN56_3 0x446c +#define AFE_SECURE_MASK_CONN56_4 0x4470 +#define AFE_SECURE_MASK_CONN57 0x4474 +#define AFE_SECURE_MASK_CONN57_1 0x4478 +#define AFE_SECURE_MASK_CONN57_2 0x447c +#define AFE_SECURE_MASK_CONN57_3 0x4480 +#define AFE_SECURE_MASK_CONN57_4 0x4484 +#define AFE_SECURE_MASK_CONN58 0x4488 +#define AFE_SECURE_MASK_CONN58_1 0x448c +#define AFE_SECURE_MASK_CONN58_2 0x4490 +#define AFE_SECURE_MASK_CONN58_3 0x4494 +#define AFE_SECURE_MASK_CONN58_4 0x4498 +#define AFE_SECURE_MASK_CONN59 0x449c +#define AFE_SECURE_MASK_CONN59_1 0x44a0 +#define AFE_SECURE_MASK_CONN59_2 0x44a4 +#define AFE_SECURE_MASK_CONN59_3 0x44a8 +#define AFE_SECURE_MASK_CONN59_4 0x44ac +#define AFE_SECURE_MASK_CONN60 0x44b0 +#define AFE_SECURE_MASK_CONN60_1 0x44b4 +#define AFE_SECURE_MASK_CONN60_2 0x44b8 +#define AFE_SECURE_MASK_CONN60_3 0x44bc +#define AFE_SECURE_MASK_CONN60_4 0x44c0 +#define AFE_SECURE_MASK_CONN61 0x44c4 +#define AFE_SECURE_MASK_CONN61_1 0x44c8 +#define AFE_SECURE_MASK_CONN61_2 0x44cc +#define AFE_SECURE_MASK_CONN61_3 0x44d0 +#define AFE_SECURE_MASK_CONN61_4 0x44d4 +#define AFE_SECURE_MASK_CONN62 0x44d8 +#define AFE_SECURE_MASK_CONN62_1 0x44dc +#define AFE_SECURE_MASK_CONN62_2 0x44e0 +#define AFE_SECURE_MASK_CONN62_3 0x44e4 +#define AFE_SECURE_MASK_CONN62_4 0x44e8 +#define AFE_SECURE_MASK_CONN63 0x44ec +#define AFE_SECURE_MASK_CONN63_1 0x44f0 +#define AFE_SECURE_MASK_CONN63_2 0x44f4 +#define AFE_SECURE_MASK_CONN63_3 0x44f8 +#define AFE_SECURE_MASK_CONN63_4 0x44fc +#define AFE_SECURE_MASK_CONN64 0x4500 +#define AFE_SECURE_MASK_CONN64_1 0x4504 +#define AFE_SECURE_MASK_CONN64_2 0x4508 +#define AFE_SECURE_MASK_CONN64_3 0x450c +#define AFE_SECURE_MASK_CONN64_4 0x4510 +#define AFE_SECURE_MASK_CONN65 0x4514 +#define AFE_SECURE_MASK_CONN65_1 0x4518 +#define AFE_SECURE_MASK_CONN65_2 0x451c +#define AFE_SECURE_MASK_CONN65_3 0x4520 +#define AFE_SECURE_MASK_CONN65_4 0x4524 +#define AFE_SECURE_MASK_CONN66 0x4528 +#define AFE_SECURE_MASK_CONN66_1 0x452c +#define AFE_SECURE_MASK_CONN66_2 0x4530 +#define AFE_SECURE_MASK_CONN66_3 0x4534 +#define AFE_SECURE_MASK_CONN66_4 0x4538 +#define AFE_SECURE_MASK_CONN67 0x453c +#define AFE_SECURE_MASK_CONN67_1 0x4540 +#define AFE_SECURE_MASK_CONN67_2 0x4544 +#define AFE_SECURE_MASK_CONN67_3 0x4548 +#define AFE_SECURE_MASK_CONN67_4 0x454c +#define AFE_SECURE_MASK_CONN68 0x4550 +#define AFE_SECURE_MASK_CONN68_1 0x4554 +#define AFE_SECURE_MASK_CONN68_2 0x4558 +#define AFE_SECURE_MASK_CONN68_3 0x455c +#define AFE_SECURE_MASK_CONN68_4 0x4560 +#define AFE_SECURE_MASK_CONN69 0x4564 +#define AFE_SECURE_MASK_CONN69_1 0x4568 +#define AFE_SECURE_MASK_CONN69_2 0x456c +#define AFE_SECURE_MASK_CONN69_3 0x4570 +#define AFE_SECURE_MASK_CONN69_4 0x4574 +#define AFE_SECURE_MASK_CONN70 0x4578 +#define AFE_SECURE_MASK_CONN70_1 0x457c +#define AFE_SECURE_MASK_CONN70_2 0x4580 +#define AFE_SECURE_MASK_CONN70_3 0x4584 +#define AFE_SECURE_MASK_CONN70_4 0x4588 +#define AFE_SECURE_MASK_CONN71 0x458c +#define AFE_SECURE_MASK_CONN71_1 0x4590 +#define AFE_SECURE_MASK_CONN71_2 0x4594 +#define AFE_SECURE_MASK_CONN71_3 0x4598 +#define AFE_SECURE_MASK_CONN71_4 0x459c +#define AFE_SECURE_MASK_CONN72 0x45a0 +#define AFE_SECURE_MASK_CONN72_1 0x45a4 +#define AFE_SECURE_MASK_CONN72_2 0x45a8 +#define AFE_SECURE_MASK_CONN72_3 0x45ac +#define AFE_SECURE_MASK_CONN72_4 0x45b0 +#define AFE_SECURE_MASK_CONN73 0x45b4 +#define AFE_SECURE_MASK_CONN73_1 0x45b8 +#define AFE_SECURE_MASK_CONN73_2 0x45bc +#define AFE_SECURE_MASK_CONN73_3 0x45c0 +#define AFE_SECURE_MASK_CONN73_4 0x45c4 +#define AFE_SECURE_MASK_CONN74 0x45c8 +#define AFE_SECURE_MASK_CONN74_1 0x45cc +#define AFE_SECURE_MASK_CONN74_2 0x45d0 +#define AFE_SECURE_MASK_CONN74_3 0x45d4 +#define AFE_SECURE_MASK_CONN74_4 0x45d8 +#define AFE_SECURE_MASK_CONN75 0x45dc +#define AFE_SECURE_MASK_CONN75_1 0x45e0 +#define AFE_SECURE_MASK_CONN75_2 0x45e4 +#define AFE_SECURE_MASK_CONN75_3 0x45e8 +#define AFE_SECURE_MASK_CONN75_4 0x45ec +#define AFE_SECURE_MASK_CONN76 0x45f0 +#define AFE_SECURE_MASK_CONN76_1 0x45f4 +#define AFE_SECURE_MASK_CONN76_2 0x45f8 +#define AFE_SECURE_MASK_CONN76_3 0x45fc +#define AFE_SECURE_MASK_CONN76_4 0x4600 +#define AFE_SECURE_MASK_CONN77 0x4604 +#define AFE_SECURE_MASK_CONN77_1 0x4608 +#define AFE_SECURE_MASK_CONN77_2 0x460c +#define AFE_SECURE_MASK_CONN77_3 0x4610 +#define AFE_SECURE_MASK_CONN77_4 0x4614 +#define AFE_SECURE_MASK_CONN78 0x4618 +#define AFE_SECURE_MASK_CONN78_1 0x461c +#define AFE_SECURE_MASK_CONN78_2 0x4620 +#define AFE_SECURE_MASK_CONN78_3 0x4624 +#define AFE_SECURE_MASK_CONN78_4 0x4628 +#define AFE_SECURE_MASK_CONN79 0x462c +#define AFE_SECURE_MASK_CONN79_1 0x4630 +#define AFE_SECURE_MASK_CONN79_2 0x4634 +#define AFE_SECURE_MASK_CONN79_3 0x4638 +#define AFE_SECURE_MASK_CONN79_4 0x463c +#define AFE_SECURE_MASK_CONN80 0x4640 +#define AFE_SECURE_MASK_CONN80_1 0x4644 +#define AFE_SECURE_MASK_CONN80_2 0x4648 +#define AFE_SECURE_MASK_CONN80_3 0x464c +#define AFE_SECURE_MASK_CONN80_4 0x4650 +#define AFE_SECURE_MASK_CONN81 0x4654 +#define AFE_SECURE_MASK_CONN81_1 0x4658 +#define AFE_SECURE_MASK_CONN81_2 0x465c +#define AFE_SECURE_MASK_CONN81_3 0x4660 +#define AFE_SECURE_MASK_CONN81_4 0x4664 +#define AFE_SECURE_MASK_CONN82 0x4668 +#define AFE_SECURE_MASK_CONN82_1 0x466c +#define AFE_SECURE_MASK_CONN82_2 0x4670 +#define AFE_SECURE_MASK_CONN82_3 0x4674 +#define AFE_SECURE_MASK_CONN82_4 0x4678 +#define AFE_SECURE_MASK_CONN83 0x467c +#define AFE_SECURE_MASK_CONN83_1 0x4680 +#define AFE_SECURE_MASK_CONN83_2 0x4684 +#define AFE_SECURE_MASK_CONN83_3 0x4688 +#define AFE_SECURE_MASK_CONN83_4 0x468c +#define AFE_SECURE_MASK_CONN84 0x4690 +#define AFE_SECURE_MASK_CONN84_1 0x4694 +#define AFE_SECURE_MASK_CONN84_2 0x4698 +#define AFE_SECURE_MASK_CONN84_3 0x469c +#define AFE_SECURE_MASK_CONN84_4 0x46a0 +#define AFE_SECURE_MASK_CONN85 0x46a4 +#define AFE_SECURE_MASK_CONN85_1 0x46a8 +#define AFE_SECURE_MASK_CONN85_2 0x46ac +#define AFE_SECURE_MASK_CONN85_3 0x46b0 +#define AFE_SECURE_MASK_CONN85_4 0x46b4 +#define AFE_SECURE_MASK_CONN86 0x46b8 +#define AFE_SECURE_MASK_CONN86_1 0x46bc +#define AFE_SECURE_MASK_CONN86_2 0x46c0 +#define AFE_SECURE_MASK_CONN86_3 0x46c4 +#define AFE_SECURE_MASK_CONN86_4 0x46c8 +#define AFE_SECURE_MASK_CONN87 0x46cc +#define AFE_SECURE_MASK_CONN87_1 0x46d0 +#define AFE_SECURE_MASK_CONN87_2 0x46d4 +#define AFE_SECURE_MASK_CONN87_3 0x46d8 +#define AFE_SECURE_MASK_CONN87_4 0x46dc +#define AFE_SECURE_MASK_CONN88 0x46e0 +#define AFE_SECURE_MASK_CONN88_1 0x46e4 +#define AFE_SECURE_MASK_CONN88_2 0x46e8 +#define AFE_SECURE_MASK_CONN88_3 0x46ec +#define AFE_SECURE_MASK_CONN88_4 0x46f0 +#define AFE_SECURE_MASK_CONN89 0x46f4 +#define AFE_SECURE_MASK_CONN89_1 0x46f8 +#define AFE_SECURE_MASK_CONN89_2 0x46fc +#define AFE_SECURE_MASK_CONN89_3 0x4700 +#define AFE_SECURE_MASK_CONN89_4 0x4704 +#define AFE_SECURE_MASK_CONN90 0x4708 +#define AFE_SECURE_MASK_CONN90_1 0x470c +#define AFE_SECURE_MASK_CONN90_2 0x4710 +#define AFE_SECURE_MASK_CONN90_3 0x4714 +#define AFE_SECURE_MASK_CONN90_4 0x4718 +#define AFE_SECURE_MASK_CONN91 0x471c +#define AFE_SECURE_MASK_CONN91_1 0x4720 +#define AFE_SECURE_MASK_CONN91_2 0x4724 +#define AFE_SECURE_MASK_CONN91_3 0x4728 +#define AFE_SECURE_MASK_CONN91_4 0x472c +#define AFE_SECURE_MASK_CONN92 0x4730 +#define AFE_SECURE_MASK_CONN92_1 0x4734 +#define AFE_SECURE_MASK_CONN92_2 0x4738 +#define AFE_SECURE_MASK_CONN92_3 0x473c +#define AFE_SECURE_MASK_CONN92_4 0x4740 +#define AFE_SECURE_MASK_CONN93 0x4744 +#define AFE_SECURE_MASK_CONN93_1 0x4748 +#define AFE_SECURE_MASK_CONN93_2 0x474c +#define AFE_SECURE_MASK_CONN93_3 0x4750 +#define AFE_SECURE_MASK_CONN93_4 0x4754 +#define AFE_SECURE_MASK_CONN94 0x4758 +#define AFE_SECURE_MASK_CONN94_1 0x475c +#define AFE_SECURE_MASK_CONN94_2 0x4760 +#define AFE_SECURE_MASK_CONN94_3 0x4764 +#define AFE_SECURE_MASK_CONN94_4 0x4768 +#define AFE_SECURE_MASK_CONN95 0x476c +#define AFE_SECURE_MASK_CONN95_1 0x4770 +#define AFE_SECURE_MASK_CONN95_2 0x4774 +#define AFE_SECURE_MASK_CONN95_3 0x4778 +#define AFE_SECURE_MASK_CONN95_4 0x477c +#define AFE_SECURE_MASK_CONN96 0x4780 +#define AFE_SECURE_MASK_CONN96_1 0x4784 +#define AFE_SECURE_MASK_CONN96_2 0x4788 +#define AFE_SECURE_MASK_CONN96_3 0x478c +#define AFE_SECURE_MASK_CONN96_4 0x4790 +#define AFE_SECURE_MASK_CONN97 0x4794 +#define AFE_SECURE_MASK_CONN97_1 0x4798 +#define AFE_SECURE_MASK_CONN97_2 0x479c +#define AFE_SECURE_MASK_CONN97_3 0x47a0 +#define AFE_SECURE_MASK_CONN97_4 0x47a4 +#define AFE_SECURE_MASK_CONN98 0x47a8 +#define AFE_SECURE_MASK_CONN98_1 0x47ac +#define AFE_SECURE_MASK_CONN98_2 0x47b0 +#define AFE_SECURE_MASK_CONN98_3 0x47b4 +#define AFE_SECURE_MASK_CONN98_4 0x47b8 +#define AFE_SECURE_MASK_CONN99 0x47bc +#define AFE_SECURE_MASK_CONN99_1 0x47c0 +#define AFE_SECURE_MASK_CONN99_2 0x47c4 +#define AFE_SECURE_MASK_CONN99_3 0x47c8 +#define AFE_SECURE_MASK_CONN99_4 0x47cc +#define AFE_SECURE_MASK_CONN100 0x47d0 +#define AFE_SECURE_MASK_CONN100_1 0x47d4 +#define AFE_SECURE_MASK_CONN100_2 0x47d8 +#define AFE_SECURE_MASK_CONN100_3 0x47dc +#define AFE_SECURE_MASK_CONN100_4 0x47e0 +#define AFE_SECURE_MASK_CONN101 0x47e4 +#define AFE_SECURE_MASK_CONN101_1 0x47e8 +#define AFE_SECURE_MASK_CONN101_2 0x47ec +#define AFE_SECURE_MASK_CONN101_3 0x47f0 +#define AFE_SECURE_MASK_CONN101_4 0x47f4 +#define AFE_SECURE_MASK_CONN102 0x47f8 +#define AFE_SECURE_MASK_CONN102_1 0x47fc +#define AFE_SECURE_MASK_CONN102_2 0x4800 +#define AFE_SECURE_MASK_CONN102_3 0x4804 +#define AFE_SECURE_MASK_CONN102_4 0x4808 +#define AFE_SECURE_MASK_CONN103 0x480c +#define AFE_SECURE_MASK_CONN103_1 0x4810 +#define AFE_SECURE_MASK_CONN103_2 0x4814 +#define AFE_SECURE_MASK_CONN103_3 0x4818 +#define AFE_SECURE_MASK_CONN103_4 0x481c +#define AFE_SECURE_MASK_CONN104 0x4820 +#define AFE_SECURE_MASK_CONN104_1 0x4824 +#define AFE_SECURE_MASK_CONN104_2 0x4828 +#define AFE_SECURE_MASK_CONN104_3 0x482c +#define AFE_SECURE_MASK_CONN104_4 0x4830 +#define AFE_SECURE_MASK_CONN105 0x4834 +#define AFE_SECURE_MASK_CONN105_1 0x4838 +#define AFE_SECURE_MASK_CONN105_2 0x483c +#define AFE_SECURE_MASK_CONN105_3 0x4840 +#define AFE_SECURE_MASK_CONN105_4 0x4844 +#define AFE_SECURE_MASK_CONN106 0x4848 +#define AFE_SECURE_MASK_CONN106_1 0x484c +#define AFE_SECURE_MASK_CONN106_2 0x4850 +#define AFE_SECURE_MASK_CONN106_3 0x4854 +#define AFE_SECURE_MASK_CONN106_4 0x4858 +#define AFE_SECURE_MASK_CONN107 0x485c +#define AFE_SECURE_MASK_CONN107_1 0x4860 +#define AFE_SECURE_MASK_CONN107_2 0x4864 +#define AFE_SECURE_MASK_CONN107_3 0x4868 +#define AFE_SECURE_MASK_CONN107_4 0x486c +#define AFE_SECURE_MASK_CONN108 0x4870 +#define AFE_SECURE_MASK_CONN108_1 0x4874 +#define AFE_SECURE_MASK_CONN108_2 0x4878 +#define AFE_SECURE_MASK_CONN108_3 0x487c +#define AFE_SECURE_MASK_CONN108_4 0x4880 +#define AFE_SECURE_MASK_CONN109 0x4884 +#define AFE_SECURE_MASK_CONN109_1 0x4888 +#define AFE_SECURE_MASK_CONN109_2 0x488c +#define AFE_SECURE_MASK_CONN109_3 0x4890 +#define AFE_SECURE_MASK_CONN109_4 0x4894 +#define AFE_SECURE_MASK_CONN110 0x4898 +#define AFE_SECURE_MASK_CONN110_1 0x489c +#define AFE_SECURE_MASK_CONN110_2 0x48a0 +#define AFE_SECURE_MASK_CONN110_3 0x48a4 +#define AFE_SECURE_MASK_CONN110_4 0x48a8 +#define AFE_SECURE_MASK_CONN111 0x48ac +#define AFE_SECURE_MASK_CONN111_1 0x48b0 +#define AFE_SECURE_MASK_CONN111_2 0x48b4 +#define AFE_SECURE_MASK_CONN111_3 0x48b8 +#define AFE_SECURE_MASK_CONN111_4 0x48bc +#define AFE_SECURE_MASK_CONN112 0x48c0 +#define AFE_SECURE_MASK_CONN112_1 0x48c4 +#define AFE_SECURE_MASK_CONN112_2 0x48c8 +#define AFE_SECURE_MASK_CONN112_3 0x48cc +#define AFE_SECURE_MASK_CONN112_4 0x48d0 +#define AFE_SECURE_MASK_CONN113 0x48d4 +#define AFE_SECURE_MASK_CONN113_1 0x48d8 +#define AFE_SECURE_MASK_CONN113_2 0x48dc +#define AFE_SECURE_MASK_CONN113_3 0x48e0 +#define AFE_SECURE_MASK_CONN113_4 0x48e4 +#define AFE_SECURE_MASK_CONN114 0x48e8 +#define AFE_SECURE_MASK_CONN114_1 0x48ec +#define AFE_SECURE_MASK_CONN114_2 0x48f0 +#define AFE_SECURE_MASK_CONN114_3 0x48f4 +#define AFE_SECURE_MASK_CONN114_4 0x48f8 +#define AFE_SECURE_MASK_CONN115 0x48fc +#define AFE_SECURE_MASK_CONN115_1 0x4900 +#define AFE_SECURE_MASK_CONN115_2 0x4904 +#define AFE_SECURE_MASK_CONN115_3 0x4908 +#define AFE_SECURE_MASK_CONN115_4 0x490c +#define AFE_SECURE_MASK_CONN116 0x4910 +#define AFE_SECURE_MASK_CONN116_1 0x4914 +#define AFE_SECURE_MASK_CONN116_2 0x4918 +#define AFE_SECURE_MASK_CONN116_3 0x491c +#define AFE_SECURE_MASK_CONN116_4 0x4920 +#define AFE_SECURE_MASK_CONN117 0x4924 +#define AFE_SECURE_MASK_CONN117_1 0x4928 +#define AFE_SECURE_MASK_CONN117_2 0x492c +#define AFE_SECURE_MASK_CONN117_3 0x4930 +#define AFE_SECURE_MASK_CONN117_4 0x4934 +#define AFE_SECURE_MASK_CONN118 0x4938 +#define AFE_SECURE_MASK_CONN118_1 0x493c +#define AFE_SECURE_MASK_CONN118_2 0x4940 +#define AFE_SECURE_MASK_CONN118_3 0x4944 +#define AFE_SECURE_MASK_CONN118_4 0x4948 +#define AFE_SECURE_MASK_CONN119 0x494c +#define AFE_SECURE_MASK_CONN119_1 0x4950 +#define AFE_SECURE_MASK_CONN119_2 0x4954 +#define AFE_SECURE_MASK_CONN119_3 0x4958 +#define AFE_SECURE_MASK_CONN119_4 0x495c +#define AFE_SECURE_MASK_CONN120 0x4960 +#define AFE_SECURE_MASK_CONN120_1 0x4964 +#define AFE_SECURE_MASK_CONN120_2 0x4968 +#define AFE_SECURE_MASK_CONN120_3 0x496c +#define AFE_SECURE_MASK_CONN120_4 0x4970 +#define AFE_SECURE_MASK_CONN121 0x4974 +#define AFE_SECURE_MASK_CONN121_1 0x4978 +#define AFE_SECURE_MASK_CONN121_2 0x497c +#define AFE_SECURE_MASK_CONN121_3 0x4980 +#define AFE_SECURE_MASK_CONN121_4 0x4984 +#define AFE_SECURE_MASK_CONN122 0x4988 +#define AFE_SECURE_MASK_CONN122_1 0x498c +#define AFE_SECURE_MASK_CONN122_2 0x4990 +#define AFE_SECURE_MASK_CONN122_3 0x4994 +#define AFE_SECURE_MASK_CONN122_4 0x4998 +#define AFE_SECURE_MASK_CONN123 0x499c +#define AFE_SECURE_MASK_CONN123_1 0x49a0 +#define AFE_SECURE_MASK_CONN123_2 0x49a4 +#define AFE_SECURE_MASK_CONN123_3 0x49a8 +#define AFE_SECURE_MASK_CONN123_4 0x49ac +#define AFE_SECURE_MASK_CONN124 0x49b0 +#define AFE_SECURE_MASK_CONN124_1 0x49b4 +#define AFE_SECURE_MASK_CONN124_2 0x49b8 +#define AFE_SECURE_MASK_CONN124_3 0x49bc +#define AFE_SECURE_MASK_CONN124_4 0x49c0 +#define AFE_SECURE_MASK_CONN125 0x49c4 +#define AFE_SECURE_MASK_CONN125_1 0x49c8 +#define AFE_SECURE_MASK_CONN125_2 0x49cc +#define AFE_SECURE_MASK_CONN125_3 0x49d0 +#define AFE_SECURE_MASK_CONN125_4 0x49d4 +#define AFE_SECURE_MASK_CONN126 0x49d8 +#define AFE_SECURE_MASK_CONN126_1 0x49dc +#define AFE_SECURE_MASK_CONN126_2 0x49e0 +#define AFE_SECURE_MASK_CONN126_3 0x49e4 +#define AFE_SECURE_MASK_CONN126_4 0x49e8 +#define AFE_SECURE_MASK_CONN127 0x49ec +#define AFE_SECURE_MASK_CONN127_1 0x49f0 +#define AFE_SECURE_MASK_CONN127_2 0x49f4 +#define AFE_SECURE_MASK_CONN127_3 0x49f8 +#define AFE_SECURE_MASK_CONN127_4 0x49fc +#define AFE_SECURE_MASK_CONN128 0x4a00 +#define AFE_SECURE_MASK_CONN128_1 0x4a04 +#define AFE_SECURE_MASK_CONN128_2 0x4a08 +#define AFE_SECURE_MASK_CONN128_3 0x4a0c +#define AFE_SECURE_MASK_CONN128_4 0x4a10 +#define AFE_SECURE_MASK_CONN129 0x4a14 +#define AFE_SECURE_MASK_CONN129_1 0x4a18 +#define AFE_SECURE_MASK_CONN129_2 0x4a1c +#define AFE_SECURE_MASK_CONN129_3 0x4a20 +#define AFE_SECURE_MASK_CONN129_4 0x4a24 +#define AFE_SECURE_MASK_CONN130 0x4a28 +#define AFE_SECURE_MASK_CONN130_1 0x4a2c +#define AFE_SECURE_MASK_CONN130_2 0x4a30 +#define AFE_SECURE_MASK_CONN130_3 0x4a34 +#define AFE_SECURE_MASK_CONN130_4 0x4a38 +#define AFE_SECURE_MASK_CONN131 0x4a3c +#define AFE_SECURE_MASK_CONN131_1 0x4a40 +#define AFE_SECURE_MASK_CONN131_2 0x4a44 +#define AFE_SECURE_MASK_CONN131_3 0x4a48 +#define AFE_SECURE_MASK_CONN131_4 0x4a4c +#define AFE_SECURE_MASK_CONN132 0x4a50 +#define AFE_SECURE_MASK_CONN132_1 0x4a54 +#define AFE_SECURE_MASK_CONN132_2 0x4a58 +#define AFE_SECURE_MASK_CONN132_3 0x4a5c +#define AFE_SECURE_MASK_CONN132_4 0x4a60 +#define AFE_SECURE_MASK_CONN133 0x4a64 +#define AFE_SECURE_MASK_CONN133_1 0x4a68 +#define AFE_SECURE_MASK_CONN133_2 0x4a6c +#define AFE_SECURE_MASK_CONN133_3 0x4a70 +#define AFE_SECURE_MASK_CONN133_4 0x4a74 +#define AFE_SECURE_MASK_CONN134 0x4a78 +#define AFE_SECURE_MASK_CONN134_1 0x4a7c +#define AFE_SECURE_MASK_CONN134_2 0x4a80 +#define AFE_SECURE_MASK_CONN134_3 0x4a84 +#define AFE_SECURE_MASK_CONN134_4 0x4a88 +#define AFE_SECURE_MASK_CONN135 0x4a8c +#define AFE_SECURE_MASK_CONN135_1 0x4a90 +#define AFE_SECURE_MASK_CONN135_2 0x4a94 +#define AFE_SECURE_MASK_CONN135_3 0x4a98 +#define AFE_SECURE_MASK_CONN135_4 0x4a9c +#define AFE_SECURE_MASK_CONN136 0x4aa0 +#define AFE_SECURE_MASK_CONN136_1 0x4aa4 +#define AFE_SECURE_MASK_CONN136_2 0x4aa8 +#define AFE_SECURE_MASK_CONN136_3 0x4aac +#define AFE_SECURE_MASK_CONN136_4 0x4ab0 +#define AFE_SECURE_MASK_CONN137 0x4ab4 +#define AFE_SECURE_MASK_CONN137_1 0x4ab8 +#define AFE_SECURE_MASK_CONN137_2 0x4abc +#define AFE_SECURE_MASK_CONN137_3 0x4ac0 +#define AFE_SECURE_MASK_CONN137_4 0x4ac4 +#define AFE_SECURE_MASK_CONN138 0x4ac8 +#define AFE_SECURE_MASK_CONN138_1 0x4acc +#define AFE_SECURE_MASK_CONN138_2 0x4ad0 +#define AFE_SECURE_MASK_CONN138_3 0x4ad4 +#define AFE_SECURE_MASK_CONN138_4 0x4ad8 +#define AFE_SECURE_MASK_CONN139 0x4adc +#define AFE_SECURE_MASK_CONN139_1 0x4ae0 +#define AFE_SECURE_MASK_CONN139_2 0x4ae4 +#define AFE_SECURE_MASK_CONN139_3 0x4ae8 +#define AFE_SECURE_MASK_CONN139_4 0x4aec +#define AFE_SECURE_MASK_CONN_RS 0x4af0 +#define AFE_SECURE_MASK_CONN_RS_1 0x4af4 +#define AFE_SECURE_MASK_CONN_RS_2 0x4af8 +#define AFE_SECURE_MASK_CONN_RS_3 0x4afc +#define AFE_SECURE_MASK_CONN_RS_4 0x4b00 +#define AFE_SECURE_MASK_CONN_16BIT 0x4b04 +#define AFE_SECURE_MASK_CONN_16BIT_1 0x4b08 +#define AFE_SECURE_MASK_CONN_16BIT_2 0x4b0c +#define AFE_SECURE_MASK_CONN_16BIT_3 0x4b10 +#define AFE_SECURE_MASK_CONN_16BIT_4 0x4b14 +#define AFE_SECURE_MASK_CONN_24BIT 0x4b18 +#define AFE_SECURE_MASK_CONN_24BIT_1 0x4b1c +#define AFE_SECURE_MASK_CONN_24BIT_2 0x4b20 +#define AFE_SECURE_MASK_CONN_24BIT_3 0x4b24 +#define AFE_SECURE_MASK_CONN_24BIT_4 0x4b28 +#define AFE_GASRC0_NEW_CON0 0x4c40 +#define AFE_GASRC0_NEW_CON1 0x4c44 +#define AFE_GASRC0_NEW_CON2 0x4c48 +#define AFE_GASRC0_NEW_CON3 0x4c4c +#define AFE_GASRC0_NEW_CON4 0x4c50 +#define AFE_GASRC0_NEW_CON5 0x4c54 +#define AFE_GASRC0_NEW_CON6 0x4c58 +#define AFE_GASRC0_NEW_CON7 0x4c5c +#define AFE_GASRC0_NEW_CON8 0x4c60 +#define AFE_GASRC0_NEW_CON9 0x4c64 +#define AFE_GASRC0_NEW_CON10 0x4c68 +#define AFE_GASRC0_NEW_CON11 0x4c6c +#define AFE_GASRC0_NEW_CON12 0x4c70 +#define AFE_GASRC0_NEW_CON13 0x4c74 +#define AFE_GASRC0_NEW_CON14 0x4c78 +#define AFE_GASRC1_NEW_CON0 0x4c80 +#define AFE_GASRC1_NEW_CON1 0x4c84 +#define AFE_GASRC1_NEW_CON2 0x4c88 +#define AFE_GASRC1_NEW_CON3 0x4c8c +#define AFE_GASRC1_NEW_CON4 0x4c90 +#define AFE_GASRC1_NEW_CON5 0x4c94 +#define AFE_GASRC1_NEW_CON6 0x4c98 +#define AFE_GASRC1_NEW_CON7 0x4c9c +#define AFE_GASRC1_NEW_CON8 0x4ca0 +#define AFE_GASRC1_NEW_CON9 0x4ca4 +#define AFE_GASRC1_NEW_CON10 0x4ca8 +#define AFE_GASRC1_NEW_CON11 0x4cac +#define AFE_GASRC1_NEW_CON12 0x4cb0 +#define AFE_GASRC1_NEW_CON13 0x4cb4 +#define AFE_GASRC1_NEW_CON14 0x4cb8 +#define AFE_GASRC2_NEW_CON0 0x4cc0 +#define AFE_GASRC2_NEW_CON1 0x4cc4 +#define AFE_GASRC2_NEW_CON2 0x4cc8 +#define AFE_GASRC2_NEW_CON3 0x4ccc +#define AFE_GASRC2_NEW_CON4 0x4cd0 +#define AFE_GASRC2_NEW_CON5 0x4cd4 +#define AFE_GASRC2_NEW_CON6 0x4cd8 +#define AFE_GASRC2_NEW_CON7 0x4cdc +#define AFE_GASRC2_NEW_CON8 0x4ce0 +#define AFE_GASRC2_NEW_CON9 0x4ce4 +#define AFE_GASRC2_NEW_CON10 0x4ce8 +#define AFE_GASRC2_NEW_CON11 0x4cec +#define AFE_GASRC2_NEW_CON12 0x4cf0 +#define AFE_GASRC2_NEW_CON13 0x4cf4 +#define AFE_GASRC2_NEW_CON14 0x4cf8 +#define AFE_GASRC3_NEW_CON0 0x4d00 +#define AFE_GASRC3_NEW_CON1 0x4d04 +#define AFE_GASRC3_NEW_CON2 0x4d08 +#define AFE_GASRC3_NEW_CON3 0x4d0c +#define AFE_GASRC3_NEW_CON4 0x4d10 +#define AFE_GASRC3_NEW_CON5 0x4d14 +#define AFE_GASRC3_NEW_CON6 0x4d18 +#define AFE_GASRC3_NEW_CON7 0x4d1c +#define AFE_GASRC3_NEW_CON8 0x4d20 +#define AFE_GASRC3_NEW_CON9 0x4d24 +#define AFE_GASRC3_NEW_CON10 0x4d28 +#define AFE_GASRC3_NEW_CON11 0x4d2c +#define AFE_GASRC3_NEW_CON12 0x4d30 +#define AFE_GASRC3_NEW_CON13 0x4d34 +#define AFE_GASRC3_NEW_CON14 0x4d38 +#define AFE_GASRC4_NEW_CON0 0x4d40 +#define AFE_GASRC4_NEW_CON1 0x4d44 +#define AFE_GASRC4_NEW_CON2 0x4d48 +#define AFE_GASRC4_NEW_CON3 0x4d4c +#define AFE_GASRC4_NEW_CON4 0x4d50 +#define AFE_GASRC4_NEW_CON5 0x4d54 +#define AFE_GASRC4_NEW_CON6 0x4d58 +#define AFE_GASRC4_NEW_CON7 0x4d5c +#define AFE_GASRC4_NEW_CON8 0x4d60 +#define AFE_GASRC4_NEW_CON9 0x4d64 +#define AFE_GASRC4_NEW_CON10 0x4d68 +#define AFE_GASRC4_NEW_CON11 0x4d6c +#define AFE_GASRC4_NEW_CON12 0x4d70 +#define AFE_GASRC4_NEW_CON13 0x4d74 +#define AFE_GASRC4_NEW_CON14 0x4d78 +#define AFE_GASRC5_NEW_CON0 0x4d80 +#define AFE_GASRC5_NEW_CON1 0x4d84 +#define AFE_GASRC5_NEW_CON2 0x4d88 +#define AFE_GASRC5_NEW_CON3 0x4d8c +#define AFE_GASRC5_NEW_CON4 0x4d90 +#define AFE_GASRC5_NEW_CON5 0x4d94 +#define AFE_GASRC5_NEW_CON6 0x4d98 +#define AFE_GASRC5_NEW_CON7 0x4d9c +#define AFE_GASRC5_NEW_CON8 0x4da0 +#define AFE_GASRC5_NEW_CON9 0x4da4 +#define AFE_GASRC5_NEW_CON10 0x4da8 +#define AFE_GASRC5_NEW_CON11 0x4dac +#define AFE_GASRC5_NEW_CON12 0x4db0 +#define AFE_GASRC5_NEW_CON13 0x4db4 +#define AFE_GASRC5_NEW_CON14 0x4db8 +#define AFE_GASRC6_NEW_CON0 0x4dc0 +#define AFE_GASRC6_NEW_CON1 0x4dc4 +#define AFE_GASRC6_NEW_CON2 0x4dc8 +#define AFE_GASRC6_NEW_CON3 0x4dcc +#define AFE_GASRC6_NEW_CON4 0x4dd0 +#define AFE_GASRC6_NEW_CON5 0x4dd4 +#define AFE_GASRC6_NEW_CON6 0x4dd8 +#define AFE_GASRC6_NEW_CON7 0x4ddc +#define AFE_GASRC6_NEW_CON8 0x4de0 +#define AFE_GASRC6_NEW_CON9 0x4de4 +#define AFE_GASRC6_NEW_CON10 0x4de8 +#define AFE_GASRC6_NEW_CON11 0x4dec +#define AFE_GASRC6_NEW_CON12 0x4df0 +#define AFE_GASRC6_NEW_CON13 0x4df4 +#define AFE_GASRC6_NEW_CON14 0x4df8 +#define AFE_GASRC7_NEW_CON0 0x4e00 +#define AFE_GASRC7_NEW_CON1 0x4e04 +#define AFE_GASRC7_NEW_CON2 0x4e08 +#define AFE_GASRC7_NEW_CON3 0x4e0c +#define AFE_GASRC7_NEW_CON4 0x4e10 +#define AFE_GASRC7_NEW_CON5 0x4e14 +#define AFE_GASRC7_NEW_CON6 0x4e18 +#define AFE_GASRC7_NEW_CON7 0x4e1c +#define AFE_GASRC7_NEW_CON8 0x4e20 +#define AFE_GASRC7_NEW_CON9 0x4e24 +#define AFE_GASRC7_NEW_CON10 0x4e28 +#define AFE_GASRC7_NEW_CON11 0x4e2c +#define AFE_GASRC7_NEW_CON12 0x4e30 +#define AFE_GASRC7_NEW_CON13 0x4e34 +#define AFE_GASRC7_NEW_CON14 0x4e38 +#define AFE_GASRC8_NEW_CON0 0x4e40 +#define AFE_GASRC8_NEW_CON1 0x4e44 +#define AFE_GASRC8_NEW_CON2 0x4e48 +#define AFE_GASRC8_NEW_CON3 0x4e4c +#define AFE_GASRC8_NEW_CON4 0x4e50 +#define AFE_GASRC8_NEW_CON5 0x4e54 +#define AFE_GASRC8_NEW_CON6 0x4e58 +#define AFE_GASRC8_NEW_CON7 0x4e5c +#define AFE_GASRC8_NEW_CON8 0x4e60 +#define AFE_GASRC8_NEW_CON9 0x4e64 +#define AFE_GASRC8_NEW_CON10 0x4e68 +#define AFE_GASRC8_NEW_CON11 0x4e6c +#define AFE_GASRC8_NEW_CON12 0x4e70 +#define AFE_GASRC8_NEW_CON13 0x4e74 +#define AFE_GASRC8_NEW_CON14 0x4e78 +#define AFE_GASRC9_NEW_CON0 0x4e80 +#define AFE_GASRC9_NEW_CON1 0x4e84 +#define AFE_GASRC9_NEW_CON2 0x4e88 +#define AFE_GASRC9_NEW_CON3 0x4e8c +#define AFE_GASRC9_NEW_CON4 0x4e90 +#define AFE_GASRC9_NEW_CON5 0x4e94 +#define AFE_GASRC9_NEW_CON6 0x4e98 +#define AFE_GASRC9_NEW_CON7 0x4e9c +#define AFE_GASRC9_NEW_CON8 0x4ea0 +#define AFE_GASRC9_NEW_CON9 0x4ea4 +#define AFE_GASRC9_NEW_CON10 0x4ea8 +#define AFE_GASRC9_NEW_CON11 0x4eac +#define AFE_GASRC9_NEW_CON12 0x4eb0 +#define AFE_GASRC9_NEW_CON13 0x4eb4 +#define AFE_GASRC9_NEW_CON14 0x4eb8 +#define AFE_GASRC10_NEW_CON0 0x4ec0 +#define AFE_GASRC10_NEW_CON1 0x4ec4 +#define AFE_GASRC10_NEW_CON2 0x4ec8 +#define AFE_GASRC10_NEW_CON3 0x4ecc +#define AFE_GASRC10_NEW_CON4 0x4ed0 +#define AFE_GASRC10_NEW_CON5 0x4ed4 +#define AFE_GASRC10_NEW_CON6 0x4ed8 +#define AFE_GASRC10_NEW_CON7 0x4edc +#define AFE_GASRC10_NEW_CON8 0x4ee0 +#define AFE_GASRC10_NEW_CON9 0x4ee4 +#define AFE_GASRC10_NEW_CON10 0x4ee8 +#define AFE_GASRC10_NEW_CON11 0x4eec +#define AFE_GASRC10_NEW_CON12 0x4ef0 +#define AFE_GASRC10_NEW_CON13 0x4ef4 +#define AFE_GASRC10_NEW_CON14 0x4ef8 +#define AFE_GASRC11_NEW_CON0 0x4f00 +#define AFE_GASRC11_NEW_CON1 0x4f04 +#define AFE_GASRC11_NEW_CON2 0x4f08 +#define AFE_GASRC11_NEW_CON3 0x4f0c +#define AFE_GASRC11_NEW_CON4 0x4f10 +#define AFE_GASRC11_NEW_CON5 0x4f14 +#define AFE_GASRC11_NEW_CON6 0x4f18 +#define AFE_GASRC11_NEW_CON7 0x4f1c +#define AFE_GASRC11_NEW_CON8 0x4f20 +#define AFE_GASRC11_NEW_CON9 0x4f24 +#define AFE_GASRC11_NEW_CON10 0x4f28 +#define AFE_GASRC11_NEW_CON11 0x4f2c +#define AFE_GASRC11_NEW_CON12 0x4f30 +#define AFE_GASRC11_NEW_CON13 0x4f34 +#define AFE_GASRC11_NEW_CON14 0x4f38 +#define AFE_GASRC12_NEW_CON0 0x4f40 +#define AFE_GASRC12_NEW_CON1 0x4f44 +#define AFE_GASRC12_NEW_CON2 0x4f48 +#define AFE_GASRC12_NEW_CON3 0x4f4c +#define AFE_GASRC12_NEW_CON4 0x4f50 +#define AFE_GASRC12_NEW_CON5 0x4f54 +#define AFE_GASRC12_NEW_CON6 0x4f58 +#define AFE_GASRC12_NEW_CON7 0x4f5c +#define AFE_GASRC12_NEW_CON8 0x4f60 +#define AFE_GASRC12_NEW_CON9 0x4f64 +#define AFE_GASRC12_NEW_CON10 0x4f68 +#define AFE_GASRC12_NEW_CON11 0x4f6c +#define AFE_GASRC12_NEW_CON12 0x4f70 +#define AFE_GASRC12_NEW_CON13 0x4f74 +#define AFE_GASRC12_NEW_CON14 0x4f78 +#define AFE_GASRC13_NEW_CON0 0x4f80 +#define AFE_GASRC13_NEW_CON1 0x4f84 +#define AFE_GASRC13_NEW_CON2 0x4f88 +#define AFE_GASRC13_NEW_CON3 0x4f8c +#define AFE_GASRC13_NEW_CON4 0x4f90 +#define AFE_GASRC13_NEW_CON5 0x4f94 +#define AFE_GASRC13_NEW_CON6 0x4f98 +#define AFE_GASRC13_NEW_CON7 0x4f9c +#define AFE_GASRC13_NEW_CON8 0x4fa0 +#define AFE_GASRC13_NEW_CON9 0x4fa4 +#define AFE_GASRC13_NEW_CON10 0x4fa8 +#define AFE_GASRC13_NEW_CON11 0x4fac +#define AFE_GASRC13_NEW_CON12 0x4fb0 +#define AFE_GASRC13_NEW_CON13 0x4fb4 +#define AFE_GASRC13_NEW_CON14 0x4fb8 +#define AFE_GASRC14_NEW_CON0 0x4fc0 +#define AFE_GASRC14_NEW_CON1 0x4fc4 +#define AFE_GASRC14_NEW_CON2 0x4fc8 +#define AFE_GASRC14_NEW_CON3 0x4fcc +#define AFE_GASRC14_NEW_CON4 0x4fd0 +#define AFE_GASRC14_NEW_CON5 0x4fd4 +#define AFE_GASRC14_NEW_CON6 0x4fd8 +#define AFE_GASRC14_NEW_CON7 0x4fdc +#define AFE_GASRC14_NEW_CON8 0x4fe0 +#define AFE_GASRC14_NEW_CON9 0x4fe4 +#define AFE_GASRC14_NEW_CON10 0x4fe8 +#define AFE_GASRC14_NEW_CON11 0x4fec +#define AFE_GASRC14_NEW_CON12 0x4ff0 +#define AFE_GASRC14_NEW_CON13 0x4ff4 +#define AFE_GASRC14_NEW_CON14 0x4ff8 +#define AFE_GASRC15_NEW_CON0 0x5000 +#define AFE_GASRC15_NEW_CON1 0x5004 +#define AFE_GASRC15_NEW_CON2 0x5008 +#define AFE_GASRC15_NEW_CON3 0x500c +#define AFE_GASRC15_NEW_CON4 0x5010 +#define AFE_GASRC15_NEW_CON5 0x5014 +#define AFE_GASRC15_NEW_CON6 0x5018 +#define AFE_GASRC15_NEW_CON7 0x501c +#define AFE_GASRC15_NEW_CON8 0x5020 +#define AFE_GASRC15_NEW_CON9 0x5024 +#define AFE_GASRC15_NEW_CON10 0x5028 +#define AFE_GASRC15_NEW_CON11 0x502c +#define AFE_GASRC15_NEW_CON12 0x5030 +#define AFE_GASRC15_NEW_CON13 0x5034 +#define AFE_GASRC15_NEW_CON14 0x5038 +#define AFE_GASRC16_NEW_CON0 0x5040 +#define AFE_GASRC16_NEW_CON1 0x5044 +#define AFE_GASRC16_NEW_CON2 0x5048 +#define AFE_GASRC16_NEW_CON3 0x504c +#define AFE_GASRC16_NEW_CON4 0x5050 +#define AFE_GASRC16_NEW_CON5 0x5054 +#define AFE_GASRC16_NEW_CON6 0x5058 +#define AFE_GASRC16_NEW_CON7 0x505c +#define AFE_GASRC16_NEW_CON8 0x5060 +#define AFE_GASRC16_NEW_CON9 0x5064 +#define AFE_GASRC16_NEW_CON10 0x5068 +#define AFE_GASRC16_NEW_CON11 0x506c +#define AFE_GASRC16_NEW_CON12 0x5070 +#define AFE_GASRC16_NEW_CON13 0x5074 +#define AFE_GASRC16_NEW_CON14 0x5078 +#define AFE_GASRC17_NEW_CON0 0x5080 +#define AFE_GASRC17_NEW_CON1 0x5084 +#define AFE_GASRC17_NEW_CON2 0x5088 +#define AFE_GASRC17_NEW_CON3 0x508c +#define AFE_GASRC17_NEW_CON4 0x5090 +#define AFE_GASRC17_NEW_CON5 0x5094 +#define AFE_GASRC17_NEW_CON6 0x5098 +#define AFE_GASRC17_NEW_CON7 0x509c +#define AFE_GASRC17_NEW_CON8 0x50a0 +#define AFE_GASRC17_NEW_CON9 0x50a4 +#define AFE_GASRC17_NEW_CON10 0x50a8 +#define AFE_GASRC17_NEW_CON11 0x50ac +#define AFE_GASRC17_NEW_CON12 0x50b0 +#define AFE_GASRC17_NEW_CON13 0x50b4 +#define AFE_GASRC17_NEW_CON14 0x50b8 +#define AFE_GASRC18_NEW_CON0 0x50c0 +#define AFE_GASRC18_NEW_CON1 0x50c4 +#define AFE_GASRC18_NEW_CON2 0x50c8 +#define AFE_GASRC18_NEW_CON3 0x50cc +#define AFE_GASRC18_NEW_CON4 0x50d0 +#define AFE_GASRC18_NEW_CON5 0x50d4 +#define AFE_GASRC18_NEW_CON6 0x50d8 +#define AFE_GASRC18_NEW_CON7 0x50dc +#define AFE_GASRC18_NEW_CON8 0x50e0 +#define AFE_GASRC18_NEW_CON9 0x50e4 +#define AFE_GASRC18_NEW_CON10 0x50e8 +#define AFE_GASRC18_NEW_CON11 0x50ec +#define AFE_GASRC18_NEW_CON12 0x50f0 +#define AFE_GASRC18_NEW_CON13 0x50f4 +#define AFE_GASRC18_NEW_CON14 0x50f8 +#define AFE_GASRC19_NEW_CON0 0x5100 +#define AFE_GASRC19_NEW_CON1 0x5104 +#define AFE_GASRC19_NEW_CON2 0x5108 +#define AFE_GASRC19_NEW_CON3 0x510c +#define AFE_GASRC19_NEW_CON4 0x5110 +#define AFE_GASRC19_NEW_CON5 0x5114 +#define AFE_GASRC19_NEW_CON6 0x5118 +#define AFE_GASRC19_NEW_CON7 0x511c +#define AFE_GASRC19_NEW_CON8 0x5120 +#define AFE_GASRC19_NEW_CON9 0x5124 +#define AFE_GASRC19_NEW_CON10 0x5128 +#define AFE_GASRC19_NEW_CON11 0x512c +#define AFE_GASRC19_NEW_CON12 0x5130 +#define AFE_GASRC19_NEW_CON13 0x5134 +#define AFE_GASRC19_NEW_CON14 0x5138 + +/* ASYS_TOP_CON */ +#define ASYS_TOP_CON_A1SYS_TIMING_ON BIT(0) +#define ASYS_TOP_CON_A2SYS_TIMING_ON BIT(1) +#define ASYS_TOP_CON_A3SYS_TIMING_ON BIT(4) +#define ASYS_TOP_CON_A4SYS_TIMING_ON BIT(5) +#define ASYS_TOP_CON_26M_TIMING_ON BIT(2) + +/* PWR2_TOP_CON0 */ +#define PWR2_TOP_CON_DMIC8_SRC_SEL_MASK GENMASK(31, 29) +#define PWR2_TOP_CON_DMIC7_SRC_SEL_MASK GENMASK(28, 26) +#define PWR2_TOP_CON_DMIC6_SRC_SEL_MASK GENMASK(25, 23) +#define PWR2_TOP_CON_DMIC5_SRC_SEL_MASK GENMASK(22, 20) +#define PWR2_TOP_CON_DMIC4_SRC_SEL_MASK GENMASK(19, 17) +#define PWR2_TOP_CON_DMIC3_SRC_SEL_MASK GENMASK(16, 14) +#define PWR2_TOP_CON_DMIC2_SRC_SEL_MASK GENMASK(13, 11) +#define PWR2_TOP_CON_DMIC1_SRC_SEL_MASK GENMASK(10, 8) +#define PWR2_TOP_CON_DMIC8_SRC_SEL_VAL(x) ((x) << 29) +#define PWR2_TOP_CON_DMIC7_SRC_SEL_VAL(x) ((x) << 26) +#define PWR2_TOP_CON_DMIC6_SRC_SEL_VAL(x) ((x) << 23) +#define PWR2_TOP_CON_DMIC5_SRC_SEL_VAL(x) ((x) << 20) +#define PWR2_TOP_CON_DMIC4_SRC_SEL_VAL(x) ((x) << 17) +#define PWR2_TOP_CON_DMIC3_SRC_SEL_VAL(x) ((x) << 14) +#define PWR2_TOP_CON_DMIC2_SRC_SEL_VAL(x) ((x) << 11) +#define PWR2_TOP_CON_DMIC1_SRC_SEL_VAL(x) ((x) << 8) + +/* PWR2_TOP_CON1 */ +#define PWR2_TOP_CON1_DMIC_CKDIV_ON BIT(1) + +/* PCM_INTF_CON1 */ +#define PCM_INTF_CON1_SYNC_OUT_INV BIT(23) +#define PCM_INTF_CON1_BCLK_OUT_INV BIT(22) +#define PCM_INTF_CON1_CLK_OUT_INV_MASK GENMASK(23, 22) +#define PCM_INTF_CON1_SYNC_IN_INV BIT(21) +#define PCM_INTF_CON1_BCLK_IN_INV BIT(20) +#define PCM_INTF_CON1_CLK_IN_INV_MASK GENMASK(21, 20) +#define PCM_INTF_CON1_PCM_24BIT BIT(16) +#define PCM_INTF_CON1_PCM_16BIT (0 << 16) +#define PCM_INTF_CON1_PCM_BIT_MASK BIT(16) +#define PCM_INTF_CON1_PCM_WLEN_32BCK (0 << 14) +#define PCM_INTF_CON1_PCM_WLEN_64BCK BIT(14) +#define PCM_INTF_CON1_PCM_WLEN_MASK BIT(14) +#define PCM_INTF_CON1_SYNC_LENGTH(x) (((x) & 0x1f) << 9) +#define PCM_INTF_CON1_SYNC_LENGTH_MASK (0x1f << 9) +#define PCM_INTF_CON1_PCM_SLAVE BIT(5) +#define PCM_INTF_CON1_PCM_MASTER (0 << 5) +#define PCM_INTF_CON1_PCM_M_S_MASK BIT(5) +#define PCM_INTF_CON1_PCM_MODE(x) (((x) & 0x3) << 3) +#define PCM_INTF_CON1_PCM_MODE_MASK (0x3 << 3) +#define PCM_INTF_CON1_PCM_FMT(x) (((x) & 0x3) << 1) +#define PCM_INTF_CON1_PCM_FMT_MASK (0x3 << 1) +#define PCM_INTF_CON1_PCM_EN BIT(0) + +/* PCM_INTF_CON2 */ +#define PCM_INTF_CON2_CLK_DOMAIN_SEL(x) (((x) & 0x3) << 23) +#define PCM_INTF_CON2_CLK_DOMAIN_SEL_MASK (0x3 << 23) +#define PCM_INTF_CON2_SYNC_FREQ_MODE(x) (((x) & 0x1f) << 12) +#define PCM_INTF_CON2_SYNC_FREQ_MODE_MASK (0x1f << 12) +#define PCM_INTF_CON2_PCM_TX2RX_LPBK BIT(8) + +/* AFE_MPHONE_MULTIx_CON0 */ +#define AFE_MPHONE_MULTI_CON0_16BIT_SWAP BIT(3) +#define AFE_MPHONE_MULTI_CON0_16BIT_SWAP_MASK BIT(3) +#define AFE_MPHONE_MULTI_CON0_24BIT_DATA (0x1 << 1) +#define AFE_MPHONE_MULTI_CON0_16BIT_DATA (0x0 << 1) +#define AFE_MPHONE_MULIT_CON0_24BIT_DATA_MASK BIT(1) +#define AFE_MPHONE_MULTI_CON0_EN BIT(0) +#define AFE_MPHONE_MULTI_CON0_EN_MASK BIT(0) + +/* AFE_MPHONE_MULTIx_CON1 */ +#define AFE_MPHONE_MULTI_CON1_SYNC_ON BIT(24) +#define AFE_MPHONE_MULTI_CON1_SYNC_ON_MASK BIT(24) +#define AFE_MPHONE_MULTI_CON1_24BIT_SWAP_BYPASS BIT(22) +#define AFE_MPHONE_MULTI_CON1_24BIT_SWAP_BYPASS_MASK BIT(22) +#define AFE_MPHONE_MULTI_CON1_NON_COMPACT_MODE (0x1 << 19) +#define AFE_MPHONE_MULTI_CON1_COMPACT_MODE (0x0 << 19) +#define AFE_MPHONE_MULTI_CON1_NON_COMPACT_MODE_MASK BIT(19) +#define AFE_MPHONE_MULTI_CON1_HBR_MODE BIT(18) +#define AFE_MPHONE_MULTI_CON1_HBR_MODE_MASK BIT(18) +#define AFE_MPHONE_MULTI_CON1_LRCK_32_CYCLE (0x2 << 16) +#define AFE_MPHONE_MULTI_CON1_LRCK_24_CYCLE (0x1 << 16) +#define AFE_MPHONE_MULTI_CON1_LRCK_16_CYCLE (0x0 << 16) +#define AFE_MPHONE_MULTI_CON1_LRCK_CYCLE_SEL_MASK GENMASK(17, 16) +#define AFE_MPHONE_MULTI_CON1_LRCK_INV BIT(15) +#define AFE_MPHONE_MULTI_CON1_LRCK_INV_MASK BIT(15) +#define AFE_MPHONE_MULTI_CON1_DELAY_DATA BIT(14) +#define AFE_MPHONE_MULTI_CON1_DELAY_DATA_MASK BIT(14) +#define AFE_MPHONE_MULTI_CON1_LEFT_ALIGN BIT(13) +#define AFE_MPHONE_MULTI_CON1_LEFT_ALIGN_MASK BIT(13) +#define AFE_MPHONE_MULTI_CON1_BIT_NUM(x) ((((x) - 1) & 0x1f) << 8) +#define AFE_MPHONE_MULTI_CON1_BIT_NUM_MASK GENMASK(12, 8) +#define AFE_MPHONE_MULTI_CON1_BCK_INV BIT(6) +#define AFE_MPHONE_MULTI_CON1_BCK_INV_MASK BIT(6) +#define AFE_MPHONE_MULTI_CON1_CH_NUM(x) ((((x) >> 1) - 1) & 0x3) +#define AFE_MPHONE_MULTI_CON1_CH_NUM_MASK GENMASK(1, 0) + +/* AFE_MPHONE_MULTIx_CON2 */ +#define AFE_MPHONE_MULTI_CON2_SEL_SPDIFIN BIT(19) +#define AFE_MPHONE_MULTI_CON2_SEL_SPDIFIN_MASK BIT(19) + +/* AFE_AUD_PAD_TOP */ +#define RG_RX_PROTOCOL2 BIT(3) +#define RG_RX_FIFO_ON BIT(0) + +/* AFE_ADDA_MTKAIF_CFG0 */ +#define MTKAIF_RXIF_CLKINV_ADC BIT(31) +#define MTKAIF_RXIF_PROTOCOL2 BIT(16) +#define MTKAIF_TXIF_PROTOCOL2 BIT(4) +#define MTKAIF_TXIF_8TO5 BIT(2) +#define MTKAIF_RXIF_8TO5 BIT(1) +#define MTKAIF_IF_LOOPBACK1 BIT(0) + +/* AFE_ADDA_MTKAIF_RX_CFG2 */ +#define MTKAIF_RXIF_DELAY_CYCLE(x) ((x) << 12) +#define MTKAIF_RXIF_DELAY_CYCLE_MASK GENMASK(15, 12) +#define MTKAIF_RXIF_DELAY_DATA BIT(8) +#define MTKAIF_RXIF_DELAY_DATA_SHIFT 8 + +/* AFE_ADDA_MTKAIF_SYNCWORD_CFG */ +#define ADDA6_MTKAIF_RX_SYNC_WORD2_DISABLE BIT(23) + +/* AFE_DMICx_UL_SRC_CON0 */ +#define AFE_DMIC_UL_SRC_CON0_UL_PHASE_SEL_CH1(x) (((x) & 0x7) << 27) +#define AFE_DMIC_UL_SRC_CON0_UL_PHASE_SEL_CH2(x) (((x) & 0x7) << 24) +#define AFE_DMIC_UL_SRC_CON0_UL_TWO_WIRE_MODE_CTL BIT(23) +#define AFE_DMIC_UL_SRC_CON0_UL_MODE_3P25M_CH2_CTL BIT(22) +#define AFE_DMIC_UL_SRC_CON0_UL_MODE_3P25M_CH1_CTL BIT(21) +#define AFE_DMIC_UL_VOICE_MODE(x) (((x) & 0x7) << 17) +#define AFE_DMIC_UL_CON0_VOCIE_MODE_8K AFE_DMIC_UL_VOICE_MODE(0) +#define AFE_DMIC_UL_CON0_VOCIE_MODE_16K AFE_DMIC_UL_VOICE_MODE(1) +#define AFE_DMIC_UL_CON0_VOCIE_MODE_32K AFE_DMIC_UL_VOICE_MODE(2) +#define AFE_DMIC_UL_CON0_VOCIE_MODE_48K AFE_DMIC_UL_VOICE_MODE(3) +#define AFE_DMIC_UL_SRC_CON0_UL_IIR_MODE_CTL(x) (((x) & 0x7) << 7) +#define AFE_DMIC_UL_SRC_CON0_UL_IIR_ON_TMP_CTL BIT(10) +#define AFE_DMIC_UL_SRC_CON0_UL_SDM_3_LEVEL_CTL BIT(1) +#define AFE_DMIC_UL_SRC_CON0_UL_SRC_ON_TMP_CTL BIT(0) + +/* ETDM_INx_AFIFO_CON */ +#define ETDM_IN_USE_AFIFO BIT(8) +#define ETDM_IN_AFIFO_CLOCK(x) ((x) << 5) +#define ETDM_IN_AFIFO_CLOCK_MASK GENMASK(7, 5) +#define ETDM_IN_AFIFO_MODE(x) ((x) << 0) +#define ETDM_IN_AFIFO_MODE_MASK GENMASK(4, 0) + +/* ETDM_COWORK_CON0 */ +#define ETDM_OUT1_SLAVE_SEL(x) ((x) << 20) +#define ETDM_OUT1_SLAVE_SEL_MASK GENMASK(23, 20) +#define ETDM_OUT1_SLAVE_SEL_SHIFT 20 + +/* ETDM_COWORK_CON1 */ +#define ETDM_IN1_SDATA_SEL(x) ((x) << 20) +#define ETDM_IN1_SDATA_SEL_MASK GENMASK(23, 20) +#define ETDM_IN1_SDATA_SEL_SHIFT 20 +#define ETDM_IN1_SDATA0_SEL(x) ((x) << 16) +#define ETDM_IN1_SDATA0_SEL_MASK GENMASK(19, 16) +#define ETDM_IN1_SDATA0_SEL_SHIFT 16 +#define ETDM_IN1_SLAVE_SEL(x) ((x) << 8) +#define ETDM_IN1_SLAVE_SEL_MASK GENMASK(11, 8) +#define ETDM_IN1_SLAVE_SEL_SHIFT 8 + +/* ETDM_COWORK_CON2 */ +#define ETDM_IN2_SLAVE_SEL(x) ((x) << 24) +#define ETDM_IN2_SLAVE_SEL_MASK GENMASK(27, 24) +#define ETDM_IN2_SLAVE_SEL_SHIFT 24 +#define ETDM_OUT3_SLAVE_SEL(x) ((x) << 20) +#define ETDM_OUT3_SLAVE_SEL_MASK GENMASK(23, 20) +#define ETDM_OUT3_SLAVE_SEL_SHIFT 20 +#define ETDM_OUT2_SLAVE_SEL(x) ((x) << 8) +#define ETDM_OUT2_SLAVE_SEL_MASK GENMASK(11, 8) +#define ETDM_OUT2_SLAVE_SEL_SHIFT 8 + +/* ETDM_COWORK_CON3 */ +#define ETDM_IN2_SDATA_SEL(x) ((x) << 4) +#define ETDM_IN2_SDATA_SEL_MASK GENMASK(7, 4) +#define ETDM_IN2_SDATA_SEL_SHIFT 4 +#define ETDM_IN2_SDATA0_SEL(x) ((x) << 0) +#define ETDM_IN2_SDATA0_SEL_MASK GENMASK(3, 0) +#define ETDM_IN2_SDATA0_SEL_SHIFT 0 + +/* ETDM_x_CONx */ +#define ETDM_CON0_CH_NUM(x) (((x) - 1) << 23) +#define ETDM_CON0_CH_NUM_MASK GENMASK(27, 23) +#define ETDM_CON0_WORD_LEN(x) (((x) - 1) << 16) +#define ETDM_CON0_WORD_LEN_MASK GENMASK(20, 16) +#define ETDM_CON0_BIT_LEN(x) (((x) - 1) << 11) +#define ETDM_CON0_BIT_LEN_MASK GENMASK(15, 11) +#define ETDM_CON0_FORMAT(x) ((x) << 6) +#define ETDM_CON0_FORMAT_MASK GENMASK(8, 6) +#define ETDM_CON0_SLAVE_MODE BIT(5) +#define ETDM_CON0_EN BIT(0) + +#define ETDM_OUT_CON0_RELATCH_DOMAIN(x) ((x) << 28) +#define ETDM_OUT_CON0_RELATCH_DOMAIN_MASK GENMASK(29, 28) + +#define ETDM_CON1_LRCK_AUTO_MODE BIT(29) +#define ETDM_CON1_LRCK_WIDTH(x) (((x) - 1) << 20) +#define ETDM_CON1_LRCK_WIDTH_MASK GENMASK(29, 20) +#define ETDM_CON1_MCLK_OUTPUT BIT(16) + +#define ETDM_IN_CON2_MULTI_IP_2CH_MODE BIT(31) +#define ETDM_IN_CON2_MULTI_IP_TOTAL_CH(x) (((x) - 1) << 15) +#define ETDM_IN_CON2_MULTI_IP_TOTAL_CH_MASK GENMASK(19, 15) +#define ETDM_IN_CON2_CLOCK(x) ((x) << 10) +#define ETDM_IN_CON2_CLOCK_MASK GENMASK(12, 10) +#define ETDM_IN_CON2_CLOCK_SHIFT 10 +#define ETDM_IN_CON2_UPDATE_GAP(x) ((x) << 5) +#define ETDM_IN_CON2_UPDATE_GAP_MASK GENMASK(9, 5) + +#define ETDM_OUT_CON2_LRCK_DELAY_BCK_INV BIT(30) +#define ETDM_OUT_CON2_LRCK_DELAY_0P5T_EN BIT(29) + +#define ETDM_IN_CON3_FS(x) ((x) << 26) +#define ETDM_IN_CON3_FS_MASK GENMASK(30, 26) +#define ETDM_IN_CON3_DISABLE_OUT(x) BIT(((x) & 0xffff)) +#define ETDM_IN_CON3_DISABLE_OUT_MASK GENMASK(15, 0) + +#define ETDM_IN_CON4_MASTER_LRCK_INV BIT(19) +#define ETDM_IN_CON4_MASTER_BCK_INV BIT(18) +#define ETDM_IN_CON4_SLAVE_LRCK_INV BIT(17) +#define ETDM_IN_CON4_SLAVE_BCK_INV BIT(16) + +#define ETDM_OUT_CON4_RELATCH_EN(x) ((x) << 24) +#define ETDM_OUT_CON4_RELATCH_EN_MASK GENMASK(28, 24) +#define ETDM_OUT_CON4_CLOCK(x) ((x) << 6) +#define ETDM_OUT_CON4_CLOCK_MASK GENMASK(8, 6) +#define ETDM_OUT_CON4_CLOCK_SHIFT 6 +#define ETDM_OUT_CON4_FS(x) ((x) << 0) +#define ETDM_OUT_CON4_FS_MASK GENMASK(4, 0) + +#define ETDM_IN_CON5_LR_SWAP(x) BIT(((x) & 0xffff) + 16) +#define ETDM_IN_CON5_LR_SWAP_MASK GENMASK(31, 16) +#define ETDM_IN_CON5_ENABLE_ODD(x) BIT(((x) & 0xffff)) +#define ETDM_IN_CON5_ENABLE_ODD_MASK GENMASK(15, 0) + +#define ETDM_OUT_CON5_MASTER_LRCK_INV BIT(10) +#define ETDM_OUT_CON5_MASTER_BCK_INV BIT(9) +#define ETDM_OUT_CON5_SLAVE_LRCK_INV BIT(8) +#define ETDM_OUT_CON5_SLAVE_BCK_INV BIT(7) + +/* AFE_DPTX_CON */ +#define AFE_DPTX_CON_CH_EN(x) (((x) & 0xf) << 8) +#define AFE_DPTX_CON_CH_EN_2CH (AFE_DPTX_CON_CH_EN(GENMASK(1, 0))) +#define AFE_DPTX_CON_CH_EN_4CH (AFE_DPTX_CON_CH_EN(GENMASK(3, 0))) +#define AFE_DPTX_CON_CH_EN_6CH (AFE_DPTX_CON_CH_EN(GENMASK(5, 0))) +#define AFE_DPTX_CON_CH_EN_8CH (AFE_DPTX_CON_CH_EN(GENMASK(7, 0))) +#define AFE_DPTX_CON_CH_EN_MASK GENMASK(15, 8) +#define AFE_DPTX_CON_16BIT BIT(2) +#define AFE_DPTX_CON_24BIT (0 << 2) +#define AFE_DPTX_CON_16BIT_MASK BIT(2) +#define AFE_DPTX_CON_CH_NUM(x) (((x) & 0x1) << 1) +#define AFE_DPTX_CON_CH_NUM_2CH (AFE_DPTX_CON_CH_NUM(0)) +#define AFE_DPTX_CON_CH_NUM_8CH (AFE_DPTX_CON_CH_NUM(1)) +#define AFE_DPTX_CON_CH_NUM_MASK (0x1 << 1) +#define AFE_DPTX_CON_ON BIT(0) +#define AFE_DPTX_CON_ON_MASK BIT(0) + +/* AFE_ADDA_UL_DL_CON0 */ +#define ADDA_AFE_ON_SHIFT 0 + +/* AFE_ADDA_DL_SRC2_CON0 */ +#define DL_2_INPUT_MODE_CTL(x) ((x) << 28) +#define DL_2_INPUT_MODE_CTL_MASK GENMASK(31, 28) +#define DL_2_CH1_SATURATION_EN_CTL BIT(27) +#define DL_2_CH2_SATURATION_EN_CTL BIT(26) +#define DL_2_MUTE_CH1_OFF_CTL_PRE BIT(12) +#define DL_2_MUTE_CH2_OFF_CTL_PRE BIT(11) +#define DL_2_VOICE_MODE_CTL_PRE BIT(5) +#define DL_2_GAIN_ON_CTL_PRE_SHIFT 1 +#define DL_2_SRC_ON_TMP_CTRL_PRE_SHIFT 0 + +/* AFE_ADDA_DL_SRC2_CON1 */ +#define DL_2_GAIN_CTL_PRE(x) ((x) << 16) +#define DL_2_GAIN_CTL_PRE_MASK GENMASK(31, 16) +#define DL_2_GAIN_CTL_PRE_SHIFT 16 + +/* AFE_ADDA_TOP_CON0 */ +#define C_LOOPBACK_MODE_CTL_MASK GENMASK(15, 12) +#define DL_INPUT_FROM_SINEGEN (4 << 12) + +/* AFE_ADDA_DL_SDM_DCCOMP_CON */ +#define DL_USE_NEW_2ND_SDM BIT(30) +#define ATTGAIN_CTL_MASK GENMASK(5, 0) + +/* AFE_ADDA_UL_SRC_CON0 */ +#define UL_MODE_3P25M_CH2_CTL BIT(22) +#define UL_MODE_3P25M_CH1_CTL BIT(21) +#define UL_VOICE_MODE_CTL(x) ((x) << 17) +#define UL_VOICE_MODE_CTL_MASK GENMASK(19, 17) +#define UL_LOOPBACK_MODE_CTL BIT(2) +#define UL_SDM3_LEVEL_CTL BIT(1) +#define UL_SRC_ON_TMP_CTL_SHIFT 0 + +#endif From 438df3a0718c0a10a35a5e9b898e4ff52724de69 Mon Sep 17 00:00:00 2001 From: Allen-KH Cheng Date: Fri, 3 Sep 2021 18:01:01 +0800 Subject: [PATCH 09/15] platform: mtk: compile afe support for mt8195 The AFE is a audio hw interface on the mt8195 platform. This commit brings the compile support for the AFE. The audio front-end essentially consists of voice and audio data paths Signed-off-by: YC Hung Signed-off-by: Allen-KH Cheng --- src/drivers/mediatek/mt8195/CMakeLists.txt | 2 +- src/platform/mt8195/CMakeLists.txt | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/drivers/mediatek/mt8195/CMakeLists.txt b/src/drivers/mediatek/mt8195/CMakeLists.txt index d4fafaf25d08..a0b748083088 100644 --- a/src/drivers/mediatek/mt8195/CMakeLists.txt +++ b/src/drivers/mediatek/mt8195/CMakeLists.txt @@ -1,6 +1,6 @@ # SPDX-License-Identifier: BSD-3-Clause add_local_sources(sof ipc.c timer.c - interrupt.c + interrupt.c uart.c afe-memif.c afe-dai.c afe-drv.c ) diff --git a/src/platform/mt8195/CMakeLists.txt b/src/platform/mt8195/CMakeLists.txt index 3d3806b32bf0..1452f7ec44a5 100644 --- a/src/platform/mt8195/CMakeLists.txt +++ b/src/platform/mt8195/CMakeLists.txt @@ -2,5 +2,5 @@ add_subdirectory(lib) -add_local_sources(sof platform.c) +add_local_sources(sof platform.c printf.c afe-platform.c) target_include_directories(sof_options INTERFACE ${PROJECT_SOURCE_DIR}/src/platform/mt8195/include/platform) From d678beaff40b4c96c84583e8bbaa6b08b5c0fe8f Mon Sep 17 00:00:00 2001 From: Allen-KH Cheng Date: Fri, 27 Aug 2021 16:28:24 +0800 Subject: [PATCH 10/15] topology1: add mt8195.m4 Add mt8195 pipelines and components Signed-off-by: YC Hung Signed-off-by: Allen-KH Cheng --- .../topology1/platform/mediatek/mt8195.m4 | 23 +++++++++++++++++++ 1 file changed, 23 insertions(+) create mode 100644 tools/topology/topology1/platform/mediatek/mt8195.m4 diff --git a/tools/topology/topology1/platform/mediatek/mt8195.m4 b/tools/topology/topology1/platform/mediatek/mt8195.m4 new file mode 100644 index 000000000000..dff17dc3d7e0 --- /dev/null +++ b/tools/topology/topology1/platform/mediatek/mt8195.m4 @@ -0,0 +1,23 @@ +# +# MT8195 differentiation for pipelines and components +# + +include(`memory.m4') + +define(`PLATFORM_DAI_MEM_CAP', MEMCAPS(MEM_CAP_RAM, MEM_CAP_DMA, MEM_CAP_CACHE)) +define(`PLATFORM_HOST_MEM_CAP', MEMCAPS(MEM_CAP_RAM, MEM_CAP_DMA, MEM_CAP_CACHE)) +define(`PLATFORM_PASS_MEM_CAP', MEMCAPS(MEM_CAP_RAM, MEM_CAP_DMA, MEM_CAP_CACHE)) +define(`PLATFORM_COMP_MEM_CAP', MEMCAPS(MEM_CAP_RAM, MEM_CAP_CACHE)) + +# Low Latency PCM Configuration +W_VENDORTUPLES(pipe_ll_schedule_plat_tokens, sof_sched_tokens, LIST(` ', `SOF_TKN_SCHED_MIPS "50000"')) +W_DATA(pipe_ll_schedule_plat, pipe_ll_schedule_plat_tokens) + +# Media PCM Configuration +W_VENDORTUPLES(pipe_media_schedule_plat_tokens, sof_sched_tokens, LIST(` ', `SOF_TKN_SCHED_MIPS "100000"')) +W_DATA(pipe_media_schedule_plat, pipe_media_schedule_plat_tokens) + +# DAI schedule Configuration - scheduled by IRQ +W_VENDORTUPLES(pipe_dai_schedule_plat_tokens, sof_sched_tokens, LIST(` ', `SOF_TKN_SCHED_MIPS "5000"')) +W_DATA(pipe_dai_schedule_plat, pipe_dai_schedule_plat_tokens) + From 57e76d6bfe70459709c977299f9cc1f16e7ea2d7 Mon Sep 17 00:00:00 2001 From: Allen-KH Cheng Date: Fri, 27 Aug 2021 16:29:51 +0800 Subject: [PATCH 11/15] topology1: add sof-mt8195-mt6359-rt1019-rt5682.m4 Add sof-mt8195-mt6359-rt1019-rt5682.m4 for mt8195 Signed-off-by: YC Hung Signed-off-by: Allen-KH Cheng --- .../sof-mt8195-mt6359-rt1019-rt5682.m4 | 124 ++++++++++++++++++ 1 file changed, 124 insertions(+) create mode 100644 tools/topology/topology1/sof-mt8195-mt6359-rt1019-rt5682.m4 diff --git a/tools/topology/topology1/sof-mt8195-mt6359-rt1019-rt5682.m4 b/tools/topology/topology1/sof-mt8195-mt6359-rt1019-rt5682.m4 new file mode 100644 index 000000000000..4e8dc7d4c8cd --- /dev/null +++ b/tools/topology/topology1/sof-mt8195-mt6359-rt1019-rt5682.m4 @@ -0,0 +1,124 @@ +# +# Topology for MT8195 board with mt6359/rt5682/rt1019 +# + +# Include topology builder +include(`utils.m4') +include(`dai.m4') +include(`pipeline.m4') +include(`afe.m4') +include(`pcm.m4') +include(`buffer.m4') + +# Include TLV library +include(`common/tlv.m4') + +# Include Token library +include(`sof/tokens.m4') + +# Include DSP configuration +include(`platform/mediatek/mt8195.m4') + +# +# Define the pipelines +# +# PCM16 ---> AFE (Speaker - rt1019) +# PCM17 ---> AFE (Headset playback - rt5682) +# PCM18 <--- AFE (DMIC - MT6365) +# PCM19 <--- AFE (Headset record - rt5682) + + +dnl PIPELINE_PCM_ADD(pipeline, +dnl pipe id, pcm, max channels, format, +dnl period, priority, core, +dnl pcm_min_rate, pcm_max_rate, pipeline_rate, +dnl time_domain, sched_comp) + +# Low Latency capture pipeline 1 on PCM 16 using max 2 channels of s16le +# Set 10000us deadline on core 0 with priority 0 +PIPELINE_PCM_ADD(sof/pipe-passthrough-playback.m4, + 1, 16, 2, s16le, + 10000, 0, 0, + 48000, 48000, 48000) + +# Low Latency playback pipeline 2 on PCM 16 using max 2 channels of s16le +# Set 10000us deadline on core 0 with priority 0 +PIPELINE_PCM_ADD(sof/pipe-passthrough-playback.m4, + 2, 17, 2, s16le, + 10000, 0, 0, + 48000, 48000, 48000) + +# Low Latency capture pipeline 3 on PCM 16 using max 2 channels of s16le +# Set 10000us deadline on core 0 with priority 0 +PIPELINE_PCM_ADD(sof/pipe-passthrough-capture.m4, + 3, 18, 2, s16le, + 10000, 0, 0, + 48000, 48000, 48000) + +# Low Latency playback pipeline 4 on PCM 16 using max 2 channels of s16le +# Set 10000us deadline on core 0 with priority 0 +PIPELINE_PCM_ADD(sof/pipe-passthrough-capture.m4, + 4, 19, 2, s16le, + 10000, 0, 0, + 48000, 48000, 48000) + +# +# DAIs configuration +# + +dnl DAI_ADD(pipeline, +dnl pipe id, dai type, dai_index, dai_be, +dnl buffer, periods, format, +dnl deadline, priority, core) + + +# playback DAI is AFE using 2 periods +# Buffers use s16le format, with 48 frame per 1000us on core 0 with priority 0 +DAI_ADD(sof/pipe-dai-playback.m4, + 1, AFE, 0, AFE_SOF_DL2, + PIPELINE_SOURCE_1, 2, s16le, + 10000, 0, 0, SCHEDULE_TIME_DOMAIN_TIMER) + +# playback DAI is AFE using 2 periods +# Buffers use s16le format, with 48 frame per 1000us on core 0 with priority 0 +DAI_ADD(sof/pipe-dai-playback.m4, + 2, AFE, 1, AFE_SOF_DL3, + PIPELINE_SOURCE_2, 2, s16le, + 10000, 0, 0, SCHEDULE_TIME_DOMAIN_TIMER) + +# capture DAI is AFE using 2 periods +# Buffers use s16le format, with 48 frame per 1000us on core 0 with priority 0 +DAI_ADD(sof/pipe-dai-capture.m4, + 3, AFE, 2, AFE_SOF_UL4, + PIPELINE_SINK_3, 2, s16le, + 10000, 0, 0, SCHEDULE_TIME_DOMAIN_TIMER) + +# capture DAI is AFE using 2 periods +# Buffers use s16le format, with 48 frame per 1000us on core 0 with priority 0 +DAI_ADD(sof/pipe-dai-capture.m4, + 4, AFE, 3, AFE_SOF_UL5, + PIPELINE_SINK_4, 2, s16le, + 10000, 0, 0, SCHEDULE_TIME_DOMAIN_TIMER) + +#SCHEDULE_TIME_DOMAIN_DMA +dnl PCM_PLAYBACK_ADD(name, pcm_id, playback) + +# PCM Low Latency, id 0 +PCM_PLAYBACK_ADD(SOF_DL2, 16, PIPELINE_PCM_1) +PCM_PLAYBACK_ADD(SOF_DL3, 17, PIPELINE_PCM_2) +PCM_CAPTURE_ADD(SOF_UL4, 18, PIPELINE_PCM_3) +PCM_CAPTURE_ADD(SOF_UL5, 19, PIPELINE_PCM_4) + +dnl DAI_CONFIG(type, dai_index, link_id, name, afe_config) + +DAI_CONFIG(AFE, 0, 0, AFE_SOF_DL2, + AFE_CONFIG(AFE_CONFIG_DATA(AFE, 0, 48000, 2, s16le))) + +DAI_CONFIG(AFE, 1, 0, AFE_SOF_DL3, + AFE_CONFIG(AFE_CONFIG_DATA(AFE, 1, 48000, 2, s16le))) + +DAI_CONFIG(AFE, 2, 0, AFE_SOF_UL4, + AFE_CONFIG(AFE_CONFIG_DATA(AFE, 2, 48000, 2, s16le))) + +DAI_CONFIG(AFE, 3, 0, AFE_SOF_UL5, + AFE_CONFIG(AFE_CONFIG_DATA(AFE, 3, 48000, 2, s16le))) From adce6ca5c37310d0d67a2f36bc4c49fe98e7b255 Mon Sep 17 00:00:00 2001 From: Allen-KH Cheng Date: Fri, 27 Aug 2021 16:38:19 +0800 Subject: [PATCH 12/15] topology1: add afe.m4 Add afe.m4 for afe related define Signed-off-by: YC Hung Signed-off-by: Allen-KH Cheng --- .../topology/topology1/platform/common/afe.m4 | 28 +++++++++++++++++++ 1 file changed, 28 insertions(+) create mode 100644 tools/topology/topology1/platform/common/afe.m4 diff --git a/tools/topology/topology1/platform/common/afe.m4 b/tools/topology/topology1/platform/common/afe.m4 new file mode 100644 index 000000000000..47a790361ff4 --- /dev/null +++ b/tools/topology/topology1/platform/common/afe.m4 @@ -0,0 +1,28 @@ +divert(-1) + +dnl AFE related macros + +dnl AFE_CONFIG(afe_config_data) +define(`AFE_CONFIG', +`}' +$1 +) + +dnl AFE_CONFIG_DATA(type, idx, rate, channels, format) +define(`AFE_CONFIG_DATA', +`SectionVendorTuples."'N_DAI_CONFIG($1$2)`_tuples" {' +` tokens "sof_afe_tokens"' +` tuples."word" {' +` SOF_TKN_MEDIATEK_AFE_RATE' STR($3) +` SOF_TKN_MEDIATEK_AFE_CH' STR($4) +` }' +` tuples."string" {' +` SOF_TKN_MEDIATEK_AFE_FORMAT' STR($5) +` }' +`}' +`SectionData."'N_DAI_CONFIG($1$2)`_data" {' +` tuples "'N_DAI_CONFIG($1$2)`_tuples"' +`}' +) + +divert(0)dnl From 7a0c00b15e68a4e8d0d92d56cef6145c11db7888 Mon Sep 17 00:00:00 2001 From: Allen-KH Cheng Date: Fri, 27 Aug 2021 16:43:43 +0800 Subject: [PATCH 13/15] topology1: add afe tokens Add afe tokens for mt8195 Signed-off-by: YC Hung Signed-off-by: Allen-KH Cheng --- tools/topology/topology1/sof/tokens.m4 | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/tools/topology/topology1/sof/tokens.m4 b/tools/topology/topology1/sof/tokens.m4 index 86ce138aaccf..c395ee04002b 100644 --- a/tools/topology/topology1/sof/tokens.m4 +++ b/tools/topology/topology1/sof/tokens.m4 @@ -130,3 +130,9 @@ SectionVendorTokens."sof_hda_tokens" { SOF_TKN_INTEL_HDA_RATE "1500" SOF_TKN_INTEL_HDA_CH "1501" } + +SectionVendorTokens."sof_afe_tokens" { + SOF_TKN_MEDIATEK_AFE_RATE "1600" + SOF_TKN_MEDIATEK_AFE_CH "1601" + SOF_TKN_MEDIATEK_AFE_FORMAT "1602" +} From ffe91b62f1985f951e8e70cb8713e358e5399c4d Mon Sep 17 00:00:00 2001 From: Allen-KH Cheng Date: Fri, 27 Aug 2021 16:45:46 +0800 Subject: [PATCH 14/15] topology1: add afe config Add afe config for mt8195 Signed-off-by: YC Hung Signed-off-by: Allen-KH Cheng --- tools/topology/topology1/m4/dai.m4 | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/tools/topology/topology1/m4/dai.m4 b/tools/topology/topology1/m4/dai.m4 index 3ad896e72553..b9e666ee52c0 100644 --- a/tools/topology/topology1/m4/dai.m4 +++ b/tools/topology/topology1/m4/dai.m4 @@ -149,13 +149,13 @@ define(`D_DAI', `SectionDAI."'N_DAI`" {' dnl DAI Config) define(`N_DAI_CONFIG', `DAICONFIG.'$1) -dnl DAI_CONFIG(type, idx, link_id, name, sai_config/esai_config/ssp_config/dmic_config) +dnl DAI_CONFIG(type, idx, link_id, name, sai_config/esai_config/ssp_config/dmic_config/afe_config) define(`DO_DAI_CONFIG', `SectionHWConfig."'$1$2`" {' `' ` id "'$3`"' `' -` ifelse($1, `SSP', $5, $1, `HDA', $5, $1, `ALH', $5, $1, `ESAI', $5, $1, `SAI', $5, `}')' +` ifelse($1, `SSP', $5, $1, `HDA', $5, $1, `ALH', $5, $1, `ESAI', $5, $1, `SAI', $5, $1, `AFE', $5, `}')' `ifelse($1, `DMIC', $5, `')' `SectionVendorTuples."'N_DAI_CONFIG($1$2)`_tuples_common" {' ` tokens "sof_dai_tokens"' From 2c620b3a35c27ae51502c8d989c4db11748e9aa2 Mon Sep 17 00:00:00 2001 From: Allen-KH Cheng Date: Fri, 27 Aug 2021 16:46:48 +0800 Subject: [PATCH 15/15] topology1: add sof-mt8195-mt6359-rt1019-rt5682 topology Add sof-mt8195-mt6359-rt1019-rt5682 topology Signed-off-by: YC Hung Signed-off-by: Allen-KH Cheng --- tools/topology/topology1/CMakeLists.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/tools/topology/topology1/CMakeLists.txt b/tools/topology/topology1/CMakeLists.txt index 3c66bfe90320..83dfa09dc910 100644 --- a/tools/topology/topology1/CMakeLists.txt +++ b/tools/topology/topology1/CMakeLists.txt @@ -163,6 +163,7 @@ set(TPLGS "sof-jsl-rt5682\;sof-jsl-rt5682-rt1015\;-DPLATFORM=jsl-rt1015" "sof-jsl-rt5682\;sof-jsl-rt5682-rt1015-xperi\;-DPLATFORM=jsl-rt1015\;-DINCLUDE_IIR_EQ=1" "sof-jsl-rt5682\;sof-jsl-rt5682-mx98360a\;-DPLATFORM=jsl-dedede" + "sof-mt8195-mt6359-rt1019-rt5682\;sof-mt8195-mt6359-rt1019-rt5682" ) add_custom_target(topologies1 ALL