From c2a5209866abf108d35bdcc380793c37c723bee1 Mon Sep 17 00:00:00 2001 From: Guennadi Liakhovetski Date: Mon, 30 Jan 2023 15:41:00 +0100 Subject: [PATCH] platform: remove support for cAVS 1.5 platforms Remove all support for cAVS 1.5 platformsm including Apollo Lake, Sky Lake, Kaby Lake, Broxton and Gemini Lake, they aren't supported any more. Signed-off-by: Guennadi Liakhovetski --- app/boards/intel_adsp_cavs15.conf | 8 - installer/GNUmakefile | 5 +- scripts/cmake/xtensa-toolchain.cmake | 2 +- scripts/docker_build/sof_builder/Dockerfile | 5 +- scripts/qemu-check.sh | 28 +- scripts/scan/clang-scan-build-xtensa.sh | 2 +- scripts/xtensa-build-all.sh | 44 +- scripts/xtensa-build-zephyr.py | 7 - src/arch/xtensa/CMakeLists.txt | 15 +- src/arch/xtensa/configs/apollolake_defconfig | 11 - src/arch/xtensa/configs/kabylake_defconfig | 6 - src/arch/xtensa/configs/skylake_defconfig | 6 - src/arch/xtensa/xtos/reset-vector.S | 12 +- src/audio/Kconfig | 2 +- src/drivers/intel/cavs/ipc.c | 124 +--- src/drivers/intel/cavs/timestamp.c | 25 - src/include/sof/drivers/dmic.h | 6 - src/ipc/ipc3/handler.c | 4 +- src/platform/CMakeLists.txt | 4 +- src/platform/Kconfig | 34 +- src/platform/apollolake/CMakeLists.txt | 12 - src/platform/apollolake/apollolake.x.in | 629 ------------------ src/platform/apollolake/base_module.c | 30 - src/platform/apollolake/boot_ldr.x.in | 237 ------- src/platform/apollolake/boot_module.c | 30 - .../include/arch/xtensa/config/core-isa.h | 613 ----------------- .../include/arch/xtensa/config/core-matmap.h | 323 --------- .../include/arch/xtensa/config/defs.h | 46 -- .../include/arch/xtensa/config/specreg.h | 114 ---- .../include/arch/xtensa/config/system.h | 285 -------- .../include/arch/xtensa/config/tie-asm.h | 293 -------- .../include/arch/xtensa/config/tie.h | 188 ------ .../include/platform/drivers/dw-dma.h | 21 - .../apollolake/include/platform/drivers/idc.h | 21 - .../include/platform/drivers/interrupt.h | 152 ----- .../apollolake/include/platform/drivers/mn.h | 21 - .../include/platform/drivers/timestamp.h | 42 -- .../include/platform/lib/asm_ldo_management.h | 20 - .../platform/lib/asm_memory_management.h | 70 -- .../apollolake/include/platform/lib/clk.h | 42 -- .../apollolake/include/platform/lib/cpu.h | 26 - .../apollolake/include/platform/lib/dai.h | 46 -- .../apollolake/include/platform/lib/dma.h | 65 -- .../apollolake/include/platform/lib/mailbox.h | 22 - .../apollolake/include/platform/lib/memory.h | 494 -------------- .../include/platform/lib/pm_runtime.h | 27 - .../apollolake/include/platform/lib/shim.h | 268 -------- .../apollolake/include/platform/platform.h | 120 ---- .../apollolake/include/platform/trace/trace.h | 21 - src/platform/apollolake/lib/CMakeLists.txt | 6 - src/platform/apollolake/lib/clk.c | 48 -- src/platform/apollolake/lib/power_down.S | 152 ----- src/platform/apollolake/rom.x.in | 347 ---------- src/platform/cannonlake/rom.x.in | 2 +- src/platform/icelake/rom.x.in | 2 +- .../include/cavs/lib/asm_memory_management.h | 2 - .../intel/cavs/include/cavs/lib/pm_memory.h | 4 - .../intel/cavs/include/cavs/version.h | 5 +- src/platform/intel/cavs/lib/clk.c | 12 - src/platform/intel/cavs/lib/dma.c | 9 +- src/platform/intel/cavs/lib/pm_memory.c | 6 - src/platform/intel/cavs/lib/pm_runtime.c | 79 +-- src/platform/intel/cavs/lib/power_down.S | 5 - src/platform/intel/cavs/platform.c | 45 +- src/platform/tigerlake/rom.x.in | 2 +- src/samples/audio/Kconfig | 2 +- tools/README.md | 6 +- tools/topology/topology1/CMakeLists.txt | 43 -- .../topology1/development/CMakeLists.txt | 19 - .../development/sof-apl-asrc-pcm512x.m4 | 117 ---- .../development/sof-apl-asrc-wm8804.m4 | 86 --- .../development/sof-apl-dmic-a96k-b16k.m4 | 104 --- .../development/sof-apl-dmic-asymmetric.m4 | 103 --- .../topology1/development/sof-apl-dmic.m4 | 108 --- .../development/sof-apl-nocodec-ci.m4 | 321 --------- .../sof-apl-nocodec-demux-eq-2ch4ch.m4 | 113 ---- .../sof-apl-nocodec-demux-eq-4ch4ch.m4 | 114 ---- .../development/sof-apl-pcm512x-nohdmi.m4 | 82 --- .../development/sof-apl-src-50khz-pcm512x.m4 | 74 --- .../development/sof-apl-src-pcm512x.m4 | 117 ---- .../topology1/platform/intel/apl-dmic-a2b2.m4 | 20 - .../topology1/platform/intel/apl-dmic-a2b4.m4 | 20 - .../topology1/platform/intel/apl-dmic-a4b2.m4 | 20 - .../topology1/platform/intel/glk-da7219.m4 | 17 - tools/topology/topology1/sof-apl-da7219.m4 | 211 ------ .../topology1/sof-apl-demux-pcm512x.m4 | 200 ------ .../topology1/sof-apl-keyword-detect.m4 | 99 --- tools/topology/topology1/sof-apl-pcm512x.m4 | 206 ------ tools/topology/topology1/sof-apl-rt298.m4 | 124 ---- tools/topology/topology1/sof-apl-tdf8532.m4 | 262 -------- tools/topology/topology1/sof-apl-wm8804.m4 | 81 --- tools/topology/topology1/sof-cavs-nocodec.m4 | 34 +- tools/topology/topology1/sof-glk-da7219.m4 | 240 ------- tools/topology/topology1/sof-glk-rt5682.m4 | 214 ------ zephyr/CMakeLists.txt | 73 -- 95 files changed, 46 insertions(+), 8538 deletions(-) delete mode 100644 app/boards/intel_adsp_cavs15.conf delete mode 100644 src/arch/xtensa/configs/apollolake_defconfig delete mode 100644 src/arch/xtensa/configs/kabylake_defconfig delete mode 100644 src/arch/xtensa/configs/skylake_defconfig delete mode 100644 src/platform/apollolake/CMakeLists.txt delete mode 100644 src/platform/apollolake/apollolake.x.in delete mode 100644 src/platform/apollolake/base_module.c delete mode 100644 src/platform/apollolake/boot_ldr.x.in delete mode 100644 src/platform/apollolake/boot_module.c delete mode 100644 src/platform/apollolake/include/arch/xtensa/config/core-isa.h delete mode 100644 src/platform/apollolake/include/arch/xtensa/config/core-matmap.h delete mode 100644 src/platform/apollolake/include/arch/xtensa/config/defs.h delete mode 100644 src/platform/apollolake/include/arch/xtensa/config/specreg.h delete mode 100644 src/platform/apollolake/include/arch/xtensa/config/system.h delete mode 100644 src/platform/apollolake/include/arch/xtensa/config/tie-asm.h delete mode 100644 src/platform/apollolake/include/arch/xtensa/config/tie.h delete mode 100644 src/platform/apollolake/include/platform/drivers/dw-dma.h delete mode 100644 src/platform/apollolake/include/platform/drivers/idc.h delete mode 100644 src/platform/apollolake/include/platform/drivers/interrupt.h delete mode 100644 src/platform/apollolake/include/platform/drivers/mn.h delete mode 100644 src/platform/apollolake/include/platform/drivers/timestamp.h delete mode 100644 src/platform/apollolake/include/platform/lib/asm_ldo_management.h delete mode 100644 src/platform/apollolake/include/platform/lib/asm_memory_management.h delete mode 100644 src/platform/apollolake/include/platform/lib/clk.h delete mode 100644 src/platform/apollolake/include/platform/lib/cpu.h delete mode 100644 src/platform/apollolake/include/platform/lib/dai.h delete mode 100644 src/platform/apollolake/include/platform/lib/dma.h delete mode 100644 src/platform/apollolake/include/platform/lib/mailbox.h delete mode 100644 src/platform/apollolake/include/platform/lib/memory.h delete mode 100644 src/platform/apollolake/include/platform/lib/pm_runtime.h delete mode 100644 src/platform/apollolake/include/platform/lib/shim.h delete mode 100644 src/platform/apollolake/include/platform/platform.h delete mode 100644 src/platform/apollolake/include/platform/trace/trace.h delete mode 100644 src/platform/apollolake/lib/CMakeLists.txt delete mode 100644 src/platform/apollolake/lib/clk.c delete mode 100644 src/platform/apollolake/lib/power_down.S delete mode 100644 src/platform/apollolake/rom.x.in delete mode 100644 tools/topology/topology1/development/sof-apl-asrc-pcm512x.m4 delete mode 100644 tools/topology/topology1/development/sof-apl-asrc-wm8804.m4 delete mode 100644 tools/topology/topology1/development/sof-apl-dmic-a96k-b16k.m4 delete mode 100644 tools/topology/topology1/development/sof-apl-dmic-asymmetric.m4 delete mode 100644 tools/topology/topology1/development/sof-apl-dmic.m4 delete mode 100644 tools/topology/topology1/development/sof-apl-nocodec-ci.m4 delete mode 100644 tools/topology/topology1/development/sof-apl-nocodec-demux-eq-2ch4ch.m4 delete mode 100644 tools/topology/topology1/development/sof-apl-nocodec-demux-eq-4ch4ch.m4 delete mode 100644 tools/topology/topology1/development/sof-apl-pcm512x-nohdmi.m4 delete mode 100644 tools/topology/topology1/development/sof-apl-src-50khz-pcm512x.m4 delete mode 100644 tools/topology/topology1/development/sof-apl-src-pcm512x.m4 delete mode 100644 tools/topology/topology1/platform/intel/apl-dmic-a2b2.m4 delete mode 100644 tools/topology/topology1/platform/intel/apl-dmic-a2b4.m4 delete mode 100644 tools/topology/topology1/platform/intel/apl-dmic-a4b2.m4 delete mode 100644 tools/topology/topology1/platform/intel/glk-da7219.m4 delete mode 100644 tools/topology/topology1/sof-apl-da7219.m4 delete mode 100644 tools/topology/topology1/sof-apl-demux-pcm512x.m4 delete mode 100644 tools/topology/topology1/sof-apl-keyword-detect.m4 delete mode 100644 tools/topology/topology1/sof-apl-pcm512x.m4 delete mode 100644 tools/topology/topology1/sof-apl-rt298.m4 delete mode 100644 tools/topology/topology1/sof-apl-tdf8532.m4 delete mode 100644 tools/topology/topology1/sof-apl-wm8804.m4 delete mode 100644 tools/topology/topology1/sof-glk-da7219.m4 delete mode 100644 tools/topology/topology1/sof-glk-rt5682.m4 diff --git a/app/boards/intel_adsp_cavs15.conf b/app/boards/intel_adsp_cavs15.conf deleted file mode 100644 index 793ea566f5db..000000000000 --- a/app/boards/intel_adsp_cavs15.conf +++ /dev/null @@ -1,8 +0,0 @@ -CONFIG_APOLLOLAKE=y -CONFIG_INTEL_DMIC=y -CONFIG_DMIC_HW_IOCLK=19200000 -CONFIG_INTEL_SSP=y -CONFIG_LP_MEMORY_BANKS=2 -CONFIG_HP_MEMORY_BANKS=8 -CONFIG_PERFORMANCE_COUNTERS=y -CONFIG_COMP_SRC_TINY=y diff --git a/installer/GNUmakefile b/installer/GNUmakefile index 4d122cdda3eb..4d5762c9062d 100644 --- a/installer/GNUmakefile +++ b/installer/GNUmakefile @@ -39,7 +39,6 @@ $(info UNSIGNED_list = ${UNSIGNED_list} ) $(info SIGNED_list = ${SIGNED_list} ) $(info ALIAS_list = ${ALIAS_list} ) -target_of_glk := apl target_of_cfl := cnl target_of_cml := cnl @@ -312,10 +311,10 @@ COMPARE_REFS ?= /lib/firmware/intel checktree: cd ${STAGING_SOF_VERSION} && \ tree -a -v --dirsfirst . > ${BUILDS_ROOT}/staging_sof_tree.txt - # Update sof-apl-nocodec.tplg when adding or removing a default platform + # Update sof-cavs-nocodec.tplg when adding or removing a default platform diff -u tests/staging_sof${IPC_VERSION}_ref.txt ${BUILDS_ROOT}/staging_sof_tree.txt # Check two random topologies are there - test -f ${STAGING_SOF_TPLG}/sof-apl-nocodec.tplg + test -f ${STAGING_SOF_TPLG}/sof-tgl-nocodec.tplg test -f ${STAGING_SOF_TPLG}/sof-imx8-wm8960.tplg for t in sof-ctl sof-logger sof-probes; do \ test -f ${STAGING_TOOLS}${VERSION_SUFFIX}/$${t}; done diff --git a/scripts/cmake/xtensa-toolchain.cmake b/scripts/cmake/xtensa-toolchain.cmake index 75414f2b4fe4..3e070f7f6982 100644 --- a/scripts/cmake/xtensa-toolchain.cmake +++ b/scripts/cmake/xtensa-toolchain.cmake @@ -6,7 +6,7 @@ else() " Please specify toolchain to use.\n" " Examples:\n" " 1) cmake -DTOOLCHAIN=xt ...\n" - " 2) cmake -DTOOLCHAIN=xtensa-apl-elf ...\n" + " 2) cmake -DTOOLCHAIN=xtensa-cnl-elf ...\n" ) endif() diff --git a/scripts/docker_build/sof_builder/Dockerfile b/scripts/docker_build/sof_builder/Dockerfile index 07efb57be9b3..48faf9bcb2aa 100644 --- a/scripts/docker_build/sof_builder/Dockerfile +++ b/scripts/docker_build/sof_builder/Dockerfile @@ -88,7 +88,7 @@ RUN cd "$HOME" && \ git clone $CLONE_DEFAULTS --branch sof-gcc10x $CT_NG_REPO && \ cd crosstool-ng && \ ./bootstrap && ./configure --prefix=`pwd` && make && make install && \ - for arch in apl cnl imx imx8m imx8ulp rn rmb mt8186 mt8195; do \ + for arch in cnl imx imx8m imx8ulp rn rmb mt8186 mt8195; do \ echo "$arch: ct-ng build start..." && \ cp config-${arch}-gcc10.2-gdb9 .config && \ # replace the build dist to save space @@ -99,7 +99,6 @@ RUN cd "$HOME" && \ done && \ echo "Stage2: xtensa-overlay, crosstool-ng are done!" -ENV PATH="/home/sof/work/xtensa-apl-elf/bin:${PATH}" ENV PATH="/home/sof/work/xtensa-cnl-elf/bin:${PATH}" ENV PATH="/home/sof/work/xtensa-rn-elf/bin:${PATH}" ENV PATH="/home/sof/work/xtensa-rmb-elf/bin:${PATH}" @@ -113,7 +112,7 @@ ARG NEWLIB_REPO=https://github.com/jcmvbkbc/newlib-xtensa.git RUN cd "$HOME" && \ git clone $CLONE_DEFAULTS --branch xtensa $NEWLIB_REPO && \ cd newlib-xtensa && \ - for arch in apl cnl imx imx8m imx8ulp rn rmb mt8186 mt8195; do \ + for arch in cnl imx imx8m imx8ulp rn rmb mt8186 mt8195; do \ ./configure --target=xtensa-${arch}-elf \ --prefix=/home/sof/work/xtensa-root && \ make && make install && \ diff --git a/scripts/qemu-check.sh b/scripts/qemu-check.sh index 0775e502dc14..9bfcfd67fd88 100755 --- a/scripts/qemu-check.sh +++ b/scripts/qemu-check.sh @@ -3,7 +3,7 @@ # Copyright(c) 2018 Intel Corporation. All rights reserved. set -e -SUPPORTED_PLATFORMS=(apl icl skl kbl cnl imx8 imx8x imx8m) +SUPPORTED_PLATFORMS=(icl cnl imx8 imx8x imx8m) SOF_DIR=$(cd "$(dirname "$0")" && cd .. && pwd) @@ -81,32 +81,6 @@ do has_rom=false case "$platform" in - apl) - # This READY_IPC value comes from: - # ipc_write(IPC_DIPCIDR, IPC_DIPCIDR_BUSY | header); - # header = FE_READY = 0x7 - # IPC_DIPCIDR_BUSY = BIT(31) - # So "00 00 00 f0" is just "F0000000" - READY_IPC="00 00 00 f0" - SHM_IPC_REG="qemu-bridge-ipc(|-dsp)-io" - OUTBOX_OFFSET="7000" - SHM_MBOX=qemu-bridge-hp-sram-mem - has_rom=true - ;; - skl) - READY_IPC="00 00 00 f0" - SHM_IPC_REG="qemu-bridge-ipc(|-dsp)-io" - OUTBOX_OFFSET="7000" - SHM_MBOX=qemu-bridge-hp-sram-mem - has_rom=true - ;; - kbl) - READY_IPC="00 00 00 f0" - SHM_IPC_REG="qemu-bridge-ipc(|-dsp)-io" - OUTBOX_OFFSET="7000" - SHM_MBOX=qemu-bridge-hp-sram-mem - has_rom=true - ;; cnl) READY_IPC="00 00 00 f0" SHM_IPC_REG="qemu-bridge-ipc(|-dsp)-io" diff --git a/scripts/scan/clang-scan-build-xtensa.sh b/scripts/scan/clang-scan-build-xtensa.sh index 5bf97d044af2..1c8cd27f2ec6 100755 --- a/scripts/scan/clang-scan-build-xtensa.sh +++ b/scripts/scan/clang-scan-build-xtensa.sh @@ -15,7 +15,7 @@ function usage { echo " [-j n] Set number of make build jobs." echo " [-v] Verbose output." echo "Examples:" - echo " $0 -t xt -c apollolake \\" + echo " $0 -t xt -c tigerlake \\" echo " -r \$CONFIG_PATH/xtensa-elf" echo " $0 -t xtensa-cnl-elf -c cannonlake \\" echo " -r \`pwd\`/../xtensa-cnl-elf" diff --git a/scripts/xtensa-build-all.sh b/scripts/xtensa-build-all.sh index 7571b5ce8c4e..4d1bd510a9f5 100755 --- a/scripts/xtensa-build-all.sh +++ b/scripts/xtensa-build-all.sh @@ -24,7 +24,7 @@ SUPPORTED_PLATFORMS+=( mt8188 ) # Not actually "supported" in the main branch anymore (go to stable-v2.3 # instead) but kept here for historical reasons and experimentation # convenience. -SUPPORTED_PLATFORMS+=( apl skl kbl cnl icl jsl ) +SUPPORTED_PLATFORMS+=( cnl icl jsl ) BUILD_ROM=no BUILD_DEBUG=no @@ -204,48 +204,6 @@ do PLATFORM_PRIVATE_KEY='' case $platform in - apl) - PLATFORM="apollolake" - XTENSA_CORE="X4H3I16w2D48w3a_2017_8" - - # test APL compiler aliases - if command -v xtensa-bxt-elf-gcc; then - HOST="xtensa-bxt-elf" - else - HOST="xtensa-apl-elf" - fi - - XTENSA_TOOLS_VERSION="RG-2017.8-linux" - HAVE_ROM='yes' - ;; - skl) - PLATFORM="skylake" - XTENSA_CORE="X4H3I16w2D48w3a_2017_8" - - # test APL compiler aliases - if command -v xtensa-bxt-elf-gcc; then - HOST="xtensa-bxt-elf" - else - HOST="xtensa-apl-elf" - fi - - XTENSA_TOOLS_VERSION="RG-2017.8-linux" - HAVE_ROM='yes' - ;; - kbl) - PLATFORM="kabylake" - XTENSA_CORE="X4H3I16w2D48w3a_2017_8" - - # test APL compiler aliases - if command -v xtensa-bxt-elf-gcc; then - HOST="xtensa-bxt-elf" - else - HOST="xtensa-apl-elf" - fi - - XTENSA_TOOLS_VERSION="RG-2017.8-linux" - HAVE_ROM='yes' - ;; cnl) PLATFORM="cannonlake" XTENSA_CORE="X6H3CNL_2017_8" diff --git a/scripts/xtensa-build-zephyr.py b/scripts/xtensa-build-zephyr.py index a3a4a3b94351..ca2b070ad51f 100755 --- a/scripts/xtensa-build-zephyr.py +++ b/scripts/xtensa-build-zephyr.py @@ -72,13 +72,6 @@ platform_list = [ # Intel platforms - { - "name": "apl", - "PLAT_CONFIG": "intel_adsp_cavs15", - "XTENSA_CORE": "X4H3I16w2D48w3a_2017_8", - "XTENSA_TOOLS_VERSION": f"RG-2017.8{xtensa_tools_version_postfix}", - "DEFAULT_TOOLCHAIN_VARIANT": "xcc" - }, { "name": "cnl", "PLAT_CONFIG": "intel_adsp_cavs18", diff --git a/src/arch/xtensa/CMakeLists.txt b/src/arch/xtensa/CMakeLists.txt index 8bc54a8a0150..85e1f5e4eb76 100644 --- a/src/arch/xtensa/CMakeLists.txt +++ b/src/arch/xtensa/CMakeLists.txt @@ -2,9 +2,7 @@ # platform-specific values -if(CONFIG_APOLLOLAKE) - set(platform_folder apollolake) -elseif(CONFIG_CANNONLAKE) +if(CONFIG_CANNONLAKE) set(platform_folder cannonlake) elseif(CONFIG_ICELAKE) set(platform_folder icelake) @@ -546,10 +544,6 @@ list(APPEND UNSIGNED_RI rn rmb) # MediaTek list(APPEND UNSIGNED_RI mt8186 mt8188 mt8195) -# Signed and non-deterministic but sof_ri_info.py is not compatible with -# manifest v1.5? "CSE manifest magic number not found" -set(UNSUPPORTED_RI skl kbl) - if(${fw_name} IN_LIST UNSIGNED_RI) # mere copy add_custom_command(OUTPUT reproducible.ri COMMENT "Copying sof.ri to reproducible.ri as is" @@ -559,13 +553,6 @@ if(${fw_name} IN_LIST UNSIGNED_RI) # mere copy COMMAND cmake -E copy sof-${fw_name}.ri reproducible.ri VERBATIM ) -elseif(${fw_name} IN_LIST UNSUPPORTED_RI) - add_custom_command(OUTPUT reproducible.ri - COMMENT "WARNING: sof-${fw_name}.ri is NOT reproducible, reproducible.ri is fake" - DEPENDS glue_binary_files sof-${fw_name}.ri - COMMAND cmake -E touch reproducible.ri - VERBATIM - ) else() # strip variables add_custom_command(OUTPUT reproducible.ri COMMENT "Creating reproducible.ri" diff --git a/src/arch/xtensa/configs/apollolake_defconfig b/src/arch/xtensa/configs/apollolake_defconfig deleted file mode 100644 index e5316a95913a..000000000000 --- a/src/arch/xtensa/configs/apollolake_defconfig +++ /dev/null @@ -1,11 +0,0 @@ -CONFIG_APOLLOLAKE=y -CONFIG_INTEL_DMIC=y -CONFIG_DMIC_HW_IOCLK=19200000 -CONFIG_INTEL_SSP=y -CONFIG_CORE_COUNT=1 -CONFIG_LP_MEMORY_BANKS=2 -CONFIG_HP_MEMORY_BANKS=8 -CONFIG_PERFORMANCE_COUNTERS=y -CONFIG_COMP_SRC_SMALL=y -CONFIG_COMP_TDFB=n -CONFIG_COMP_TONE=n diff --git a/src/arch/xtensa/configs/kabylake_defconfig b/src/arch/xtensa/configs/kabylake_defconfig deleted file mode 100644 index 8303302b1c86..000000000000 --- a/src/arch/xtensa/configs/kabylake_defconfig +++ /dev/null @@ -1,6 +0,0 @@ -CONFIG_APOLLOLAKE=y -CONFIG_RIMAGE_SIGNING_SCHEMA="kbl" -CONFIG_INTEL_DMIC=y -CONFIG_INTEL_SSP=y -CONFIG_LP_MEMORY_BANKS=2 -CONFIG_HP_MEMORY_BANKS=30 diff --git a/src/arch/xtensa/configs/skylake_defconfig b/src/arch/xtensa/configs/skylake_defconfig deleted file mode 100644 index 641bd643d226..000000000000 --- a/src/arch/xtensa/configs/skylake_defconfig +++ /dev/null @@ -1,6 +0,0 @@ -CONFIG_APOLLOLAKE=y -CONFIG_RIMAGE_SIGNING_SCHEMA="skl" -CONFIG_INTEL_DMIC=y -CONFIG_INTEL_SSP=y -CONFIG_LP_MEMORY_BANKS=2 -CONFIG_HP_MEMORY_BANKS=30 diff --git a/src/arch/xtensa/xtos/reset-vector.S b/src/arch/xtensa/xtos/reset-vector.S index d74964c65497..7848a79b748f 100644 --- a/src/arch/xtensa/xtos/reset-vector.S +++ b/src/arch/xtensa/xtos/reset-vector.S @@ -339,17 +339,7 @@ _ResetHandler: #if XCHAL_HAVE_PREFETCH /* Enable cache prefetch if present. */ -#if CONFIG_APOLLOLAKE - -#if CONFIG_SKYLAKE || CONFIG_KABYLAKE - movi.n a2, 0 /* skylake and kabylake */ -#else - movi.n a2, 34 /* apollolake */ -#endif - -#else - movi.n a2, 68 /* eveything else */ -#endif + movi.n a2, 68 wsr a2, PREFCTL #endif diff --git a/src/audio/Kconfig b/src/audio/Kconfig index 6bb6b229d88f..f61c9b093003 100644 --- a/src/audio/Kconfig +++ b/src/audio/Kconfig @@ -255,7 +255,7 @@ config COMP_DCBLOCK the DC offset which often originates from a microphone's output. config MAXIM_DSM - depends on CAVS && !CAVS_VERSION_1_5 + depends on CAVS bool "Maxim DSM component" select COMP_BLOB default n diff --git a/src/drivers/intel/cavs/ipc.c b/src/drivers/intel/cavs/ipc.c index 0744dc10dbd6..f5d6dace21db 100644 --- a/src/drivers/intel/cavs/ipc.c +++ b/src/drivers/intel/cavs/ipc.c @@ -60,39 +60,21 @@ static void ipc_irq_handler(void *arg) { struct ipc *ipc = arg; uint32_t dipcctl; + uint32_t dipctdr; + uint32_t dipcida; k_spinlock_key_t key; key = k_spin_lock(&ipc->lock); -#if CAVS_VERSION == CAVS_VERSION_1_5 - uint32_t dipct; - uint32_t dipcie; - - dipct = ipc_read(IPC_DIPCT); - dipcie = ipc_read(IPC_DIPCIE); - dipcctl = ipc_read(IPC_DIPCCTL); - - tr_dbg(&ipc_tr, "ipc: irq dipct 0x%x dipcie 0x%x dipcctl 0x%x", dipct, - dipcie, dipcctl); -#else - uint32_t dipctdr; - uint32_t dipcida; - dipctdr = ipc_read(IPC_DIPCTDR); dipcida = ipc_read(IPC_DIPCIDA); dipcctl = ipc_read(IPC_DIPCCTL); tr_dbg(&ipc_tr, "ipc: irq dipctdr 0x%x dipcida 0x%x dipcctl 0x%x", dipctdr, dipcida, dipcctl); -#endif /* new message from host */ -#if CAVS_VERSION == CAVS_VERSION_1_5 - if (dipct & IPC_DIPCT_BUSY && dipcctl & IPC_DIPCCTL_IPCTBIE) -#else - if (dipctdr & IPC_DIPCTDR_BUSY && dipcctl & IPC_DIPCCTL_IPCTBIE) -#endif - { + if (dipctdr & IPC_DIPCTDR_BUSY && dipcctl & IPC_DIPCCTL_IPCTBIE) { /* mask Busy interrupt */ ipc_write(IPC_DIPCCTL, dipcctl & ~IPC_DIPCCTL_IPCTBIE); @@ -104,24 +86,14 @@ static void ipc_irq_handler(void *arg) } /* reply message(done) from host */ -#if CAVS_VERSION == CAVS_VERSION_1_5 - if (dipcie & IPC_DIPCIE_DONE && dipcctl & IPC_DIPCCTL_IPCIDIE) -#else - if (dipcida & IPC_DIPCIDA_DONE) -#endif - { + if (dipcida & IPC_DIPCIDA_DONE) { /* mask Done interrupt */ ipc_write(IPC_DIPCCTL, ipc_read(IPC_DIPCCTL) & ~IPC_DIPCCTL_IPCIDIE); /* clear DONE bit - tell host we have completed the operation */ -#if CAVS_VERSION == CAVS_VERSION_1_5 - ipc_write(IPC_DIPCIE, - ipc_read(IPC_DIPCIE) | IPC_DIPCIE_DONE); -#else ipc_write(IPC_DIPCIDA, ipc_read(IPC_DIPCIDA) | IPC_DIPCIDA_DONE); -#endif ipc->is_notification_pending = false; @@ -133,7 +105,6 @@ static void ipc_irq_handler(void *arg) k_spin_unlock(&ipc->lock, key); } -#if CAVS_VERSION >= CAVS_VERSION_1_8 int ipc_platform_compact_read_msg(struct ipc_cmd_hdr *hdr, int words) { uint32_t *chdr = (uint32_t *)hdr; @@ -163,27 +134,11 @@ int ipc_platform_compact_write_msg(struct ipc_cmd_hdr *hdr, int words) return 2; /* number of words written */ } -#else -int ipc_platform_compact_write_msg(struct ipc_cmd_hdr *hdr, int words) -{ - return 0; /* number of words written - not used on CAVS1.5 */ -} - -int ipc_platform_compact_read_msg(struct ipc_cmd_hdr *hdr, int words) -{ - return 0; /* number of words read - not used on CAVS1.5 */ -} -#endif - enum task_state ipc_platform_do_cmd(struct ipc *ipc) { struct ipc_cmd_hdr *hdr; -#if CAVS_VERSION >= CAVS_VERSION_1_8 hdr = ipc_compact_read_msg(); -#else - hdr = mailbox_validate(); -#endif /* perform command */ ipc_cmd(hdr); @@ -201,12 +156,8 @@ enum task_state ipc_platform_do_cmd(struct ipc *ipc) void ipc_platform_complete_cmd(struct ipc *ipc) { /* write 1 to clear busy, and trigger interrupt to host*/ -#if CAVS_VERSION == CAVS_VERSION_1_5 - ipc_write(IPC_DIPCT, ipc_read(IPC_DIPCT) | IPC_DIPCT_BUSY); -#else ipc_write(IPC_DIPCTDR, ipc_read(IPC_DIPCTDR) | IPC_DIPCTDR_BUSY); ipc_write(IPC_DIPCTDA, ipc_read(IPC_DIPCTDA) | IPC_DIPCTDA_DONE); -#endif #if CONFIG_DEBUG_IPC_COUNTERS increment_ipc_processed_counter(); @@ -222,14 +173,9 @@ int ipc_platform_send_msg(const struct ipc_msg *msg) struct ipc_cmd_hdr *hdr; if (ipc->is_notification_pending || -#if CAVS_VERSION == CAVS_VERSION_1_5 - ipc_read(IPC_DIPCI) & IPC_DIPCI_BUSY) { -#else ipc_read(IPC_DIPCIDR) & IPC_DIPCIDR_BUSY || - ipc_read(IPC_DIPCIDA) & IPC_DIPCIDA_DONE) { -#endif + ipc_read(IPC_DIPCIDA) & IPC_DIPCIDA_DONE) return -EBUSY; - } tr_dbg(&ipc_tr, "ipc: msg tx -> 0x%x", msg->header); @@ -240,21 +186,11 @@ int ipc_platform_send_msg(const struct ipc_msg *msg) /* now interrupt host to tell it we have message sent */ #if CONFIG_IPC_MAJOR_3 -#if CAVS_VERSION == CAVS_VERSION_1_5 - ipc_write(IPC_DIPCIE, hdr->dat[1]); - ipc_write(IPC_DIPCI, IPC_DIPCI_BUSY | hdr->dat[0]); -#else ipc_write(IPC_DIPCIDD, hdr->dat[1]); ipc_write(IPC_DIPCIDR, IPC_DIPCIDR_BUSY | hdr->dat[0]); -#endif #elif CONFIG_IPC_MAJOR_4 -#if CAVS_VERSION == CAVS_VERSION_1_5 - ipc_write(IPC_DIPCIE, hdr->ext); - ipc_write(IPC_DIPCI, IPC_DIPCI_BUSY | hdr->pri); -#else ipc_write(IPC_DIPCIDD, hdr->ext); ipc_write(IPC_DIPCIDR, IPC_DIPCIDR_BUSY | hdr->pri); -#endif #endif return 0; @@ -296,12 +232,8 @@ void ipc_platform_poll_set_cmd_done(void) { /* write 1 to clear busy, and trigger interrupt to host*/ -#if CAVS_VERSION == CAVS_VERSION_1_5 - ipc_write(IPC_DIPCT, ipc_read(IPC_DIPCT) | IPC_DIPCT_BUSY); -#else ipc_write(IPC_DIPCTDR, ipc_read(IPC_DIPCTDR) | IPC_DIPCTDR_BUSY); ipc_write(IPC_DIPCTDA, ipc_read(IPC_DIPCTDA) | IPC_DIPCTDA_DONE); -#endif /* unmask Busy interrupt */ ipc_write(IPC_DIPCCTL, ipc_read(IPC_DIPCCTL) | IPC_DIPCCTL_IPCTBIE); @@ -311,27 +243,13 @@ void ipc_platform_poll_set_cmd_done(void) int ipc_platform_poll_is_cmd_pending(void) { uint32_t dipcctl; - -#if CAVS_VERSION == CAVS_VERSION_1_5 - uint32_t dipct; - - dipct = ipc_read(IPC_DIPCT); - dipcctl = ipc_read(IPC_DIPCCTL); - -#else uint32_t dipctdr; dipctdr = ipc_read(IPC_DIPCTDR); dipcctl = ipc_read(IPC_DIPCCTL); -#endif /* new message from host */ -#if CAVS_VERSION == CAVS_VERSION_1_5 - if (dipct & IPC_DIPCT_BUSY && dipcctl & IPC_DIPCCTL_IPCTBIE) -#else - if (dipctdr & IPC_DIPCTDR_BUSY && dipcctl & IPC_DIPCCTL_IPCTBIE) -#endif - { + if (dipctdr & IPC_DIPCTDR_BUSY && dipcctl & IPC_DIPCCTL_IPCTBIE) { /* mask Busy interrupt */ ipc_write(IPC_DIPCCTL, dipcctl & ~IPC_DIPCCTL_IPCTBIE); @@ -345,38 +263,19 @@ int ipc_platform_poll_is_cmd_pending(void) int ipc_platform_poll_is_host_ready(void) { -#if CAVS_VERSION == CAVS_VERSION_1_5 - uint32_t dipcie; - uint32_t dipcctl; - - dipcie = ipc_read(IPC_DIPCIE); - dipcctl = ipc_read(IPC_DIPCCTL); - -#else uint32_t dipcida; dipcida = ipc_read(IPC_DIPCIDA); -#endif /* reply message(done) from host */ -#if CAVS_VERSION == CAVS_VERSION_1_5 - if (dipcie & IPC_DIPCIE_DONE && dipcctl & IPC_DIPCCTL_IPCIDIE) -#else - if (dipcida & IPC_DIPCIDA_DONE) -#endif - { + if (dipcida & IPC_DIPCIDA_DONE) { /* mask Done interrupt */ ipc_write(IPC_DIPCCTL, ipc_read(IPC_DIPCCTL) & ~IPC_DIPCCTL_IPCIDIE); /* clear DONE bit - tell host we have completed the operation */ -#if CAVS_VERSION == CAVS_VERSION_1_5 - ipc_write(IPC_DIPCIE, - ipc_read(IPC_DIPCIE) | IPC_DIPCIE_DONE); -#else ipc_write(IPC_DIPCIDA, ipc_read(IPC_DIPCIDA) | IPC_DIPCIDA_DONE); -#endif /* unmask Done interrupt */ ipc_write(IPC_DIPCCTL, @@ -393,12 +292,8 @@ int ipc_platform_poll_is_host_ready(void) int ipc_platform_poll_tx_host_msg(struct ipc_msg *msg) { -#if CAVS_VERSION == CAVS_VERSION_1_5 - if (ipc_read(IPC_DIPCI) & IPC_DIPCI_BUSY) -#else if (ipc_read(IPC_DIPCIDR) & IPC_DIPCIDR_BUSY || ipc_read(IPC_DIPCIDA) & IPC_DIPCIDA_DONE) -#endif /* cant send message atm */ return 0; @@ -406,13 +301,8 @@ int ipc_platform_poll_tx_host_msg(struct ipc_msg *msg) mailbox_dspbox_write(0, msg->tx_data, msg->tx_size); /* now interrupt host to tell it we have message sent */ -#if CAVS_VERSION == CAVS_VERSION_1_5 - ipc_write(IPC_DIPCIE, 0); - ipc_write(IPC_DIPCI, IPC_DIPCI_BUSY | msg->header); -#else ipc_write(IPC_DIPCIDD, 0); ipc_write(IPC_DIPCIDR, IPC_DIPCIDR_BUSY | msg->header); -#endif /* message sent */ return 1; diff --git a/src/drivers/intel/cavs/timestamp.c b/src/drivers/intel/cavs/timestamp.c index b220d88bf356..eee54cb21b0e 100644 --- a/src/drivers/intel/cavs/timestamp.c +++ b/src/drivers/intel/cavs/timestamp.c @@ -170,42 +170,17 @@ int timestamp_dmic_get(struct dai *dai, struct timestamp_cfg *cfg, static uint32_t ssp_ts_local_tsctrl_addr(int index) { -#if CONFIG_APOLLOLAKE - /* TSCTRL registers for SSP0, 1, 2, and 3 are in continuous - * registers space while SSP4 and more are handled with other - * macro. - */ - if (index < DAI_NUM_SSP_BASE) - return TIMESTAMP_BASE + TS_I2S_LOCAL_TSCTRL(index); - else - return TIMESTAMP_BASE + TS_I2SE_LOCAL_TSCTRL(index); -#else return TIMESTAMP_BASE + TS_I2S_LOCAL_TSCTRL(index); -#endif } static uint32_t ssp_ts_local_sample_addr(int index) { -#if CONFIG_APOLLOLAKE - if (index < DAI_NUM_SSP_BASE) - return TIMESTAMP_BASE + TS_I2S_LOCAL_SAMPLE(index); - else - return TIMESTAMP_BASE + TS_I2SE_LOCAL_SAMPLE(index); -#else return TIMESTAMP_BASE + TS_I2S_LOCAL_SAMPLE(index); -#endif } static uint32_t ssp_ts_local_walclk_addr(int index) { -#if CONFIG_APOLLOLAKE - if (index < DAI_NUM_SSP_BASE) - return TIMESTAMP_BASE + TS_I2S_LOCAL_WALCLK(index); - else - return TIMESTAMP_BASE + TS_I2SE_LOCAL_WALCLK(index); -#else return TIMESTAMP_BASE + TS_I2S_LOCAL_WALCLK(index); -#endif } int timestamp_ssp_config(struct dai *dai, struct timestamp_cfg *cfg) diff --git a/src/include/sof/drivers/dmic.h b/src/include/sof/drivers/dmic.h index 3dcdb7be5634..1f5ca187d812 100644 --- a/src/include/sof/drivers/dmic.h +++ b/src/include/sof/drivers/dmic.h @@ -35,12 +35,6 @@ #define DMIC_UNMUTE_CIC 1 /* Unmute CIC at 1 ms */ #define DMIC_UNMUTE_FIR 2 /* Unmute FIR at 2 ms */ -#if CONFIG_APOLLOLAKE -#define DMIC_HW_VERSION 1 -#define DMIC_HW_CONTROLLERS 2 -#define DMIC_HW_FIFOS 2 -#endif - #if CONFIG_CANNONLAKE #define DMIC_HW_VERSION 1 #define DMIC_HW_CONTROLLERS 2 diff --git a/src/ipc/ipc3/handler.c b/src/ipc/ipc3/handler.c index f411272e6572..7d42b58d8ca2 100644 --- a/src/ipc/ipc3/handler.c +++ b/src/ipc/ipc3/handler.c @@ -66,7 +66,7 @@ LOG_MODULE_DECLARE(ipc, CONFIG_SOF_LOG_LEVEL); -#if CONFIG_CAVS && CAVS_VERSION >= CAVS_VERSION_1_8 +#if CONFIG_CAVS #include #include #define CAVS_IPC_TYPE_S(x) ((x) & CAVS_IPC_TYPE_MASK) @@ -1545,7 +1545,7 @@ static int ipc_glb_test_message(uint32_t header) } #endif -#if CONFIG_CAVS && CAVS_VERSION >= CAVS_VERSION_1_8 +#if CONFIG_CAVS static struct ipc_cmd_hdr *ipc_cavs_read_set_d0ix(struct ipc_cmd_hdr *hdr) { struct sof_ipc_pm_gate *cmd = ipc_get()->comp_data; diff --git a/src/platform/CMakeLists.txt b/src/platform/CMakeLists.txt index 253429583623..e3d4a6206844 100644 --- a/src/platform/CMakeLists.txt +++ b/src/platform/CMakeLists.txt @@ -5,9 +5,7 @@ if(CONFIG_LIBRARY) return() endif() -if(CONFIG_APOLLOLAKE) - add_subdirectory(apollolake) -elseif(CONFIG_CANNONLAKE) +if(CONFIG_CANNONLAKE) add_subdirectory(cannonlake) elseif(CONFIG_ICELAKE) add_subdirectory(icelake) diff --git a/src/platform/Kconfig b/src/platform/Kconfig index 13ac3c41f149..2529731ff0aa 100644 --- a/src/platform/Kconfig +++ b/src/platform/Kconfig @@ -7,21 +7,6 @@ choice default ZEPHYR_POSIX if ARCH_POSIX default TIGERLAKE -config APOLLOLAKE - bool "Build for Apollolake" - select XT_BOOT_LOADER - select XT_IRQ_MAP - select DMA_GW - select DW - select DW_DMA - select MEM_WND - select DMA_HW_LLI - select DMA_FIFO_PARTITION - select CAVS - select CAVS_VERSION_1_5 - help - Select if your target platform is Apollolake-compatible - config CANNONLAKE bool "Build for Cannonlake" select XT_BOOT_LOADER @@ -239,7 +224,6 @@ endchoice config MAX_CORE_COUNT int - default 2 if APOLLOLAKE default 4 if ICELAKE || CANNONLAKE || TIGERLAKE default 3 if METEORLAKE default 1 @@ -300,27 +284,20 @@ config CAVS select WAKEUP_HOOK select SCHEDULE_DMA_SINGLE_CHANNEL -config CAVS_VERSION_1_5 - depends on CAVS - bool - help - Select for CAVS version 1.5 - config CAVS_VERSION_1_8 - depends on CAVS && !CAVS_VERSION_1_5 + depends on CAVS bool help Select for CAVS version 1.8 config CAVS_VERSION_2_0 - depends on CAVS && !CAVS_VERSION_1_5 && !CAVS_VERSION_1_8 + depends on CAVS && !CAVS_VERSION_1_8 bool help Select for CAVS version 2.0 config CAVS_VERSION_2_5 - depends on CAVS && !CAVS_VERSION_1_5 && !CAVS_VERSION_1_8 \ - && !CAVS_VERSION_2_0 + depends on CAVS && !CAVS_VERSION_1_8 && !CAVS_VERSION_2_0 bool help Select for CAVS version 2.5 @@ -397,7 +374,7 @@ config CAVS_LPS config CAVS_LPRO_ONLY bool "Use low power ring oscillator always" default n - depends on CAVS && !CAVS_VERSION_1_5 + depends on CAVS help Select if you want to use only the 120MHz LPRO as the DSP clock source. This option is for debugging only at the moment, choose n if unclear. @@ -424,7 +401,7 @@ config L3_HEAP config CAVS_IMR_D3_PERSISTENT bool "Intel IMR content persistent on DSP in D3" - depends on CAVS && !CAVS_VERSION_1_5 + depends on CAVS default y help Select this if the Intel cAVS platform can keep the @@ -437,7 +414,6 @@ config CAVS_IMR_D3_PERSISTENT # TODO: it should just take manifest version and offsets config RIMAGE_SIGNING_SCHEMA string "Rimage firmware signing schema name" - default "apl" if APOLLOLAKE default "cnl" if CANNONLAKE default "icl" if ICELAKE default "tgl" if TIGERLAKE diff --git a/src/platform/apollolake/CMakeLists.txt b/src/platform/apollolake/CMakeLists.txt deleted file mode 100644 index d7462e527e47..000000000000 --- a/src/platform/apollolake/CMakeLists.txt +++ /dev/null @@ -1,12 +0,0 @@ -# SPDX-License-Identifier: BSD-3-Clause - -add_subdirectory(lib) - -add_executable(boot_module boot_module.c) -add_executable(base_module base_module.c) - -target_link_libraries(boot_module sof_options) -target_link_libraries(base_module sof_options) - -sof_append_relative_path_definitions(boot_module) -sof_append_relative_path_definitions(base_module) diff --git a/src/platform/apollolake/apollolake.x.in b/src/platform/apollolake/apollolake.x.in deleted file mode 100644 index 6686b97fec43..000000000000 --- a/src/platform/apollolake/apollolake.x.in +++ /dev/null @@ -1,629 +0,0 @@ -/* - * Linker Script for Apololake. - * - * This script is run through the GNU C preprocessor to align the memory - * offsets with headers. - * - * Use spaces for formatting as cpp ignore tab sizes. - */ - - -#include -#include - -OUTPUT_ARCH(xtensa) - -MEMORY -{ -#if defined(CONFIG_SKYLAKE) || defined(CONFIG_KABYLAKE) - vector_reset_text : - org = HP_SRAM_VECBASE_RESET, - len = HP_SRAM_RESET_TEXT_SIZE - vector_reset_lit : - org = HP_SRAM_VECBASE_RESET + HP_SRAM_RESET_TEXT_SIZE, - len = HP_SRAM_RESET_LIT_SIZE -#endif - vector_memory_lit : - org = XCHAL_MEMERROR_VECTOR_PADDR + SOF_MEM_ERROR_LIT_SIZE, - len = SOF_MEM_ERROR_LIT_SIZE - vector_memory_text : - org = XCHAL_MEMERROR_VECTOR_PADDR, - len = SOF_MEM_ERROR_TEXT_SIZE - vector_base_text : - org = SOF_MEM_VECBASE, - len = SOF_MEM_VECBASE_LIT_SIZE - vector_int2_lit : - org = SOF_MEM_VECBASE + XCHAL_INTLEVEL2_VECOFS - SOF_MEM_VECT_LIT_SIZE, - len = SOF_MEM_VECT_LIT_SIZE - vector_int2_text : - org = SOF_MEM_VECBASE + XCHAL_INTLEVEL2_VECOFS, - len = SOF_MEM_VECT_TEXT_SIZE - vector_int3_lit : - org = SOF_MEM_VECBASE + XCHAL_INTLEVEL3_VECOFS - SOF_MEM_VECT_LIT_SIZE, - len = SOF_MEM_VECT_LIT_SIZE - vector_int3_text : - org = SOF_MEM_VECBASE + XCHAL_INTLEVEL3_VECOFS, - len = SOF_MEM_VECT_TEXT_SIZE - vector_int4_lit : - org = SOF_MEM_VECBASE + XCHAL_INTLEVEL4_VECOFS - SOF_MEM_VECT_LIT_SIZE, - len = SOF_MEM_VECT_LIT_SIZE - vector_int4_text : - org = SOF_MEM_VECBASE + XCHAL_INTLEVEL4_VECOFS, - len = SOF_MEM_VECT_TEXT_SIZE - vector_int5_lit : - org = SOF_MEM_VECBASE + XCHAL_INTLEVEL5_VECOFS - SOF_MEM_VECT_LIT_SIZE, - len = SOF_MEM_VECT_LIT_SIZE - vector_int5_text : - org = SOF_MEM_VECBASE + XCHAL_INTLEVEL5_VECOFS, - len = SOF_MEM_VECT_TEXT_SIZE - vector_int6_lit : - org = SOF_MEM_VECBASE + XCHAL_INTLEVEL6_VECOFS - SOF_MEM_VECT_LIT_SIZE, - len = SOF_MEM_VECT_LIT_SIZE - vector_int6_text : - org = SOF_MEM_VECBASE + XCHAL_INTLEVEL6_VECOFS, - len = SOF_MEM_VECT_TEXT_SIZE - vector_int7_lit : - org = SOF_MEM_VECBASE + XCHAL_INTLEVEL7_VECOFS - SOF_MEM_VECT_LIT_SIZE, - len = SOF_MEM_VECT_LIT_SIZE - vector_int7_text : - org = SOF_MEM_VECBASE + XCHAL_INTLEVEL7_VECOFS, - len = SOF_MEM_VECT_TEXT_SIZE - vector_kernel_lit : - org = SOF_MEM_VECBASE + XCHAL_KERNEL_VECOFS - SOF_MEM_VECT_LIT_SIZE, - len = SOF_MEM_VECT_LIT_SIZE - vector_kernel_text : - org = SOF_MEM_VECBASE + XCHAL_KERNEL_VECOFS, - len = SOF_MEM_VECT_TEXT_SIZE - vector_user_lit : - org = SOF_MEM_VECBASE + XCHAL_USER_VECOFS - SOF_MEM_VECT_LIT_SIZE, - len = SOF_MEM_VECT_LIT_SIZE - vector_user_text : - org = SOF_MEM_VECBASE + XCHAL_USER_VECOFS, - len = SOF_MEM_VECT_TEXT_SIZE - vector_double_lit : - org = SOF_MEM_VECBASE + XCHAL_DOUBLEEXC_VECOFS - SOF_MEM_VECT_LIT_SIZE, - len = SOF_MEM_VECT_LIT_SIZE - vector_double_text : - org = SOF_MEM_VECBASE + XCHAL_DOUBLEEXC_VECOFS, - len = SOF_MEM_VECT_TEXT_SIZE - sof_fw : - org = SOF_FW_BASE, - len = SOF_FW_MAX_SIZE - wnd0 : - org = HP_SRAM_WIN0_BASE, - len = HP_SRAM_WIN0_SIZE - wnd1 : - org = HP_SRAM_WIN1_BASE, - len = HP_SRAM_WIN1_SIZE - wnd2 : - org = HP_SRAM_WIN2_BASE, - len = HP_SRAM_WIN2_SIZE - wnd3 : - org = HP_SRAM_WIN3_BASE, - len = HP_SRAM_WIN3_SIZE - static_uuid_entries_seg (!ari) : - org = UUID_ENTRY_ELF_BASE, - len = UUID_ENTRY_ELF_SIZE - static_log_entries_seg (!ari) : - org = LOG_ENTRY_ELF_BASE, - len = LOG_ENTRY_ELF_SIZE - fw_metadata_seg (!ari) : - org = EXT_MANIFEST_ELF_BASE, - len = EXT_MANIFEST_ELF_SIZE -} - -PHDRS -{ - vector_reset_text_phdr PT_LOAD; - vector_reset_lit_phdr PT_LOAD; - vector_memory_lit_phdr PT_LOAD; - vector_memory_text_phdr PT_LOAD; - vector_base_text_phdr PT_LOAD; - vector_int2_lit_phdr PT_LOAD; - vector_int2_text_phdr PT_LOAD; - vector_int3_lit_phdr PT_LOAD; - vector_int3_text_phdr PT_LOAD; - vector_int4_lit_phdr PT_LOAD; - vector_int4_text_phdr PT_LOAD; - vector_int5_lit_phdr PT_LOAD; - vector_int5_text_phdr PT_LOAD; - vector_int6_lit_phdr PT_LOAD; - vector_int6_text_phdr PT_LOAD; - vector_int7_lit_phdr PT_LOAD; - vector_int7_text_phdr PT_LOAD; - vector_kernel_lit_phdr PT_LOAD; - vector_kernel_text_phdr PT_LOAD; - vector_user_lit_phdr PT_LOAD; - vector_user_text_phdr PT_LOAD; - vector_double_lit_phdr PT_LOAD; - vector_double_text_phdr PT_LOAD; - sof_fw_phdr PT_LOAD; - wnd0_phdr PT_LOAD; - wnd1_phdr PT_LOAD; - wnd2_phdr PT_LOAD; - wnd3_phdr PT_LOAD; - - static_uuid_entries_phdr PT_NOTE; - static_log_entries_phdr PT_NOTE; - metadata_entries_phdr PT_NOTE; -} - -/* Default entry point: */ -#if !defined(CONFIG_SKYLAKE) && !defined(CONFIG_KABYLAKE) -ENTRY(_MainEntry) -#endif -_rom_store_table = 0; - -/* ABI0 does not use Window base */ -PROVIDE(_memmap_vecbase_reset = SOF_MEM_VECBASE); - -/* Various memory-map dependent cache attribute settings: */ -_memmap_cacheattr_wbna_trapnull = 0xFF42FFF2; -PROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_wbna_trapnull); - -_EXT_MAN_ALIGN_ = 16; -EXTERN(ext_man_fw_ver) -EXTERN(ext_man_cavs_config) - -SECTIONS -{ - .MemoryExceptionVector.literal : ALIGN(4) - { - _MemoryExceptionVector_literal_start = ABSOLUTE(.); - KEEP (*(.MemoryExceptionVector.literal)) - _MemoryExceptionVector_literal_end = ABSOLUTE(.); - } >vector_memory_lit :vector_memory_lit_phdr - - .MemoryExceptionVector.text : ALIGN(4) - { - _MemoryExceptionVector_text_start = ABSOLUTE(.); - KEEP (*(.MemoryExceptionVector.text)) - _MemoryExceptionVector_text_end = ABSOLUTE(.); - } >vector_memory_text :vector_memory_text_phdr - - .wnd0 (NOLOAD) : ALIGN(8) - { - . = ALIGN (32); - _wnd0_start = ABSOLUTE(.); - . = . + HP_SRAM_WIN0_SIZE; - _wnd0_end = ABSOLUTE(.); - } >wnd0 :wnd0_phdr - - .wnd1 (NOLOAD) : ALIGN(8) - { - . = ALIGN (32); - _wnd1_start = ABSOLUTE(.); - . = . + HP_SRAM_WIN1_SIZE; - _wnd1_end = ABSOLUTE(.); - } >wnd1 :wnd1_phdr - - .wnd2 (NOLOAD) : ALIGN(8) - { - . = ALIGN (32); - _wnd2_start = ABSOLUTE(.); - . = . + HP_SRAM_WIN2_SIZE; - _wnd2_end = ABSOLUTE(.); - } >wnd2 :wnd2_phdr - - .wnd3 (NOLOAD) : ALIGN(8) - { - . = ALIGN (32); - _wnd3_start = ABSOLUTE(.); - . = . + HP_SRAM_WIN3_SIZE; - _wnd3_end = ABSOLUTE(.); - } >wnd3 :wnd3_phdr - -#if defined(CONFIG_SKYLAKE) || defined(CONFIG_KABYLAKE) - .ResetVector.text : ALIGN(4) - { - _ResetVector_text_start = ABSOLUTE(.); - KEEP (*(.ResetVector.text)) - _ResetVector_text_end = ABSOLUTE(.); - } >vector_reset_text :vector_reset_text_phdr - - .ResetVector.literal : ALIGN(4) - { - _ResetVector_literal_start = ABSOLUTE(.); - *(.ResetVector.literal) - _ResetVector_literal_end = ABSOLUTE(.); - } >vector_reset_lit :vector_reset_lit_phdr - -#endif - - .WindowVectors.text : ALIGN(4) - { - _WindowVectors_text_start = ABSOLUTE(.); - KEEP (*(.WindowVectors.text)) - _WindowVectors_text_end = ABSOLUTE(.); - } >vector_base_text :vector_base_text_phdr - - .Level2InterruptVector.literal : ALIGN(4) - { - _Level2InterruptVector_literal_start = ABSOLUTE(.); - *(.Level2InterruptVector.literal) - _Level2InterruptVector_literal_end = ABSOLUTE(.); - } >vector_int2_lit :vector_int2_lit_phdr - - .Level2InterruptVector.text : ALIGN(4) - { - _Level2InterruptVector_text_start = ABSOLUTE(.); - KEEP (*(.Level2InterruptVector.text)) - _Level2InterruptVector_text_end = ABSOLUTE(.); - } >vector_int2_text :vector_int2_text_phdr - - .Level3InterruptVector.literal : ALIGN(4) - { - _Level3InterruptVector_literal_start = ABSOLUTE(.); - *(.Level3InterruptVector.literal) - _Level3InterruptVector_literal_end = ABSOLUTE(.); - } >vector_int3_lit :vector_int3_lit_phdr - - .Level3InterruptVector.text : ALIGN(4) - { - _Level3InterruptVector_text_start = ABSOLUTE(.); - KEEP (*(.Level3InterruptVector.text)) - _Level3InterruptVector_text_end = ABSOLUTE(.); - } >vector_int3_text :vector_int3_text_phdr - - .Level4InterruptVector.literal : ALIGN(4) - { - _Level4InterruptVector_literal_start = ABSOLUTE(.); - *(.Level4InterruptVector.literal) - _Level4InterruptVector_literal_end = ABSOLUTE(.); - } >vector_int4_lit :vector_int4_lit_phdr - - .Level4InterruptVector.text : ALIGN(4) - { - _Level4InterruptVector_text_start = ABSOLUTE(.); - KEEP (*(.Level4InterruptVector.text)) - _Level4InterruptVector_text_end = ABSOLUTE(.); - } >vector_int4_text :vector_int4_text_phdr - - .Level5InterruptVector.literal : ALIGN(4) - { - _Level5InterruptVector_literal_start = ABSOLUTE(.); - *(.Level5InterruptVector.literal) - _Level5InterruptVector_literal_end = ABSOLUTE(.); - } >vector_int5_lit :vector_int5_lit_phdr - - .Level5InterruptVector.text : ALIGN(4) - { - _Level5InterruptVector_text_start = ABSOLUTE(.); - KEEP (*(.Level5InterruptVector.text)) - _Level5InterruptVector_text_end = ABSOLUTE(.); - } >vector_int5_text :vector_int5_text_phdr - - .DebugExceptionVector.literal : ALIGN(4) - { - _DebugExceptionVector_literal_start = ABSOLUTE(.); - *(.DebugExceptionVector.literal) - _DebugExceptionVector_literal_end = ABSOLUTE(.); - } >vector_int6_lit :vector_int6_lit_phdr - - .DebugExceptionVector.text : ALIGN(4) - { - _DebugExceptionVector_text_start = ABSOLUTE(.); - KEEP (*(.DebugExceptionVector.text)) - _DebugExceptionVector_text_end = ABSOLUTE(.); - } >vector_int6_text :vector_int6_text_phdr - - .NMIExceptionVector.literal : ALIGN(4) - { - _NMIExceptionVector_literal_start = ABSOLUTE(.); - *(.NMIExceptionVector.literal) - _NMIExceptionVector_literal_end = ABSOLUTE(.); - } >vector_int7_lit :vector_int7_lit_phdr - - .NMIExceptionVector.text : ALIGN(4) - { - _NMIExceptionVector_text_start = ABSOLUTE(.); - KEEP (*(.NMIExceptionVector.text)) - _NMIExceptionVector_text_end = ABSOLUTE(.); - } >vector_int7_text :vector_int7_text_phdr - - .KernelExceptionVector.literal : ALIGN(4) - { - _KernelExceptionVector_literal_start = ABSOLUTE(.); - *(.KernelExceptionVector.literal) - _KernelExceptionVector_literal_end = ABSOLUTE(.); - } >vector_kernel_lit :vector_kernel_lit_phdr - - .KernelExceptionVector.text : ALIGN(4) - { - _KernelExceptionVector_text_start = ABSOLUTE(.); - KEEP (*(.KernelExceptionVector.text)) - _KernelExceptionVector_text_end = ABSOLUTE(.); - } >vector_kernel_text :vector_kernel_text_phdr - - .UserExceptionVector.literal : ALIGN(4) - { - _UserExceptionVector_literal_start = ABSOLUTE(.); - *(.UserExceptionVector.literal) - _UserExceptionVector_literal_end = ABSOLUTE(.); - } >vector_user_lit :vector_user_lit_phdr - - .UserExceptionVector.text : ALIGN(4) - { - _UserExceptionVector_text_start = ABSOLUTE(.); - KEEP (*(.UserExceptionVector.text)) - _UserExceptionVector_text_end = ABSOLUTE(.); - } >vector_user_text :vector_user_text_phdr - - .DoubleExceptionVector.literal : ALIGN(4) - { - _DoubleExceptionVector_literal_start = ABSOLUTE(.); - *(.DoubleExceptionVector.literal) - _DoubleExceptionVector_literal_end = ABSOLUTE(.); - } >vector_double_lit :vector_double_lit_phdr - - .DoubleExceptionVector.text : ALIGN(4) - { - _DoubleExceptionVector_text_start = ABSOLUTE(.); - KEEP (*(.DoubleExceptionVector.text)) - _DoubleExceptionVector_text_end = ABSOLUTE(.); - } >vector_double_text :vector_double_text_phdr - - .text : ALIGN(4) - { - _stext = .; - _text_start = ABSOLUTE(.); - KEEP (*(.MainEntry.text)) - *(.entry.text) - *(.init.literal) - KEEP(*(.init)) - *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*) - *(.fini.literal) - KEEP(*(.fini)) - *(.gnu.version) - _text_end = ABSOLUTE(.); - _etext = .; - } >sof_fw :sof_fw_phdr - - .rodata : ALIGN(4096) - { - _rodata_start = ABSOLUTE(.); - *(.rodata) - *(.rodata.*) - *(.gnu.linkonce.r.*) - *(.rodata1) - __XT_EXCEPTION_TABLE__ = ABSOLUTE(.); - KEEP (*(.xt_except_table)) - KEEP (*(.gcc_except_table)) - *(.gnu.linkonce.e.*) - *(.gnu.version_r) - KEEP (*(.eh_frame)) - /* C++ constructor and destructor tables, properly ordered: */ - KEEP (*crtbegin.o(.ctors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) - KEEP (*(SORT(.ctors.*))) - KEEP (*(.ctors)) - KEEP (*crtbegin.o(.dtors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) - KEEP (*(SORT(.dtors.*))) - KEEP (*(.dtors)) - /* C++ exception handlers table: */ - __XT_EXCEPTION_DESCS__ = ABSOLUTE(.); - *(.xt_except_desc) - *(.gnu.linkonce.h.*) - __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.); - *(.xt_except_desc_end) - *(.dynamic) - *(.gnu.version_d) - . = ALIGN(4); /* this table MUST be 4-byte aligned */ - _bss_table_start = ABSOLUTE(.); - LONG(_bss_start) - LONG(_bss_end) - _bss_table_end = ABSOLUTE(.); - _rodata_end = ABSOLUTE(.); - } >sof_fw :sof_fw_phdr - - .module_init : ALIGN(4) - { - _module_init_start = ABSOLUTE(.); - *(*.initcall) - _module_init_end = ABSOLUTE(.); - } >sof_fw :sof_fw_phdr - - .shared_data : ALIGN(PLATFORM_DCACHE_ALIGN) - { - _shared_data_start = ABSOLUTE(.); - *(*.shared_data) - _shared_data_end = ABSOLUTE(.); - . = ALIGN(PLATFORM_DCACHE_ALIGN); - } >sof_fw :sof_fw_phdr - - .data : ALIGN(4) - { - _data_start = ABSOLUTE(.); - *(.data) - *(.data.*) - *(.gnu.linkonce.d.*) - KEEP(*(.gnu.linkonce.d.*personality*)) - *(.data1) - *(.sdata) - *(.sdata.*) - *(.gnu.linkonce.s.*) - *(.sdata2) - *(.sdata2.*) - *(.gnu.linkonce.s2.*) - KEEP(*(.jcr)) - _trace_ctx_start = ABSOLUTE(.); - *(.trace_ctx) - _trace_ctx_end = ABSOLUTE(.); - _data_end = ABSOLUTE(.); - } >sof_fw :sof_fw_phdr - - .lit4 : ALIGN(4) - { - _lit4_start = ABSOLUTE(.); - *(*.lit4) - *(.lit4.*) - *(.gnu.linkonce.lit4.*) - _lit4_end = ABSOLUTE(.); - } >sof_fw :sof_fw_phdr - - .fw_ready : ALIGN(4) - { - KEEP (*(.fw_ready)) - KEEP (*(.fw_ready_metadata)) - } >sof_fw :sof_fw_phdr - - .bss (NOLOAD) : ALIGN(4096) - { - . = ALIGN (8); - _bss_start = ABSOLUTE(.); - *(.dynsbss) - *(.sbss) - *(.sbss.*) - *(.gnu.linkonce.sb.*) - *(.scommon) - *(.sbss2) - *(.sbss2.*) - *(.gnu.linkonce.sb2.*) - *(.dynbss) - *(.bss) - *(.bss.*) - *(.gnu.linkonce.b.*) - *(COMMON) - - . = ALIGN (HEAP_BUF_ALIGNMENT); - _system_heap_start = ABSOLUTE(.); - . = . + HEAP_SYSTEM_M_SIZE; - _system_heap_end = ABSOLUTE(.); - - . = ALIGN (HEAP_BUF_ALIGNMENT); - _system_runtime_heap_start = ABSOLUTE(.); - . = . + HEAP_SYS_RUNTIME_M_SIZE; - _system_runtime_heap_end = ABSOLUTE(.); - - . = ALIGN (4096); - _sof_stack_start = ABSOLUTE(.); - . = . + SOF_STACK_SIZE; - _sof_stack_end = ABSOLUTE(.); - -#if CONFIG_CORE_COUNT > 1 - . = ALIGN (PLATFORM_DCACHE_ALIGN); - _runtime_shared_heap_start = ABSOLUTE(.); - . = . + HEAP_RUNTIME_SHARED_SIZE; - . = ALIGN (PLATFORM_DCACHE_ALIGN); - _runtime_shared_heap_end = ABSOLUTE(.); - - . = ALIGN (PLATFORM_DCACHE_ALIGN); - _system_shared_heap_start = ABSOLUTE(.); - . = . + HEAP_SYSTEM_SHARED_SIZE; - . = ALIGN (PLATFORM_DCACHE_ALIGN); - _system_shared_heap_end = ABSOLUTE(.); - - . = ALIGN (HEAP_BUF_ALIGNMENT); - _sof_core_s_start = ABSOLUTE(.); - . = . + SOF_CORE_S_T_SIZE; - _sof_core_s_end = ABSOLUTE(.); -#endif - - _runtime_heap_start = ABSOLUTE(.); - . = . + HEAP_RUNTIME_SIZE; - _runtime_heap_end = ABSOLUTE(.); - - . = ALIGN (PLATFORM_DCACHE_ALIGN); - _buffer_heap_start = ABSOLUTE(.); - . = . + SOF_FW_END - _buffer_heap_start; - _buffer_heap_end = ABSOLUTE(.); - - _bss_end = ABSOLUTE(.); - } >sof_fw :sof_fw_phdr - - /* stack */ - _end = _sof_stack_start; - PROVIDE(end = _sof_stack_start); - _stack_sentry = _sof_stack_start; - __stack = _sof_stack_end; - - /* Secondary core size */ - _core_s_size = SOF_CORE_S_SIZE; - - /* System Heap */ - _system_heap = _system_heap_start; - - /* system runtime heap */ - _system_runtime_heap = _system_runtime_heap_start; - -#if CONFIG_CORE_COUNT > 1 - /* Shared Heap */ - _runtime_shared_heap = _runtime_shared_heap_start; - _system_shared_heap = _system_shared_heap_start; -#endif - - /* module heap */ - _module_heap = _runtime_heap_start; - - /* buffer heap */ - _buffer_heap = _buffer_heap_start; - _buffer_heap_end = _buffer_heap_end; - - .debug 0 : { *(.debug) } - .line 0 : { *(.line) } - .debug_srcinfo 0 : { *(.debug_srcinfo) } - .debug_sfnames 0 : { *(.debug_sfnames) } - .debug_aranges 0 : { *(.debug_aranges) } - .debug_pubnames 0 : { *(.debug_pubnames) } - .debug_info 0 : { *(.debug_info) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_line 0 : { *(.debug_line) } - .debug_frame 0 : { *(.debug_frame) } - .debug_str 0 : { *(.debug_str) } - .debug_loc 0 : { *(.debug_loc) } - .debug_macinfo 0 : { *(.debug_macinfo) } - .debug_weaknames 0 : { *(.debug_weaknames) } - .debug_funcnames 0 : { *(.debug_funcnames) } - .debug_typenames 0 : { *(.debug_typenames) } - .debug_varnames 0 : { *(.debug_varnames) } - - .xt.insn 0 : - { - KEEP (*(.xt.insn)) - KEEP (*(.gnu.linkonce.x.*)) - } - .xt.prop 0 : - { - KEEP (*(.xt.prop)) - KEEP (*(.xt.prop.*)) - KEEP (*(.gnu.linkonce.prop.*)) - } - .xt.lit 0 : - { - KEEP (*(.xt.lit)) - KEEP (*(.xt.lit.*)) - KEEP (*(.gnu.linkonce.p.*)) - } - .xt.profile_range 0 : - { - KEEP (*(.xt.profile_range)) - KEEP (*(.gnu.linkonce.profile_range.*)) - } - .xt.profile_ranges 0 : - { - KEEP (*(.xt.profile_ranges)) - KEEP (*(.gnu.linkonce.xt.profile_ranges.*)) - } - .xt.profile_files 0 : - { - KEEP (*(.xt.profile_files)) - KEEP (*(.gnu.linkonce.xt.profile_files.*)) - } - - .static_uuid_entries (COPY) : ALIGN(1024) - { - *(*.static_uuids) - } > static_uuid_entries_seg :static_uuid_entries_phdr - - .static_log_entries (COPY) : ALIGN(1024) - { - *(*.static_log*) - } > static_log_entries_seg :static_log_entries_phdr - - .fw_metadata (COPY) : ALIGN(1024) - { - KEEP (*(.fw_metadata)) - . = ALIGN(_EXT_MAN_ALIGN_); - } >fw_metadata_seg :metadata_entries_phdr -} diff --git a/src/platform/apollolake/base_module.c b/src/platform/apollolake/base_module.c deleted file mode 100644 index 17229771cc51..000000000000 --- a/src/platform/apollolake/base_module.c +++ /dev/null @@ -1,30 +0,0 @@ -// SPDX-License-Identifier: BSD-3-Clause -// -// Copyright(c) 2018 Intel Corporation. All rights reserved. -// -// Author: Liam Girdwood - -#include -#include - -/* - * Each module has an entry in the FW manifest header. This is NOT part of - * the SOF executable image but is inserted by object copy as a ELF section - * for parsing by rimage (to genrate the manifest). - */ -struct sof_man_module_manifest apl_manifest = { - .module = { - .name = "BASEFW", - .uuid = {0x2e, 0x9e, 0x86, 0xfc, 0xf8, 0x45, 0x45, 0x40, - 0xa4, 0x16, 0x89, 0x88, 0x0a, 0xe3, 0x20, 0xa9}, - .entry_point = SOF_TEXT_START, - .type = { - .load_type = SOF_MAN_MOD_TYPE_MODULE, - .domain_ll = 1, - }, - .affinity_mask = 3, - }, -}; - -/* not used, but stops linker complaining */ -int _start; diff --git a/src/platform/apollolake/boot_ldr.x.in b/src/platform/apollolake/boot_ldr.x.in deleted file mode 100644 index 4989c280fb1c..000000000000 --- a/src/platform/apollolake/boot_ldr.x.in +++ /dev/null @@ -1,237 +0,0 @@ -/* - * Linker Script for Apollolake Bootloader. - * - * This script is run through the GNU C preprocessor to align the memory - * offsets with headers. - * - * Use spaces for formatting as cpp ignore tab sizes. - */ - - -#include -#include - -OUTPUT_ARCH(xtensa) - -MEMORY -{ - boot_entry_text : - org = IMR_BOOT_LDR_TEXT_ENTRY_BASE, - len = IMR_BOOT_LDR_TEXT_ENTRY_SIZE - boot_entry_lit : - org = IMR_BOOT_LDR_LIT_BASE, - len = IMR_BOOT_LDR_LIT_SIZE - sof_text : - org = IMR_BOOT_LDR_TEXT_BASE, - len = IMR_BOOT_LDR_TEXT_SIZE, - sof_data : - org = IMR_BOOT_LDR_DATA_BASE, - len = IMR_BOOT_LDR_DATA_SIZE - sof_bss_data : - org = IMR_BOOT_LDR_BSS_BASE, - len = IMR_BOOT_LDR_BSS_SIZE - sof_stack : - org = BOOT_LDR_STACK_BASE, - len = BOOT_LDR_STACK_SIZE - wnd0 : - org = HP_SRAM_WIN0_BASE, - len = HP_SRAM_WIN0_SIZE -} - -PHDRS -{ - boot_entry_text_phdr PT_LOAD; - boot_entry_lit_phdr PT_LOAD; - sof_text_phdr PT_LOAD; - sof_data_phdr PT_LOAD; - sof_bss_data_phdr PT_LOAD; - sof_stack_phdr PT_LOAD; - wnd0_phdr PT_LOAD; -} - -/* Default entry point: */ -ENTRY(boot_entry) -EXTERN(reset_vector) - -SECTIONS -{ - .boot_entry.text : ALIGN(4) - { - _boot_entry_text_start = ABSOLUTE(.); - KEEP (*(.boot_entry.text)) - _boot_entry_text_end = ABSOLUTE(.); - } >boot_entry_text :boot_entry_text_phdr - - .boot_entry.literal : ALIGN(4) - { - _boot_entry_literal_start = ABSOLUTE(.); - *(.boot_entry.literal) - *(.literal .literal.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*) - _boot_entry_literal_end = ABSOLUTE(.); - } >boot_entry_lit :boot_entry_lit_phdr - - .text : ALIGN(4) - { - _stext = .; - _text_start = ABSOLUTE(.); - *(.entry.text) - *(.init.literal) - KEEP(*(.init)) - *( .text .text.*) - *(.fini.literal) - KEEP(*(.fini)) - *(.gnu.version) - KEEP (*(.ResetVector.text)) - KEEP (*(.ResetHandler.text)) - _text_end = ABSOLUTE(.); - _etext = .; - } >sof_text :sof_text_phdr - - .rodata : ALIGN(4) - { - _rodata_start = ABSOLUTE(.); - *(.rodata) - *(.rodata.*) - *(.gnu.linkonce.r.*) - *(.rodata1) - __XT_EXCEPTION_TABLE__ = ABSOLUTE(.); - KEEP (*(.xt_except_table)) - KEEP (*(.gcc_except_table)) - *(.gnu.linkonce.e.*) - *(.gnu.version_r) - KEEP (*(.eh_frame)) - /* C++ constructor and destructor tables, properly ordered: */ - KEEP (*crtbegin.o(.ctors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) - KEEP (*(SORT(.ctors.*))) - KEEP (*(.ctors)) - KEEP (*crtbegin.o(.dtors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) - KEEP (*(SORT(.dtors.*))) - KEEP (*(.dtors)) - /* C++ exception handlers table: */ - __XT_EXCEPTION_DESCS__ = ABSOLUTE(.); - *(.xt_except_desc) - *(.gnu.linkonce.h.*) - __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.); - *(.xt_except_desc_end) - *(.dynamic) - *(.gnu.version_d) - . = ALIGN(4); /* this table MUST be 4-byte aligned */ - _bss_table_start = ABSOLUTE(.); - LONG(_bss_start) - LONG(_bss_end) - _bss_table_end = ABSOLUTE(.); - _rodata_end = ABSOLUTE(.); - } >sof_data :sof_data_phdr - - .data : ALIGN(4) - { - _data_start = ABSOLUTE(.); - *(.data) - *(.data.*) - *(.gnu.linkonce.d.*) - KEEP(*(.gnu.linkonce.d.*personality*)) - *(.data1) - *(.sdata) - *(.sdata.*) - *(.gnu.linkonce.s.*) - *(.sdata2) - *(.sdata2.*) - *(.gnu.linkonce.s2.*) - KEEP(*(.jcr)) - _data_end = ABSOLUTE(.); - } >sof_data :sof_data_phdr - - .lit4 : ALIGN(4) - { - _lit4_start = ABSOLUTE(.); - *(*.lit4) - *(.lit4.*) - *(.gnu.linkonce.lit4.*) - _lit4_end = ABSOLUTE(.); - } >sof_data :sof_data_phdr - - .bss (NOLOAD) : ALIGN(8) - { - . = ALIGN (8); - _bss_start = ABSOLUTE(.); - *(.dynsbss) - *(.sbss) - *(.sbss.*) - *(.gnu.linkonce.sb.*) - *(.scommon) - *(.sbss2) - *(.sbss2.*) - *(.gnu.linkonce.sb2.*) - *(.dynbss) - *(.bss) - *(.bss.*) - *(.gnu.linkonce.b.*) - *(COMMON) - . = ALIGN (8); - _bss_end = ABSOLUTE(.); - } >sof_bss_data :sof_bss_data_phdr - - _man = 0x1234567; - - PROVIDE(_memmap_vecbase_reset = HP_SRAM_VECBASE_RESET); - - _memmap_cacheattr_wbna_trapnull = 0xFF42FFF2; - PROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_wbna_trapnull); - - __stack = BOOT_LDR_STACK_BASE + BOOT_LDR_STACK_SIZE; - __wnd0 = HP_SRAM_WIN0_BASE; - __wnd0_size = HP_SRAM_WIN0_SIZE; - - .debug 0 : { *(.debug) } - .line 0 : { *(.line) } - .debug_srcinfo 0 : { *(.debug_srcinfo) } - .debug_sfnames 0 : { *(.debug_sfnames) } - .debug_aranges 0 : { *(.debug_aranges) } - .debug_pubnames 0 : { *(.debug_pubnames) } - .debug_info 0 : { *(.debug_info) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_line 0 : { *(.debug_line) } - .debug_frame 0 : { *(.debug_frame) } - .debug_str 0 : { *(.debug_str) } - .debug_loc 0 : { *(.debug_loc) } - .debug_macinfo 0 : { *(.debug_macinfo) } - .debug_weaknames 0 : { *(.debug_weaknames) } - .debug_funcnames 0 : { *(.debug_funcnames) } - .debug_typenames 0 : { *(.debug_typenames) } - .debug_varnames 0 : { *(.debug_varnames) } - - .xt.insn 0 : - { - KEEP (*(.xt.insn)) - KEEP (*(.gnu.linkonce.x.*)) - } - .xt.prop 0 : - { - KEEP (*(.xt.prop)) - KEEP (*(.xt.prop.*)) - KEEP (*(.gnu.linkonce.prop.*)) - } - .xt.lit 0 : - { - KEEP (*(.xt.lit)) - KEEP (*(.xt.lit.*)) - KEEP (*(.gnu.linkonce.p.*)) - } - .xt.profile_range 0 : - { - KEEP (*(.xt.profile_range)) - KEEP (*(.gnu.linkonce.profile_range.*)) - } - .xt.profile_ranges 0 : - { - KEEP (*(.xt.profile_ranges)) - KEEP (*(.gnu.linkonce.xt.profile_ranges.*)) - } - .xt.profile_files 0 : - { - KEEP (*(.xt.profile_files)) - KEEP (*(.gnu.linkonce.xt.profile_files.*)) - } -} diff --git a/src/platform/apollolake/boot_module.c b/src/platform/apollolake/boot_module.c deleted file mode 100644 index 086306ba51dd..000000000000 --- a/src/platform/apollolake/boot_module.c +++ /dev/null @@ -1,30 +0,0 @@ -// SPDX-License-Identifier: BSD-3-Clause -// -// Copyright(c) 2018 Intel Corporation. All rights reserved. -// -// Author: Marcin Maka - -#include -#include - -/* - * Each module has an entry in the FW manifest header. This is NOT part of - * the SOF executable image but is inserted by object copy as a ELF section - * for parsing by rimage (to generate the manifest). - */ -struct sof_man_module_manifest apl_bootldr_manifest = { - .module = { - .name = "BRNGUP", - .uuid = {0xcc, 0x48, 0x7b, 0x0d, 0xa9, 0x1e, 0x0a, 0x47, - 0xa8, 0xc1, 0x53, 0x34, 0x24, 0x52, 0x8a, 0x17}, - .entry_point = IMR_BOOT_LDR_TEXT_ENTRY_BASE, - .type = { - .load_type = SOF_MAN_MOD_TYPE_MODULE, - .domain_ll = 1, - }, - .affinity_mask = 3, - }, -}; - -/* not used, but stops linker complaining */ -int _start; diff --git a/src/platform/apollolake/include/arch/xtensa/config/core-isa.h b/src/platform/apollolake/include/arch/xtensa/config/core-isa.h deleted file mode 100644 index 714a6b237417..000000000000 --- a/src/platform/apollolake/include/arch/xtensa/config/core-isa.h +++ /dev/null @@ -1,613 +0,0 @@ -/* - * xtensa/config/core-isa.h -- HAL definitions that are dependent on Xtensa - * processor CORE configuration - * - * See , which includes this file, for more details. - */ - -/* Xtensa processor core configuration information. - - Copyright (c) 1999-2018 Tensilica Inc. - - Permission is hereby granted, free of charge, to any person obtaining - a copy of this software and associated documentation files (the - "Software"), to deal in the Software without restriction, including - without limitation the rights to use, copy, modify, merge, publish, - distribute, sublicense, and/or sell copies of the Software, and to - permit persons to whom the Software is furnished to do so, subject to - the following conditions: - - The above copyright notice and this permission notice shall be included - in all copies or substantial portions of the Software. - - THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. - IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY - CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, - TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE - SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ - -#if !defined __XCC__ - -#ifndef _XTENSA_CORE_CONFIGURATION_H -#define _XTENSA_CORE_CONFIGURATION_H - - -/**************************************************************************** - Parameters Useful for Any Code, USER or PRIVILEGED - ****************************************************************************/ - -/* - * Note: Macros of the form XCHAL_HAVE_*** have a value of 1 if the option is - * configured, and a value of 0 otherwise. These macros are always defined. - */ - - -/*---------------------------------------------------------------------- - ISA - ----------------------------------------------------------------------*/ - -#define XCHAL_HAVE_BE 0 /* big-endian byte ordering */ -#define XCHAL_HAVE_WINDOWED 1 /* windowed registers option */ -#define XCHAL_NUM_AREGS 64 /* num of physical addr regs */ -#define XCHAL_NUM_AREGS_LOG2 6 /* log2(XCHAL_NUM_AREGS) */ -#define XCHAL_MAX_INSTRUCTION_SIZE 8 /* max instr bytes (3..8) */ -#define XCHAL_HAVE_DEBUG 1 /* debug option */ -#define XCHAL_HAVE_DENSITY 1 /* 16-bit instructions */ -#define XCHAL_HAVE_LOOPS 1 /* zero-overhead loops */ -#define XCHAL_LOOP_BUFFER_SIZE 0 /* zero-ov. loop instr buffer size */ -#define XCHAL_HAVE_NSA 1 /* NSA/NSAU instructions */ -#define XCHAL_HAVE_MINMAX 1 /* MIN/MAX instructions */ -#define XCHAL_HAVE_SEXT 1 /* SEXT instruction */ -#define XCHAL_HAVE_DEPBITS 0 /* DEPBITS instruction */ -#define XCHAL_HAVE_CLAMPS 1 /* CLAMPS instruction */ -#define XCHAL_HAVE_MUL16 1 /* MUL16S/MUL16U instructions */ -#define XCHAL_HAVE_MUL32 1 /* MULL instruction */ -#define XCHAL_HAVE_MUL32_HIGH 1 /* MULUH/MULSH instructions */ -#define XCHAL_HAVE_DIV32 1 /* QUOS/QUOU/REMS/REMU instructions */ -#define XCHAL_HAVE_L32R 1 /* L32R instruction */ -#define XCHAL_HAVE_ABSOLUTE_LITERALS 0 /* non-PC-rel (extended) L32R */ -#define XCHAL_HAVE_CONST16 0 /* CONST16 instruction */ -#define XCHAL_HAVE_ADDX 1 /* ADDX#/SUBX# instructions */ -#define XCHAL_HAVE_EXCLUSIVE 0 /* L32EX/S32EX instructions */ -#define XCHAL_HAVE_WIDE_BRANCHES 0 /* B*.W18 or B*.W15 instr's */ -#define XCHAL_HAVE_PREDICTED_BRANCHES 0 /* B[EQ/EQZ/NE/NEZ]T instr's */ -#define XCHAL_HAVE_CALL4AND12 1 /* (obsolete option) */ -#define XCHAL_HAVE_ABS 1 /* ABS instruction */ -/*#define XCHAL_HAVE_POPC 0*/ /* POPC instruction */ -/*#define XCHAL_HAVE_CRC 0*/ /* CRC instruction */ -#define XCHAL_HAVE_RELEASE_SYNC 1 /* L32AI/S32RI instructions */ -#define XCHAL_HAVE_S32C1I 1 /* S32C1I instruction */ -#define XCHAL_HAVE_SPECULATION 0 /* speculation */ -#define XCHAL_HAVE_FULL_RESET 1 /* all regs/state reset */ -#define XCHAL_NUM_CONTEXTS 1 /* */ -#define XCHAL_NUM_MISC_REGS 0 /* num of scratch regs (0..4) */ -#define XCHAL_HAVE_TAP_MASTER 0 /* JTAG TAP control instr's */ -#define XCHAL_HAVE_PRID 1 /* processor ID register */ -#define XCHAL_HAVE_EXTERN_REGS 1 /* WER/RER instructions */ -#define XCHAL_HAVE_MX 0 /* MX core (Tensilica internal) */ -#define XCHAL_HAVE_MP_INTERRUPTS 0 /* interrupt distributor port */ -#define XCHAL_HAVE_MP_RUNSTALL 0 /* core RunStall control port */ -#define XCHAL_HAVE_PSO 0 /* Power Shut-Off */ -#define XCHAL_HAVE_PSO_CDM 0 /* core/debug/mem pwr domains */ -#define XCHAL_HAVE_PSO_FULL_RETENTION 0 /* all regs preserved on PSO */ -#define XCHAL_HAVE_THREADPTR 1 /* THREADPTR register */ -#define XCHAL_HAVE_BOOLEANS 1 /* boolean registers */ -#define XCHAL_HAVE_CP 1 /* CPENABLE reg (coprocessor) */ -#define XCHAL_CP_MAXCFG 2 /* max allowed cp id plus one */ -#define XCHAL_HAVE_MAC16 0 /* MAC16 package */ - -#define XCHAL_HAVE_FUSION 0 /* Fusion*/ -#define XCHAL_HAVE_FUSION_FP 0 /* Fusion FP option */ -#define XCHAL_HAVE_FUSION_LOW_POWER 0 /* Fusion Low Power option */ -#define XCHAL_HAVE_FUSION_AES 0 /* Fusion BLE/Wifi AES-128 CCM option */ -#define XCHAL_HAVE_FUSION_CONVENC 0 /* Fusion Conv Encode option */ -#define XCHAL_HAVE_FUSION_LFSR_CRC 0 /* Fusion LFSR-CRC option */ -#define XCHAL_HAVE_FUSION_BITOPS 0 /* Fusion Bit Operations Support option */ -#define XCHAL_HAVE_FUSION_AVS 0 /* Fusion AVS option */ -#define XCHAL_HAVE_FUSION_16BIT_BASEBAND 0 /* Fusion 16-bit Baseband option */ -#define XCHAL_HAVE_FUSION_VITERBI 0 /* Fusion Viterbi option */ -#define XCHAL_HAVE_FUSION_SOFTDEMAP 0 /* Fusion Soft Bit Demap option */ -#define XCHAL_HAVE_HIFIPRO 0 /* HiFiPro Audio Engine pkg */ -#define XCHAL_HAVE_HIFI4 0 /* HiFi4 Audio Engine pkg */ -#define XCHAL_HAVE_HIFI4_VFPU 0 /* HiFi4 Audio Engine VFPU option */ -#define XCHAL_HAVE_HIFI3 1 /* HiFi3 Audio Engine pkg */ -#define XCHAL_HAVE_HIFI3_VFPU 0 /* HiFi3 Audio Engine VFPU option */ -#define XCHAL_HAVE_HIFI3Z 0 /* HiFi3Z Audio Engine pkg */ -#define XCHAL_HAVE_HIFI3Z_VFPU 0 /* HiFi3Z Audio Engine VFPU option */ -#define XCHAL_HAVE_HIFI2 0 /* HiFi2 Audio Engine pkg */ -#define XCHAL_HAVE_HIFI2EP 0 /* HiFi2EP */ -#define XCHAL_HAVE_HIFI_MINI 0 - - - -#define XCHAL_HAVE_VECTORFPU2005 0 /* vector floating-point pkg */ -#define XCHAL_HAVE_USER_DPFPU 0 /* user DP floating-point pkg */ -#define XCHAL_HAVE_USER_SPFPU 0 /* user SP floating-point pkg */ -#define XCHAL_HAVE_FP 0 /* single prec floating point */ -#define XCHAL_HAVE_FP_DIV 0 /* FP with DIV instructions */ -#define XCHAL_HAVE_FP_RECIP 0 /* FP with RECIP instructions */ -#define XCHAL_HAVE_FP_SQRT 0 /* FP with SQRT instructions */ -#define XCHAL_HAVE_FP_RSQRT 0 /* FP with RSQRT instructions */ -#define XCHAL_HAVE_DFP 0 /* double precision FP pkg */ -#define XCHAL_HAVE_DFP_DIV 0 /* DFP with DIV instructions */ -#define XCHAL_HAVE_DFP_RECIP 0 /* DFP with RECIP instructions*/ -#define XCHAL_HAVE_DFP_SQRT 0 /* DFP with SQRT instructions */ -#define XCHAL_HAVE_DFP_RSQRT 0 /* DFP with RSQRT instructions*/ -#define XCHAL_HAVE_DFP_ACCEL 0 /* double precision FP acceleration pkg */ -#define XCHAL_HAVE_DFP_accel XCHAL_HAVE_DFP_ACCEL /* for backward compatibility */ - -#define XCHAL_HAVE_DFPU_SINGLE_ONLY 0 /* DFPU Coprocessor, single precision only */ -#define XCHAL_HAVE_DFPU_SINGLE_DOUBLE 0 /* DFPU Coprocessor, single and double precision */ -#define XCHAL_HAVE_VECTRA1 0 /* Vectra I pkg */ -#define XCHAL_HAVE_VECTRALX 0 /* Vectra LX pkg */ - -#define XCHAL_HAVE_FUSIONG 0 /* FusionG */ -#define XCHAL_HAVE_FUSIONG3 0 /* FusionG3 */ -#define XCHAL_HAVE_FUSIONG6 0 /* FusionG6 */ -#define XCHAL_HAVE_FUSIONG_SP_VFPU 0 /* sp_vfpu option on FusionG */ -#define XCHAL_HAVE_FUSIONG_DP_VFPU 0 /* dp_vfpu option on FusionG */ -#define XCHAL_FUSIONG_SIMD32 0 /* simd32 for FusionG */ - -#define XCHAL_HAVE_PDX 0 /* PDX */ -#define XCHAL_PDX_SIMD32 0 /* simd32 for PDX */ -#define XCHAL_HAVE_PDX4 0 /* PDX4 */ -#define XCHAL_HAVE_PDX8 0 /* PDX8 */ -#define XCHAL_HAVE_PDX16 0 /* PDX16 */ - -#define XCHAL_HAVE_CONNXD2 0 /* ConnX D2 pkg */ -#define XCHAL_HAVE_CONNXD2_DUALLSFLIX 0 /* ConnX D2 & Dual LoadStore Flix */ -#define XCHAL_HAVE_BBE16 0 /* ConnX BBE16 pkg */ -#define XCHAL_HAVE_BBE16_RSQRT 0 /* BBE16 & vector recip sqrt */ -#define XCHAL_HAVE_BBE16_VECDIV 0 /* BBE16 & vector divide */ -#define XCHAL_HAVE_BBE16_DESPREAD 0 /* BBE16 & despread */ -#define XCHAL_HAVE_BBENEP 0 /* ConnX BBENEP pkgs */ -#define XCHAL_HAVE_BBENEP_SP_VFPU 0 /* sp_vfpu option on BBE-EP */ -#define XCHAL_HAVE_BSP3 0 /* ConnX BSP3 pkg */ -#define XCHAL_HAVE_BSP3_TRANSPOSE 0 /* BSP3 & transpose32x32 */ -#define XCHAL_HAVE_SSP16 0 /* ConnX SSP16 pkg */ -#define XCHAL_HAVE_SSP16_VITERBI 0 /* SSP16 & viterbi */ -#define XCHAL_HAVE_TURBO16 0 /* ConnX Turbo16 pkg */ -#define XCHAL_HAVE_BBP16 0 /* ConnX BBP16 pkg */ -#define XCHAL_HAVE_FLIX3 0 /* basic 3-way FLIX option */ -#define XCHAL_HAVE_GRIVPEP 0 /* General Release of IVPEP */ -#define XCHAL_HAVE_GRIVPEP_HISTOGRAM 0 /* Histogram option on GRIVPEP */ - -#define XCHAL_HAVE_VISION 0 /* Vision P5/P6 */ -#define XCHAL_VISION_SIMD16 0 /* simd16 for Vision P5/P6 */ -#define XCHAL_VISION_TYPE 0 /* Vision P5, P6, or P3 */ -#define XCHAL_VISION_QUAD_MAC_TYPE 0 /* quad_mac option on Vision P6 */ -#define XCHAL_HAVE_VISION_HISTOGRAM 0 /* histogram option on Vision P5/P6 */ -#define XCHAL_HAVE_VISION_SP_VFPU 0 /* sp_vfpu option on Vision P5/P6 */ -#define XCHAL_HAVE_VISION_HP_VFPU 0 /* hp_vfpu option on Vision P6 */ - -#define XCHAL_HAVE_VISIONC 0 /* Vision C */ - -/*---------------------------------------------------------------------- - MISC - ----------------------------------------------------------------------*/ - -#define XCHAL_NUM_LOADSTORE_UNITS 1 /* load/store units */ -#define XCHAL_NUM_WRITEBUFFER_ENTRIES 8 /* size of write buffer */ -#define XCHAL_INST_FETCH_WIDTH 8 /* instr-fetch width in bytes */ -#define XCHAL_DATA_WIDTH 8 /* data width in bytes */ -#define XCHAL_DATA_PIPE_DELAY 2 /* d-side pipeline delay - (1 = 5-stage, 2 = 7-stage) */ -#define XCHAL_CLOCK_GATING_GLOBAL 1 /* global clock gating */ -#define XCHAL_CLOCK_GATING_FUNCUNIT 1 /* funct. unit clock gating */ -/* In T1050, applies to selected core load and store instructions (see ISA): */ -#define XCHAL_UNALIGNED_LOAD_EXCEPTION 0 /* unaligned loads cause exc. */ -#define XCHAL_UNALIGNED_STORE_EXCEPTION 0 /* unaligned stores cause exc.*/ -#define XCHAL_UNALIGNED_LOAD_HW 1 /* unaligned loads work in hw */ -#define XCHAL_UNALIGNED_STORE_HW 1 /* unaligned stores work in hw*/ - -#define XCHAL_SW_VERSION 1200008 /* sw version of this header */ - -#define XCHAL_CORE_ID "X4H3I16w2D48w3a_2017_8" /* alphanum core name - (CoreID) set in the Xtensa - Processor Generator */ - -#define XCHAL_BUILD_UNIQUE_ID 0x00072B8F /* 22-bit sw build ID */ - -/* - * These definitions describe the hardware targeted by this software. - */ -#define XCHAL_HW_CONFIGID0 0xC3F3FBFE /* ConfigID hi 32 bits*/ -#define XCHAL_HW_CONFIGID1 0x1544813C /* ConfigID lo 32 bits*/ -#define XCHAL_HW_VERSION_NAME "LX4.0.5" /* full version name */ -#define XCHAL_HW_VERSION_MAJOR 2400 /* major ver# of targeted hw */ -#define XCHAL_HW_VERSION_MINOR 5 /* minor ver# of targeted hw */ -#define XCHAL_HW_VERSION 240005 /* major*100+minor */ -#define XCHAL_HW_REL_LX4 1 -#define XCHAL_HW_REL_LX4_0 1 -#define XCHAL_HW_REL_LX4_0_5 1 -#define XCHAL_HW_CONFIGID_RELIABLE 1 -/* If software targets a *range* of hardware versions, these are the bounds: */ -#define XCHAL_HW_MIN_VERSION_MAJOR 2400 /* major v of earliest tgt hw */ -#define XCHAL_HW_MIN_VERSION_MINOR 5 /* minor v of earliest tgt hw */ -#define XCHAL_HW_MIN_VERSION 240005 /* earliest targeted hw */ -#define XCHAL_HW_MAX_VERSION_MAJOR 2400 /* major v of latest tgt hw */ -#define XCHAL_HW_MAX_VERSION_MINOR 5 /* minor v of latest tgt hw */ -#define XCHAL_HW_MAX_VERSION 240005 /* latest targeted hw */ - - -/*---------------------------------------------------------------------- - CACHE - ----------------------------------------------------------------------*/ - -#define XCHAL_ICACHE_LINESIZE 64 /* I-cache line size in bytes */ -#define XCHAL_DCACHE_LINESIZE 64 /* D-cache line size in bytes */ -#define XCHAL_ICACHE_LINEWIDTH 6 /* log2(I line size in bytes) */ -#define XCHAL_DCACHE_LINEWIDTH 6 /* log2(D line size in bytes) */ - -#define XCHAL_ICACHE_SIZE 16384 /* I-cache size in bytes or 0 */ -#define XCHAL_DCACHE_SIZE 49152 /* D-cache size in bytes or 0 */ - -#define XCHAL_DCACHE_IS_WRITEBACK 1 /* writeback feature */ -#define XCHAL_DCACHE_IS_COHERENT 0 /* MP coherence feature */ - -#define XCHAL_HAVE_PREFETCH 1 /* PREFCTL register */ -#define XCHAL_HAVE_PREFETCH_L1 0 /* prefetch to L1 dcache */ -#define XCHAL_PREFETCH_CASTOUT_LINES 1 /* dcache pref. castout bufsz */ -#define XCHAL_PREFETCH_ENTRIES 8 /* cache prefetch entries */ -#define XCHAL_PREFETCH_BLOCK_ENTRIES 0 /* prefetch block streams */ -#define XCHAL_HAVE_CACHE_BLOCKOPS 0 /* block prefetch for caches */ -#define XCHAL_HAVE_ICACHE_TEST 1 /* Icache test instructions */ -#define XCHAL_HAVE_DCACHE_TEST 1 /* Dcache test instructions */ -#define XCHAL_HAVE_ICACHE_DYN_WAYS 0 /* Icache dynamic way support */ -#define XCHAL_HAVE_DCACHE_DYN_WAYS 0 /* Dcache dynamic way support */ - - - - -/**************************************************************************** - Parameters Useful for PRIVILEGED (Supervisory or Non-Virtualized) Code - ****************************************************************************/ - - -#ifndef XTENSA_HAL_NON_PRIVILEGED_ONLY - -/*---------------------------------------------------------------------- - CACHE - ----------------------------------------------------------------------*/ - -#define XCHAL_HAVE_PIF 1 /* any outbound bus present */ - -#define XCHAL_HAVE_AXI 0 /* AXI bus */ -#define XCHAL_HAVE_AXI_ECC 0 /* ECC on AXI bus */ -#define XCHAL_HAVE_ACELITE 0 /* ACELite bus */ - -#define XCHAL_HAVE_PIF_WR_RESP 0 /* pif write response */ -#define XCHAL_HAVE_PIF_REQ_ATTR 1 /* pif attribute */ - -/* If present, cache size in bytes == (ways * 2^(linewidth + setwidth)). */ - -/* Number of cache sets in log2(lines per way): */ -#define XCHAL_ICACHE_SETWIDTH 7 -#define XCHAL_DCACHE_SETWIDTH 8 - -/* Cache set associativity (number of ways): */ -#define XCHAL_ICACHE_WAYS 2 -#define XCHAL_DCACHE_WAYS 3 - -/* Cache features: */ -#define XCHAL_ICACHE_LINE_LOCKABLE 1 -#define XCHAL_DCACHE_LINE_LOCKABLE 1 -#define XCHAL_ICACHE_ECC_PARITY XTHAL_MEMEP_ECC -#define XCHAL_DCACHE_ECC_PARITY XTHAL_MEMEP_ECC - -/* Cache access size in bytes (affects operation of SICW instruction): */ -#define XCHAL_ICACHE_ACCESS_SIZE 8 -#define XCHAL_DCACHE_ACCESS_SIZE 8 - -#define XCHAL_DCACHE_BANKS 1 /* number of banks */ - -/* Number of encoded cache attr bits (see for decoded bits): */ -#define XCHAL_CA_BITS 4 - - -/*---------------------------------------------------------------------- - INTERNAL I/D RAM/ROMs and XLMI - ----------------------------------------------------------------------*/ -#define XCHAL_NUM_INSTROM 0 /* number of core instr. ROMs */ -#define XCHAL_NUM_INSTRAM 0 /* number of core instr. RAMs */ -#define XCHAL_NUM_DATAROM 0 /* number of core data ROMs */ -#define XCHAL_NUM_DATARAM 0 /* number of core data RAMs */ -#define XCHAL_NUM_URAM 0 /* number of core unified RAMs*/ -#define XCHAL_NUM_XLMI 0 /* number of core XLMI ports */ - -#define XCHAL_HAVE_IDMA 0 -#define XCHAL_HAVE_IDMA_TRANSPOSE 0 - -#define XCHAL_HAVE_IMEM_LOADSTORE 1 /* can load/store to IROM/IRAM*/ - - -/*---------------------------------------------------------------------- - INTERRUPTS and TIMERS - ----------------------------------------------------------------------*/ - -#define XCHAL_HAVE_INTERRUPTS 1 /* interrupt option */ -#define XCHAL_HAVE_HIGHPRI_INTERRUPTS 1 /* med/high-pri. interrupts */ -#define XCHAL_HAVE_NMI 1 /* non-maskable interrupt */ -#define XCHAL_HAVE_CCOUNT 1 /* CCOUNT reg. (timer option) */ -#define XCHAL_NUM_TIMERS 3 /* number of CCOMPAREn regs */ -#define XCHAL_NUM_INTERRUPTS 21 /* number of interrupts */ -#define XCHAL_NUM_INTERRUPTS_LOG2 5 /* ceil(log2(NUM_INTERRUPTS)) */ -#define XCHAL_NUM_EXTINTERRUPTS 8 /* num of external interrupts */ -#define XCHAL_NUM_INTLEVELS 6 /* number of interrupt levels - (not including level zero) */ -#define XCHAL_EXCM_LEVEL 5 /* level masked by PS.EXCM */ - /* (always 1 in XEA1; levels 2 .. EXCM_LEVEL are "medium priority") */ - -/* Masks of interrupts at each interrupt level: */ -#define XCHAL_INTLEVEL1_MASK 0x0000000F -#define XCHAL_INTLEVEL2_MASK 0x000000F0 -#define XCHAL_INTLEVEL3_MASK 0x00000F00 -#define XCHAL_INTLEVEL4_MASK 0x00007000 -#define XCHAL_INTLEVEL5_MASK 0x000F8000 -#define XCHAL_INTLEVEL6_MASK 0x00000000 -#define XCHAL_INTLEVEL7_MASK 0x00100000 - -/* Masks of interrupts at each range 1..n of interrupt levels: */ -#define XCHAL_INTLEVEL1_ANDBELOW_MASK 0x0000000F -#define XCHAL_INTLEVEL2_ANDBELOW_MASK 0x000000FF -#define XCHAL_INTLEVEL3_ANDBELOW_MASK 0x00000FFF -#define XCHAL_INTLEVEL4_ANDBELOW_MASK 0x00007FFF -#define XCHAL_INTLEVEL5_ANDBELOW_MASK 0x000FFFFF -#define XCHAL_INTLEVEL6_ANDBELOW_MASK 0x000FFFFF -#define XCHAL_INTLEVEL7_ANDBELOW_MASK 0x001FFFFF - -/* Level of each interrupt: */ -#define XCHAL_INT0_LEVEL 1 -#define XCHAL_INT1_LEVEL 1 -#define XCHAL_INT2_LEVEL 1 -#define XCHAL_INT3_LEVEL 1 -#define XCHAL_INT4_LEVEL 2 -#define XCHAL_INT5_LEVEL 2 -#define XCHAL_INT6_LEVEL 2 -#define XCHAL_INT7_LEVEL 2 -#define XCHAL_INT8_LEVEL 3 -#define XCHAL_INT9_LEVEL 3 -#define XCHAL_INT10_LEVEL 3 -#define XCHAL_INT11_LEVEL 3 -#define XCHAL_INT12_LEVEL 4 -#define XCHAL_INT13_LEVEL 4 -#define XCHAL_INT14_LEVEL 4 -#define XCHAL_INT15_LEVEL 5 -#define XCHAL_INT16_LEVEL 5 -#define XCHAL_INT17_LEVEL 5 -#define XCHAL_INT18_LEVEL 5 -#define XCHAL_INT19_LEVEL 5 -#define XCHAL_INT20_LEVEL 7 -#define XCHAL_DEBUGLEVEL 6 /* debug interrupt level */ -#define XCHAL_HAVE_DEBUG_EXTERN_INT 1 /* OCD external db interrupt */ -#define XCHAL_NMILEVEL 7 /* NMI "level" (for use with - EXCSAVE/EPS/EPC_n, RFI n) */ - -/* Type of each interrupt: */ -#define XCHAL_INT0_TYPE XTHAL_INTTYPE_SOFTWARE -#define XCHAL_INT1_TYPE XTHAL_INTTYPE_TIMER -#define XCHAL_INT2_TYPE XTHAL_INTTYPE_EXTERN_LEVEL -#define XCHAL_INT3_TYPE XTHAL_INTTYPE_SOFTWARE -#define XCHAL_INT4_TYPE XTHAL_INTTYPE_SOFTWARE -#define XCHAL_INT5_TYPE XTHAL_INTTYPE_TIMER -#define XCHAL_INT6_TYPE XTHAL_INTTYPE_EXTERN_LEVEL -#define XCHAL_INT7_TYPE XTHAL_INTTYPE_SOFTWARE -#define XCHAL_INT8_TYPE XTHAL_INTTYPE_SOFTWARE -#define XCHAL_INT9_TYPE XTHAL_INTTYPE_TIMER -#define XCHAL_INT10_TYPE XTHAL_INTTYPE_EXTERN_LEVEL -#define XCHAL_INT11_TYPE XTHAL_INTTYPE_SOFTWARE -#define XCHAL_INT12_TYPE XTHAL_INTTYPE_SOFTWARE -#define XCHAL_INT13_TYPE XTHAL_INTTYPE_EXTERN_LEVEL -#define XCHAL_INT14_TYPE XTHAL_INTTYPE_SOFTWARE -#define XCHAL_INT15_TYPE XTHAL_INTTYPE_SOFTWARE -#define XCHAL_INT16_TYPE XTHAL_INTTYPE_EXTERN_LEVEL -#define XCHAL_INT17_TYPE XTHAL_INTTYPE_EXTERN_LEVEL -#define XCHAL_INT18_TYPE XTHAL_INTTYPE_EXTERN_LEVEL -#define XCHAL_INT19_TYPE XTHAL_INTTYPE_SOFTWARE -#define XCHAL_INT20_TYPE XTHAL_INTTYPE_NMI - -/* Masks of interrupts for each type of interrupt: */ -#define XCHAL_INTTYPE_MASK_UNCONFIGURED 0xFFE00000 -#define XCHAL_INTTYPE_MASK_SOFTWARE 0x0008D999 -#define XCHAL_INTTYPE_MASK_EXTERN_EDGE 0x00000000 -#define XCHAL_INTTYPE_MASK_EXTERN_LEVEL 0x00072444 -#define XCHAL_INTTYPE_MASK_TIMER 0x00000222 -#define XCHAL_INTTYPE_MASK_NMI 0x00100000 -#define XCHAL_INTTYPE_MASK_WRITE_ERROR 0x00000000 -#define XCHAL_INTTYPE_MASK_PROFILING 0x00000000 -#define XCHAL_INTTYPE_MASK_IDMA_DONE 0x00000000 -#define XCHAL_INTTYPE_MASK_IDMA_ERR 0x00000000 -#define XCHAL_INTTYPE_MASK_GS_ERR 0x00000000 - -/* Interrupt numbers assigned to specific interrupt sources: */ -#define XCHAL_TIMER0_INTERRUPT 1 /* CCOMPARE0 */ -#define XCHAL_TIMER1_INTERRUPT 5 /* CCOMPARE1 */ -#define XCHAL_TIMER2_INTERRUPT 9 /* CCOMPARE2 */ -#define XCHAL_TIMER3_INTERRUPT XTHAL_TIMER_UNCONFIGURED -#define XCHAL_NMI_INTERRUPT 20 /* non-maskable interrupt */ - -/* Interrupt numbers for levels at which only one interrupt is configured: */ -#define XCHAL_INTLEVEL7_NUM 20 -/* (There are many interrupts each at level(s) 1, 2, 3, 4, 5.) */ - - -/* - * External interrupt mapping. - * These macros describe how Xtensa processor interrupt numbers - * (as numbered internally, eg. in INTERRUPT and INTENABLE registers) - * map to external BInterrupt pins, for those interrupts - * configured as external (level-triggered, edge-triggered, or NMI). - * See the Xtensa processor databook for more details. - */ - -/* Core interrupt numbers mapped to each EXTERNAL BInterrupt pin number: */ -#define XCHAL_EXTINT0_NUM 2 /* (intlevel 1) */ -#define XCHAL_EXTINT1_NUM 6 /* (intlevel 2) */ -#define XCHAL_EXTINT2_NUM 10 /* (intlevel 3) */ -#define XCHAL_EXTINT3_NUM 13 /* (intlevel 4) */ -#define XCHAL_EXTINT4_NUM 16 /* (intlevel 5) */ -#define XCHAL_EXTINT5_NUM 17 /* (intlevel 5) */ -#define XCHAL_EXTINT6_NUM 18 /* (intlevel 5) */ -#define XCHAL_EXTINT7_NUM 20 /* (intlevel 7) */ -/* EXTERNAL BInterrupt pin numbers mapped to each core interrupt number: */ -#define XCHAL_INT2_EXTNUM 0 /* (intlevel 1) */ -#define XCHAL_INT6_EXTNUM 1 /* (intlevel 2) */ -#define XCHAL_INT10_EXTNUM 2 /* (intlevel 3) */ -#define XCHAL_INT13_EXTNUM 3 /* (intlevel 4) */ -#define XCHAL_INT16_EXTNUM 4 /* (intlevel 5) */ -#define XCHAL_INT17_EXTNUM 5 /* (intlevel 5) */ -#define XCHAL_INT18_EXTNUM 6 /* (intlevel 5) */ -#define XCHAL_INT20_EXTNUM 7 /* (intlevel 7) */ - - -/*---------------------------------------------------------------------- - EXCEPTIONS and VECTORS - ----------------------------------------------------------------------*/ - -#define XCHAL_XEA_VERSION 2 /* Xtensa Exception Architecture - number: 1 == XEA1 (old) - 2 == XEA2 (new) - 0 == XEAX (extern) or TX */ -#define XCHAL_HAVE_XEA1 0 /* Exception Architecture 1 */ -#define XCHAL_HAVE_XEA2 1 /* Exception Architecture 2 */ -#define XCHAL_HAVE_XEAX 0 /* External Exception Arch. */ -#define XCHAL_HAVE_EXCEPTIONS 1 /* exception option */ -#define XCHAL_HAVE_HALT 0 /* halt architecture option */ -#define XCHAL_HAVE_BOOTLOADER 0 /* boot loader (for TX) */ -#define XCHAL_HAVE_MEM_ECC_PARITY 1 /* local memory ECC/parity */ -#define XCHAL_HAVE_VECTOR_SELECT 1 /* relocatable vectors */ -#define XCHAL_HAVE_VECBASE 1 /* relocatable vectors */ -#define XCHAL_VECBASE_RESET_VADDR 0xBEFE0800 /* VECBASE reset value */ -#define XCHAL_VECBASE_RESET_PADDR 0xBEFE0800 -#define XCHAL_RESET_VECBASE_OVERLAP 0 - -#define XCHAL_RESET_VECTOR0_VADDR 0xBEFE0000 -#define XCHAL_RESET_VECTOR0_PADDR 0xBEFE0000 -#define XCHAL_RESET_VECTOR1_VADDR 0xBE800000 -#define XCHAL_RESET_VECTOR1_PADDR 0xBE800000 -#define XCHAL_RESET_VECTOR_VADDR 0xBEFE0000 -#define XCHAL_RESET_VECTOR_PADDR 0xBEFE0000 -#define XCHAL_MEMERROR_VECTOR0_VADDR 0xBEFE0400 -#define XCHAL_MEMERROR_VECTOR0_PADDR 0xBEFE0400 -#define XCHAL_MEMERROR_VECTOR1_VADDR 0xBE800400 -#define XCHAL_MEMERROR_VECTOR1_PADDR 0xBE800400 -#define XCHAL_MEMERROR_VECTOR_VADDR 0xBEFE0400 -#define XCHAL_MEMERROR_VECTOR_PADDR 0xBEFE0400 -#define XCHAL_USER_VECOFS 0x00000340 -#define XCHAL_USER_VECTOR_VADDR 0xBEFE0B40 -#define XCHAL_USER_VECTOR_PADDR 0xBEFE0B40 -#define XCHAL_KERNEL_VECOFS 0x00000300 -#define XCHAL_KERNEL_VECTOR_VADDR 0xBEFE0B00 -#define XCHAL_KERNEL_VECTOR_PADDR 0xBEFE0B00 -#define XCHAL_DOUBLEEXC_VECOFS 0x000003C0 -#define XCHAL_DOUBLEEXC_VECTOR_VADDR 0xBEFE0BC0 -#define XCHAL_DOUBLEEXC_VECTOR_PADDR 0xBEFE0BC0 -#define XCHAL_WINDOW_OF4_VECOFS 0x00000000 -#define XCHAL_WINDOW_UF4_VECOFS 0x00000040 -#define XCHAL_WINDOW_OF8_VECOFS 0x00000080 -#define XCHAL_WINDOW_UF8_VECOFS 0x000000C0 -#define XCHAL_WINDOW_OF12_VECOFS 0x00000100 -#define XCHAL_WINDOW_UF12_VECOFS 0x00000140 -#define XCHAL_WINDOW_VECTORS_VADDR 0xBEFE0800 -#define XCHAL_WINDOW_VECTORS_PADDR 0xBEFE0800 -#define XCHAL_INTLEVEL2_VECOFS 0x00000180 -#define XCHAL_INTLEVEL2_VECTOR_VADDR 0xBEFE0980 -#define XCHAL_INTLEVEL2_VECTOR_PADDR 0xBEFE0980 -#define XCHAL_INTLEVEL3_VECOFS 0x000001C0 -#define XCHAL_INTLEVEL3_VECTOR_VADDR 0xBEFE09C0 -#define XCHAL_INTLEVEL3_VECTOR_PADDR 0xBEFE09C0 -#define XCHAL_INTLEVEL4_VECOFS 0x00000200 -#define XCHAL_INTLEVEL4_VECTOR_VADDR 0xBEFE0A00 -#define XCHAL_INTLEVEL4_VECTOR_PADDR 0xBEFE0A00 -#define XCHAL_INTLEVEL5_VECOFS 0x00000240 -#define XCHAL_INTLEVEL5_VECTOR_VADDR 0xBEFE0A40 -#define XCHAL_INTLEVEL5_VECTOR_PADDR 0xBEFE0A40 -#define XCHAL_INTLEVEL6_VECOFS 0x00000280 -#define XCHAL_INTLEVEL6_VECTOR_VADDR 0xBEFE0A80 -#define XCHAL_INTLEVEL6_VECTOR_PADDR 0xBEFE0A80 -#define XCHAL_DEBUG_VECOFS XCHAL_INTLEVEL6_VECOFS -#define XCHAL_DEBUG_VECTOR_VADDR XCHAL_INTLEVEL6_VECTOR_VADDR -#define XCHAL_DEBUG_VECTOR_PADDR XCHAL_INTLEVEL6_VECTOR_PADDR -#define XCHAL_NMI_VECOFS 0x000002C0 -#define XCHAL_NMI_VECTOR_VADDR 0xBEFE0AC0 -#define XCHAL_NMI_VECTOR_PADDR 0xBEFE0AC0 -#define XCHAL_INTLEVEL7_VECOFS XCHAL_NMI_VECOFS -#define XCHAL_INTLEVEL7_VECTOR_VADDR XCHAL_NMI_VECTOR_VADDR -#define XCHAL_INTLEVEL7_VECTOR_PADDR XCHAL_NMI_VECTOR_PADDR - - -/*---------------------------------------------------------------------- - DEBUG MODULE - ----------------------------------------------------------------------*/ - -/* Misc */ -#define XCHAL_HAVE_DEBUG_ERI 0 /* ERI to debug module */ -#define XCHAL_HAVE_DEBUG_APB 0 /* APB to debug module */ -#define XCHAL_HAVE_DEBUG_JTAG 0 /* JTAG to debug module */ - -/* On-Chip Debug (OCD) */ -#define XCHAL_HAVE_OCD 1 /* OnChipDebug option */ -#define XCHAL_NUM_IBREAK 2 /* number of IBREAKn regs */ -#define XCHAL_NUM_DBREAK 2 /* number of DBREAKn regs */ -#define XCHAL_HAVE_OCD_DIR_ARRAY 1 /* faster OCD option (to LX4) */ -#define XCHAL_HAVE_OCD_LS32DDR 0 /* L32DDR/S32DDR (faster OCD) */ - -/* TRAX (in core) */ -#define XCHAL_HAVE_TRAX 0 /* TRAX in debug module */ -#define XCHAL_TRAX_MEM_SIZE 0 /* TRAX memory size in bytes */ -#define XCHAL_TRAX_MEM_SHAREABLE 0 /* start/end regs; ready sig. */ -#define XCHAL_TRAX_ATB_WIDTH 0 /* ATB width (bits), 0=no ATB */ -#define XCHAL_TRAX_TIME_WIDTH 0 /* timestamp bitwidth, 0=none */ - -/* Perf counters */ -#define XCHAL_NUM_PERF_COUNTERS 0 /* performance counters */ - - -/*---------------------------------------------------------------------- - MMU - ----------------------------------------------------------------------*/ - -/* See core-matmap.h header file for more details. */ - -#define XCHAL_HAVE_TLBS 1 /* inverse of HAVE_CACHEATTR */ -#define XCHAL_HAVE_SPANNING_WAY 1 /* one way maps I+D 4GB vaddr */ -#define XCHAL_SPANNING_WAY 0 /* TLB spanning way number */ -#define XCHAL_HAVE_IDENTITY_MAP 0 /* vaddr == paddr always */ -#define XCHAL_HAVE_CACHEATTR 0 /* CACHEATTR register present */ -#define XCHAL_HAVE_MIMIC_CACHEATTR 0 /* region protection */ -#define XCHAL_HAVE_XLT_CACHEATTR 1 /* region prot. w/translation */ -#define XCHAL_HAVE_PTP_MMU 0 /* full MMU (with page table - [autorefill] and protection) - usable for an MMU-based OS */ - -/* If none of the above last 5 are set, it's a custom TLB configuration. */ - -#define XCHAL_MMU_ASID_BITS 0 /* number of bits in ASIDs */ -#define XCHAL_MMU_RINGS 1 /* number of rings (1..4) */ -#define XCHAL_MMU_RING_BITS 0 /* num of bits in RING field */ - -/*---------------------------------------------------------------------- - MPU - ----------------------------------------------------------------------*/ -#define XCHAL_HAVE_MPU 0 -#define XCHAL_MPU_ENTRIES 0 - -#define XCHAL_MPU_ALIGN_REQ 1 /* MPU requires alignment of entries to background map */ -#define XCHAL_MPU_BACKGROUND_ENTRIES 0 /* number of entries in bg map*/ -#define XCHAL_MPU_BG_CACHEADRDIS 0 /* default CACHEADRDIS for bg */ - -#define XCHAL_MPU_ALIGN_BITS 0 -#define XCHAL_MPU_ALIGN 0 - -#endif /* !XTENSA_HAL_NON_PRIVILEGED_ONLY */ - - -#endif /* _XTENSA_CORE_CONFIGURATION_H */ - -#else - -#error "xcc should not use this header" - -#endif /* __XCC__ */ diff --git a/src/platform/apollolake/include/arch/xtensa/config/core-matmap.h b/src/platform/apollolake/include/arch/xtensa/config/core-matmap.h deleted file mode 100644 index 9cea939f7534..000000000000 --- a/src/platform/apollolake/include/arch/xtensa/config/core-matmap.h +++ /dev/null @@ -1,323 +0,0 @@ -/* - * xtensa/config/core-matmap.h -- Memory access and translation mapping - * parameters (CHAL) of the Xtensa processor core configuration. - * - * If you are using Xtensa Tools, see (which includes - * this file) for more details. - * - * In the Xtensa processor products released to date, all parameters - * defined in this file are derivable (at least in theory) from - * information contained in the core-isa.h header file. - * In particular, the following core configuration parameters are relevant: - * XCHAL_HAVE_CACHEATTR - * XCHAL_HAVE_MIMIC_CACHEATTR - * XCHAL_HAVE_XLT_CACHEATTR - * XCHAL_HAVE_PTP_MMU - * XCHAL_ITLB_ARF_ENTRIES_LOG2 - * XCHAL_DTLB_ARF_ENTRIES_LOG2 - * XCHAL_DCACHE_IS_WRITEBACK - * XCHAL_ICACHE_SIZE (presence of I-cache) - * XCHAL_DCACHE_SIZE (presence of D-cache) - * XCHAL_HW_VERSION_MAJOR - * XCHAL_HW_VERSION_MINOR - */ - -/* Copyright (c) 1999-2018 Tensilica Inc. - - Permission is hereby granted, free of charge, to any person obtaining - a copy of this software and associated documentation files (the - "Software"), to deal in the Software without restriction, including - without limitation the rights to use, copy, modify, merge, publish, - distribute, sublicense, and/or sell copies of the Software, and to - permit persons to whom the Software is furnished to do so, subject to - the following conditions: - - The above copyright notice and this permission notice shall be included - in all copies or substantial portions of the Software. - - THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. - IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY - CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, - TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE - SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ - -#if !defined __XCC__ - -#ifndef XTENSA_CONFIG_CORE_MATMAP_H -#define XTENSA_CONFIG_CORE_MATMAP_H - - -/*---------------------------------------------------------------------- - CACHE (MEMORY ACCESS) ATTRIBUTES - ----------------------------------------------------------------------*/ - - - -/* Cache Attribute encodings -- lists of access modes for each cache attribute: */ -#define XCHAL_FCA_LIST XTHAL_FAM_EXCEPTION XCHAL_SEP \ - XTHAL_FAM_CACHED XCHAL_SEP \ - XTHAL_FAM_BYPASS XCHAL_SEP \ - XTHAL_FAM_CACHED XCHAL_SEP \ - XTHAL_FAM_CACHED XCHAL_SEP \ - XTHAL_FAM_CACHED XCHAL_SEP \ - XTHAL_FAM_EXCEPTION XCHAL_SEP \ - XTHAL_FAM_EXCEPTION XCHAL_SEP \ - XTHAL_FAM_EXCEPTION XCHAL_SEP \ - XTHAL_FAM_EXCEPTION XCHAL_SEP \ - XTHAL_FAM_EXCEPTION XCHAL_SEP \ - XTHAL_FAM_EXCEPTION XCHAL_SEP \ - XTHAL_FAM_EXCEPTION XCHAL_SEP \ - XTHAL_FAM_EXCEPTION XCHAL_SEP \ - XTHAL_FAM_EXCEPTION XCHAL_SEP \ - XTHAL_FAM_EXCEPTION -#define XCHAL_LCA_LIST XTHAL_LAM_CACHED_NOALLOC XCHAL_SEP \ - XTHAL_LAM_CACHED XCHAL_SEP \ - XTHAL_LAM_BYPASSG XCHAL_SEP \ - XTHAL_LAM_EXCEPTION XCHAL_SEP \ - XTHAL_LAM_CACHED XCHAL_SEP \ - XTHAL_LAM_CACHED XCHAL_SEP \ - XTHAL_LAM_EXCEPTION XCHAL_SEP \ - XTHAL_LAM_EXCEPTION XCHAL_SEP \ - XTHAL_LAM_EXCEPTION XCHAL_SEP \ - XTHAL_LAM_EXCEPTION XCHAL_SEP \ - XTHAL_LAM_EXCEPTION XCHAL_SEP \ - XTHAL_LAM_EXCEPTION XCHAL_SEP \ - XTHAL_LAM_EXCEPTION XCHAL_SEP \ - XTHAL_LAM_EXCEPTION XCHAL_SEP \ - XTHAL_LAM_ISOLATE XCHAL_SEP \ - XTHAL_LAM_EXCEPTION -#define XCHAL_SCA_LIST XTHAL_SAM_WRITETHRU XCHAL_SEP \ - XTHAL_SAM_WRITETHRU XCHAL_SEP \ - XTHAL_SAM_BYPASS XCHAL_SEP \ - XTHAL_SAM_EXCEPTION XCHAL_SEP \ - XTHAL_SAM_WRITEBACK XCHAL_SEP \ - XTHAL_SAM_WRITEBACK_NOALLOC XCHAL_SEP \ - XTHAL_SAM_EXCEPTION XCHAL_SEP \ - XTHAL_SAM_EXCEPTION XCHAL_SEP \ - XTHAL_SAM_EXCEPTION XCHAL_SEP \ - XTHAL_SAM_EXCEPTION XCHAL_SEP \ - XTHAL_SAM_EXCEPTION XCHAL_SEP \ - XTHAL_SAM_EXCEPTION XCHAL_SEP \ - XTHAL_SAM_EXCEPTION XCHAL_SEP \ - XTHAL_SAM_EXCEPTION XCHAL_SEP \ - XTHAL_SAM_ISOLATE XCHAL_SEP \ - XTHAL_SAM_EXCEPTION - -#define XCHAL_CA_R (0xC0 | 0x40000000) -#define XCHAL_CA_RX (0xD0 | 0x40000000) -#define XCHAL_CA_RW (0xE0 | 0x40000000) -#define XCHAL_CA_RWX (0xF0 | 0x40000000) - -/* - * Specific encoded cache attribute values of general interest. - * If a specific cache mode is not available, the closest available - * one is returned instead (eg. writethru instead of writeback, - * bypass instead of writethru). - */ -#define XCHAL_CA_BYPASS 2 /* cache disabled (bypassed) mode */ -#define XCHAL_CA_WRITETHRU 1 /* cache enabled (write-through) mode */ -#define XCHAL_CA_WRITEBACK 4 /* cache enabled (write-back) mode */ -#define XCHAL_HAVE_CA_WRITEBACK_NOALLOC 1 /* write-back no-allocate availability */ -#define XCHAL_CA_WRITEBACK_NOALLOC 5 /* cache enabled (write-back no-allocate) mode */ -#define XCHAL_CA_ILLEGAL 15 /* no access allowed (all cause exceptions) mode */ -#define XCHAL_CA_ISOLATE 14 /* cache isolate (accesses go to cache not memory) mode */ - -/*---------------------------------------------------------------------- - MMU - ----------------------------------------------------------------------*/ - -/* - * General notes on MMU parameters. - * - * Terminology: - * ASID = address-space ID (acts as an "extension" of virtual addresses) - * VPN = virtual page number - * PPN = physical page number - * CA = encoded cache attribute (access modes) - * TLB = translation look-aside buffer (term is stretched somewhat here) - * I = instruction (fetch accesses) - * D = data (load and store accesses) - * way = each TLB (ITLB and DTLB) consists of a number of "ways" - * that simultaneously match the virtual address of an access; - * a TLB successfully translates a virtual address if exactly - * one way matches the vaddr; if none match, it is a miss; - * if multiple match, one gets a "multihit" exception; - * each way can be independently configured in terms of number of - * entries, page sizes, which fields are writable or constant, etc. - * set = group of contiguous ways with exactly identical parameters - * ARF = auto-refill; hardware services a 1st-level miss by loading a PTE - * from the page table and storing it in one of the auto-refill ways; - * if this PTE load also misses, a miss exception is posted for s/w. - * min-wired = a "min-wired" way can be used to map a single (minimum-sized) - * page arbitrarily under program control; it has a single entry, - * is non-auto-refill (some other way(s) must be auto-refill), - * all its fields (VPN, PPN, ASID, CA) are all writable, and it - * supports the XCHAL_MMU_MIN_PTE_PAGE_SIZE page size (a current - * restriction is that this be the only page size it supports). - * - * TLB way entries are virtually indexed. - * TLB ways that support multiple page sizes: - * - must have all writable VPN and PPN fields; - * - can only use one page size at any given time (eg. setup at startup), - * selected by the respective ITLBCFG or DTLBCFG special register, - * whose bits n*4+3 .. n*4 index the list of page sizes for way n - * (XCHAL_xTLB_SETm_PAGESZ_LOG2_LIST for set m corresponding to way n); - * this list may be sparse for auto-refill ways because auto-refill - * ways have independent lists of supported page sizes sharing a - * common encoding with PTE entries; the encoding is the index into - * this list; unsupported sizes for a given way are zero in the list; - * selecting unsupported sizes results in undefine hardware behaviour; - * - is only possible for ways 0 thru 7 (due to ITLBCFG/DTLBCFG definition). - */ - -#define XCHAL_MMU_ASID_INVALID 0 /* ASID value indicating invalid address space */ -#define XCHAL_MMU_ASID_KERNEL 0 /* ASID value indicating kernel (ring 0) address space */ -#define XCHAL_MMU_SR_BITS 0 /* number of size-restriction bits supported */ -#define XCHAL_MMU_CA_BITS 4 /* number of bits needed to hold cache attribute encoding */ -#define XCHAL_MMU_MAX_PTE_PAGE_SIZE 29 /* max page size in a PTE structure (log2) */ -#define XCHAL_MMU_MIN_PTE_PAGE_SIZE 29 /* min page size in a PTE structure (log2) */ - - -/*** Instruction TLB: ***/ - -#define XCHAL_ITLB_WAY_BITS 0 /* number of bits holding the ways */ -#define XCHAL_ITLB_WAYS 1 /* number of ways (n-way set-associative TLB) */ -#define XCHAL_ITLB_ARF_WAYS 0 /* number of auto-refill ways */ -#define XCHAL_ITLB_SETS 1 /* number of sets (groups of ways with identical settings) */ - -/* Way set to which each way belongs: */ -#define XCHAL_ITLB_WAY0_SET 0 - -/* Ways sets that are used by hardware auto-refill (ARF): */ -#define XCHAL_ITLB_ARF_SETS 0 /* number of auto-refill sets */ - -/* Way sets that are "min-wired" (see terminology comment above): */ -#define XCHAL_ITLB_MINWIRED_SETS 0 /* number of "min-wired" sets */ - - -/* ITLB way set 0 (group of ways 0 thru 0): */ -#define XCHAL_ITLB_SET0_WAY 0 /* index of first way in this way set */ -#define XCHAL_ITLB_SET0_WAYS 1 /* number of (contiguous) ways in this way set */ -#define XCHAL_ITLB_SET0_ENTRIES_LOG2 3 /* log2(number of entries in this way) */ -#define XCHAL_ITLB_SET0_ENTRIES 8 /* number of entries in this way (always a power of 2) */ -#define XCHAL_ITLB_SET0_ARF 0 /* 1=autorefill by h/w, 0=non-autorefill (wired/constant/static) */ -#define XCHAL_ITLB_SET0_PAGESIZES 1 /* number of supported page sizes in this way */ -#define XCHAL_ITLB_SET0_PAGESZ_BITS 0 /* number of bits to encode the page size */ -#define XCHAL_ITLB_SET0_PAGESZ_LOG2_MIN 29 /* log2(minimum supported page size) */ -#define XCHAL_ITLB_SET0_PAGESZ_LOG2_MAX 29 /* log2(maximum supported page size) */ -#define XCHAL_ITLB_SET0_PAGESZ_LOG2_LIST 29 /* list of log2(page size)s, separated by XCHAL_SEP; - 2^PAGESZ_BITS entries in list, unsupported entries are zero */ -#define XCHAL_ITLB_SET0_ASID_CONSTMASK 0 /* constant ASID bits; 0 if all writable */ -#define XCHAL_ITLB_SET0_VPN_CONSTMASK 0x00000000 /* constant VPN bits, not including entry index bits; 0 if all writable */ -#define XCHAL_ITLB_SET0_PPN_CONSTMASK 0 /* constant PPN bits, including entry index bits; 0 if all writable */ -#define XCHAL_ITLB_SET0_CA_CONSTMASK 0 /* constant CA bits; 0 if all writable */ -#define XCHAL_ITLB_SET0_ASID_RESET 0 /* 1 if ASID reset values defined (and all writable); 0 otherwise */ -#define XCHAL_ITLB_SET0_VPN_RESET 0 /* 1 if VPN reset values defined (and all writable); 0 otherwise */ -#define XCHAL_ITLB_SET0_PPN_RESET 1 /* 1 if PPN reset values defined (and all writable); 0 otherwise */ -#define XCHAL_ITLB_SET0_CA_RESET 1 /* 1 if CA reset values defined (and all writable); 0 otherwise */ -/* Constant VPN values for each entry of ITLB way set 0 (because VPN_CONSTMASK is non-zero): */ -#define XCHAL_ITLB_SET0_E0_VPN_CONST 0x00000000 -#define XCHAL_ITLB_SET0_E1_VPN_CONST 0x20000000 -#define XCHAL_ITLB_SET0_E2_VPN_CONST 0x40000000 -#define XCHAL_ITLB_SET0_E3_VPN_CONST 0x60000000 -#define XCHAL_ITLB_SET0_E4_VPN_CONST 0x80000000 -#define XCHAL_ITLB_SET0_E5_VPN_CONST 0xA0000000 -#define XCHAL_ITLB_SET0_E6_VPN_CONST 0xC0000000 -#define XCHAL_ITLB_SET0_E7_VPN_CONST 0xE0000000 -/* Reset PPN values for each entry of ITLB way set 0 (because SET0_PPN_RESET is non-zero): */ -#define XCHAL_ITLB_SET0_E0_PPN_RESET 0x00000000 -#define XCHAL_ITLB_SET0_E1_PPN_RESET 0x20000000 -#define XCHAL_ITLB_SET0_E2_PPN_RESET 0x40000000 -#define XCHAL_ITLB_SET0_E3_PPN_RESET 0x60000000 -#define XCHAL_ITLB_SET0_E4_PPN_RESET 0x80000000 -#define XCHAL_ITLB_SET0_E5_PPN_RESET 0xA0000000 -#define XCHAL_ITLB_SET0_E6_PPN_RESET 0xC0000000 -#define XCHAL_ITLB_SET0_E7_PPN_RESET 0xE0000000 -/* Reset CA values for each entry of ITLB way set 0 (because SET0_CA_RESET is non-zero): */ -#define XCHAL_ITLB_SET0_E0_CA_RESET 0x02 -#define XCHAL_ITLB_SET0_E1_CA_RESET 0x02 -#define XCHAL_ITLB_SET0_E2_CA_RESET 0x02 -#define XCHAL_ITLB_SET0_E3_CA_RESET 0x02 -#define XCHAL_ITLB_SET0_E4_CA_RESET 0x02 -#define XCHAL_ITLB_SET0_E5_CA_RESET 0x02 -#define XCHAL_ITLB_SET0_E6_CA_RESET 0x02 -#define XCHAL_ITLB_SET0_E7_CA_RESET 0x02 - - -/*** Data TLB: ***/ - -#define XCHAL_DTLB_WAY_BITS 0 /* number of bits holding the ways */ -#define XCHAL_DTLB_WAYS 1 /* number of ways (n-way set-associative TLB) */ -#define XCHAL_DTLB_ARF_WAYS 0 /* number of auto-refill ways */ -#define XCHAL_DTLB_SETS 1 /* number of sets (groups of ways with identical settings) */ - -/* Way set to which each way belongs: */ -#define XCHAL_DTLB_WAY0_SET 0 - -/* Ways sets that are used by hardware auto-refill (ARF): */ -#define XCHAL_DTLB_ARF_SETS 0 /* number of auto-refill sets */ - -/* Way sets that are "min-wired" (see terminology comment above): */ -#define XCHAL_DTLB_MINWIRED_SETS 0 /* number of "min-wired" sets */ - - -/* DTLB way set 0 (group of ways 0 thru 0): */ -#define XCHAL_DTLB_SET0_WAY 0 /* index of first way in this way set */ -#define XCHAL_DTLB_SET0_WAYS 1 /* number of (contiguous) ways in this way set */ -#define XCHAL_DTLB_SET0_ENTRIES_LOG2 3 /* log2(number of entries in this way) */ -#define XCHAL_DTLB_SET0_ENTRIES 8 /* number of entries in this way (always a power of 2) */ -#define XCHAL_DTLB_SET0_ARF 0 /* 1=autorefill by h/w, 0=non-autorefill (wired/constant/static) */ -#define XCHAL_DTLB_SET0_PAGESIZES 1 /* number of supported page sizes in this way */ -#define XCHAL_DTLB_SET0_PAGESZ_BITS 0 /* number of bits to encode the page size */ -#define XCHAL_DTLB_SET0_PAGESZ_LOG2_MIN 29 /* log2(minimum supported page size) */ -#define XCHAL_DTLB_SET0_PAGESZ_LOG2_MAX 29 /* log2(maximum supported page size) */ -#define XCHAL_DTLB_SET0_PAGESZ_LOG2_LIST 29 /* list of log2(page size)s, separated by XCHAL_SEP; - 2^PAGESZ_BITS entries in list, unsupported entries are zero */ -#define XCHAL_DTLB_SET0_ASID_CONSTMASK 0 /* constant ASID bits; 0 if all writable */ -#define XCHAL_DTLB_SET0_VPN_CONSTMASK 0x00000000 /* constant VPN bits, not including entry index bits; 0 if all writable */ -#define XCHAL_DTLB_SET0_PPN_CONSTMASK 0 /* constant PPN bits, including entry index bits; 0 if all writable */ -#define XCHAL_DTLB_SET0_CA_CONSTMASK 0 /* constant CA bits; 0 if all writable */ -#define XCHAL_DTLB_SET0_ASID_RESET 0 /* 1 if ASID reset values defined (and all writable); 0 otherwise */ -#define XCHAL_DTLB_SET0_VPN_RESET 0 /* 1 if VPN reset values defined (and all writable); 0 otherwise */ -#define XCHAL_DTLB_SET0_PPN_RESET 1 /* 1 if PPN reset values defined (and all writable); 0 otherwise */ -#define XCHAL_DTLB_SET0_CA_RESET 1 /* 1 if CA reset values defined (and all writable); 0 otherwise */ -/* Constant VPN values for each entry of DTLB way set 0 (because VPN_CONSTMASK is non-zero): */ -#define XCHAL_DTLB_SET0_E0_VPN_CONST 0x00000000 -#define XCHAL_DTLB_SET0_E1_VPN_CONST 0x20000000 -#define XCHAL_DTLB_SET0_E2_VPN_CONST 0x40000000 -#define XCHAL_DTLB_SET0_E3_VPN_CONST 0x60000000 -#define XCHAL_DTLB_SET0_E4_VPN_CONST 0x80000000 -#define XCHAL_DTLB_SET0_E5_VPN_CONST 0xA0000000 -#define XCHAL_DTLB_SET0_E6_VPN_CONST 0xC0000000 -#define XCHAL_DTLB_SET0_E7_VPN_CONST 0xE0000000 -/* Reset PPN values for each entry of DTLB way set 0 (because SET0_PPN_RESET is non-zero): */ -#define XCHAL_DTLB_SET0_E0_PPN_RESET 0x00000000 -#define XCHAL_DTLB_SET0_E1_PPN_RESET 0x20000000 -#define XCHAL_DTLB_SET0_E2_PPN_RESET 0x40000000 -#define XCHAL_DTLB_SET0_E3_PPN_RESET 0x60000000 -#define XCHAL_DTLB_SET0_E4_PPN_RESET 0x80000000 -#define XCHAL_DTLB_SET0_E5_PPN_RESET 0xA0000000 -#define XCHAL_DTLB_SET0_E6_PPN_RESET 0xC0000000 -#define XCHAL_DTLB_SET0_E7_PPN_RESET 0xE0000000 -/* Reset CA values for each entry of DTLB way set 0 (because SET0_CA_RESET is non-zero): */ -#define XCHAL_DTLB_SET0_E0_CA_RESET 0x02 -#define XCHAL_DTLB_SET0_E1_CA_RESET 0x02 -#define XCHAL_DTLB_SET0_E2_CA_RESET 0x02 -#define XCHAL_DTLB_SET0_E3_CA_RESET 0x02 -#define XCHAL_DTLB_SET0_E4_CA_RESET 0x02 -#define XCHAL_DTLB_SET0_E5_CA_RESET 0x02 -#define XCHAL_DTLB_SET0_E6_CA_RESET 0x02 -#define XCHAL_DTLB_SET0_E7_CA_RESET 0x02 - - - - -#endif /*XTENSA_CONFIG_CORE_MATMAP_H*/ - -#else - -#error "xcc should not use this header" - -#endif /* __XCC__ */ diff --git a/src/platform/apollolake/include/arch/xtensa/config/defs.h b/src/platform/apollolake/include/arch/xtensa/config/defs.h deleted file mode 100644 index d93272ae05a3..000000000000 --- a/src/platform/apollolake/include/arch/xtensa/config/defs.h +++ /dev/null @@ -1,46 +0,0 @@ -/* Definitions for Xtensa instructions, types, and protos. */ - -/* Copyright (c) 2003-2004 Tensilica Inc. - - Permission is hereby granted, free of charge, to any person obtaining - a copy of this software and associated documentation files (the - "Software"), to deal in the Software without restriction, including - without limitation the rights to use, copy, modify, merge, publish, - distribute, sublicense, and/or sell copies of the Software, and to - permit persons to whom the Software is furnished to do so, subject to - the following conditions: - - The above copyright notice and this permission notice shall be included - in all copies or substantial portions of the Software. - - THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. - IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY - CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, - TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE - SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ - -/* NOTE: This file exists only for backward compatibility with T1050 - and earlier Xtensa releases. It includes only a subset of the - available header files. */ - -#if !defined __XCC__ - -#ifndef _XTENSA_BASE_HEADER -#define _XTENSA_BASE_HEADER - -#ifdef __XTENSA__ - -#include -#include -#include - -#endif /* __XTENSA__ */ -#endif /* !_XTENSA_BASE_HEADER */ - -#else - -#error "xcc should not use this header" - -#endif /* __XCC__ */ diff --git a/src/platform/apollolake/include/arch/xtensa/config/specreg.h b/src/platform/apollolake/include/arch/xtensa/config/specreg.h deleted file mode 100644 index 36fafab35555..000000000000 --- a/src/platform/apollolake/include/arch/xtensa/config/specreg.h +++ /dev/null @@ -1,114 +0,0 @@ -/* - * Xtensa Special Register symbolic names - */ - -/* $Id: //depot/rel/Foxhill/dot.8/Xtensa/SWConfig/hal/specreg.h.tpp#1 $ */ - -/* Copyright (c) 1998-2002 Tensilica Inc. - - Permission is hereby granted, free of charge, to any person obtaining - a copy of this software and associated documentation files (the - "Software"), to deal in the Software without restriction, including - without limitation the rights to use, copy, modify, merge, publish, - distribute, sublicense, and/or sell copies of the Software, and to - permit persons to whom the Software is furnished to do so, subject to - the following conditions: - - The above copyright notice and this permission notice shall be included - in all copies or substantial portions of the Software. - - THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. - IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY - CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, - TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE - SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ - -#if !defined __XCC__ - -#ifndef XTENSA_SPECREG_H -#define XTENSA_SPECREG_H - -/* Include these special register bitfield definitions, for historical reasons: */ -#include - - -/* Special registers: */ -#define LBEG 0 -#define LEND 1 -#define LCOUNT 2 -#define SAR 3 -#define BR 4 -#define SCOMPARE1 12 -#define PREFCTL 40 -#define WINDOWBASE 72 -#define WINDOWSTART 73 -#define IBREAKENABLE 96 -#define ATOMCTL 99 -#define DDR 104 -#define MEPC 106 -#define MEPS 107 -#define MESAVE 108 -#define MESR 109 -#define MECR 110 -#define MEVADDR 111 -#define IBREAKA_0 128 -#define IBREAKA_1 129 -#define DBREAKA_0 144 -#define DBREAKA_1 145 -#define DBREAKC_0 160 -#define DBREAKC_1 161 -#define EPC_1 177 -#define EPC_2 178 -#define EPC_3 179 -#define EPC_4 180 -#define EPC_5 181 -#define EPC_6 182 -#define EPC_7 183 -#define DEPC 192 -#define EPS_2 194 -#define EPS_3 195 -#define EPS_4 196 -#define EPS_5 197 -#define EPS_6 198 -#define EPS_7 199 -#define EXCSAVE_1 209 -#define EXCSAVE_2 210 -#define EXCSAVE_3 211 -#define EXCSAVE_4 212 -#define EXCSAVE_5 213 -#define EXCSAVE_6 214 -#define EXCSAVE_7 215 -#define CPENABLE 224 -#define INTERRUPT 226 -#define INTENABLE 228 -#define PS 230 -#define VECBASE 231 -#define EXCCAUSE 232 -#define DEBUGCAUSE 233 -#define CCOUNT 234 -#define PRID 235 -#define ICOUNT 236 -#define ICOUNTLEVEL 237 -#define EXCVADDR 238 -#define CCOMPARE_0 240 -#define CCOMPARE_1 241 -#define CCOMPARE_2 242 - -/* Special cases (bases of special register series): */ -#define IBREAKA 128 -#define DBREAKA 144 -#define DBREAKC 160 -#define EPC 176 -#define EPS 192 -#define EXCSAVE 208 -#define CCOMPARE 240 - -#endif /* XTENSA_SPECREG_H */ - -#else - -#error "xcc should not use this header" - -#endif /* __XCC__ */ diff --git a/src/platform/apollolake/include/arch/xtensa/config/system.h b/src/platform/apollolake/include/arch/xtensa/config/system.h deleted file mode 100644 index 0e434954c920..000000000000 --- a/src/platform/apollolake/include/arch/xtensa/config/system.h +++ /dev/null @@ -1,285 +0,0 @@ -/* - * xtensa/config/system.h -- HAL definitions that are dependent on SYSTEM configuration - * - * NOTE: The location and contents of this file are highly subject to change. - * - * Source for configuration-independent binaries (which link in a - * configuration-specific HAL library) must NEVER include this file. - * The HAL itself has historically included this file in some instances, - * but this is not appropriate either, because the HAL is meant to be - * core-specific but system independent. - */ - -/* Copyright (c) 2000-2010 Tensilica Inc. - - Permission is hereby granted, free of charge, to any person obtaining - a copy of this software and associated documentation files (the - "Software"), to deal in the Software without restriction, including - without limitation the rights to use, copy, modify, merge, publish, - distribute, sublicense, and/or sell copies of the Software, and to - permit persons to whom the Software is furnished to do so, subject to - the following conditions: - - The above copyright notice and this permission notice shall be included - in all copies or substantial portions of the Software. - - THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. - IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY - CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, - TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE - SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ - -#if !defined __XCC__ - -#ifndef XTENSA_CONFIG_SYSTEM_H -#define XTENSA_CONFIG_SYSTEM_H - -/*#include */ - - - -/*---------------------------------------------------------------------- - CONFIGURED SOFTWARE OPTIONS - ----------------------------------------------------------------------*/ - -#define XSHAL_USE_ABSOLUTE_LITERALS 0 /* (sw-only option, whether software uses absolute literals) */ -#define XSHAL_HAVE_TEXT_SECTION_LITERALS 1 /* Set if there is some memory that allows both code and literals. */ - -#define XSHAL_ABI XTHAL_ABI_WINDOWED /* (sw-only option, selected ABI) */ -/* The above maps to one of the following constants: */ -#define XTHAL_ABI_WINDOWED 0 -#define XTHAL_ABI_CALL0 1 -/* Alternatives: */ -/*#define XSHAL_WINDOWED_ABI 1*/ /* set if windowed ABI selected */ -/*#define XSHAL_CALL0_ABI 0*/ /* set if call0 ABI selected */ - -#define XSHAL_CLIB XTHAL_CLIB_NEWLIB /* (sw-only option, selected C library) */ -/* The above maps to one of the following constants: */ -#define XTHAL_CLIB_NEWLIB 0 -#define XTHAL_CLIB_UCLIBC 1 -#define XTHAL_CLIB_XCLIB 2 -/* Alternatives: */ -/*#define XSHAL_NEWLIB 1*/ /* set if newlib C library selected */ -/*#define XSHAL_UCLIBC 0*/ /* set if uCLibC C library selected */ -/*#define XSHAL_XCLIB 0*/ /* set if Xtensa C library selected */ - -#define XSHAL_USE_FLOATING_POINT 1 - -#define XSHAL_FLOATING_POINT_ABI 0 - -/* SW workarounds enabled for HW errata: */ - -/* SW options for functional safety: */ -#define XSHAL_FUNC_SAFETY_ENABLED 0 - -/*---------------------------------------------------------------------- - DEVICE ADDRESSES - ----------------------------------------------------------------------*/ - -/* - * Strange place to find these, but the configuration GUI - * allows moving these around to account for various core - * configurations. Specific boards (and their BSP software) - * will have specific meanings for these components. - */ - -/* I/O Block areas: */ -#define XSHAL_IOBLOCK_CACHED_VADDR 0x70000000 -#define XSHAL_IOBLOCK_CACHED_PADDR 0x70000000 -#define XSHAL_IOBLOCK_CACHED_SIZE 0x0E000000 - -#define XSHAL_IOBLOCK_BYPASS_VADDR 0x50000000 -#define XSHAL_IOBLOCK_BYPASS_PADDR 0x50000000 -#define XSHAL_IOBLOCK_BYPASS_SIZE 0x0E000000 - -/* System ROM: */ -#define XSHAL_ROM_VADDR 0xBEFE0000 -#define XSHAL_ROM_PADDR 0xBEFE0000 -#define XSHAL_ROM_SIZE 0x00020000 -/* Largest available area (free of vectors): */ -#define XSHAL_ROM_AVAIL_VADDR 0xBEFE0BC0 -#define XSHAL_ROM_AVAIL_VSIZE 0x0001F440 - -/* System RAM: */ -#define XSHAL_RAM_VADDR 0x80000000 -#define XSHAL_RAM_PADDR 0x80000000 -#define XSHAL_RAM_VSIZE 0x3EFE0000 -#define XSHAL_RAM_PSIZE 0x3EFE0000 -#define XSHAL_RAM_SIZE XSHAL_RAM_PSIZE -/* Largest available area (free of vectors): */ -#define XSHAL_RAM_AVAIL_VADDR 0x80000000 -#define XSHAL_RAM_AVAIL_VSIZE 0x3EFE0000 - -/* - * Shadow system RAM (same device as system RAM, at different address). - * (Emulation boards need this for the SONIC Ethernet driver - * when data caches are configured for writeback mode.) - * NOTE: on full MMU configs, this points to the BYPASS virtual address - * of system RAM, ie. is the same as XSHAL_RAM_* except that virtual - * addresses are viewed through the BYPASS static map rather than - * the CACHED static map. - */ -#define XSHAL_RAM_BYPASS_VADDR 0x20000000 -#define XSHAL_RAM_BYPASS_PADDR 0x20000000 -#define XSHAL_RAM_BYPASS_PSIZE 0x20000000 - -/* Alternate system RAM (different device than system RAM): */ -/*#define XSHAL_ALTRAM_[VP]ADDR ...not configured...*/ -/*#define XSHAL_ALTRAM_SIZE ...not configured...*/ - -/* Some available location in which to place devices in a simulation (eg. XTMP): */ -#define XSHAL_SIMIO_CACHED_VADDR 0xC0000000 -#define XSHAL_SIMIO_BYPASS_VADDR 0xC0000000 -#define XSHAL_SIMIO_PADDR 0xC0000000 -#define XSHAL_SIMIO_SIZE 0x20000000 - - -/*---------------------------------------------------------------------- - * For use by reference testbench exit and diagnostic routines. - */ -#define XSHAL_MAGIC_EXIT 0xe0000000 - -/*---------------------------------------------------------------------- - * DEVICE-ADDRESS DEPENDENT... - * - * Values written to CACHEATTR special register (or its equivalent) - * to enable and disable caches in various modes. - *----------------------------------------------------------------------*/ - -/*---------------------------------------------------------------------- - BACKWARD COMPATIBILITY ... - ----------------------------------------------------------------------*/ - -/* - * NOTE: the following two macros are DEPRECATED. Use the latter - * board-specific macros instead, which are specially tuned for the - * particular target environments' memory maps. - */ -#define XSHAL_CACHEATTR_BYPASS XSHAL_XT2000_CACHEATTR_BYPASS /* disable caches in bypass mode */ -#define XSHAL_CACHEATTR_DEFAULT XSHAL_XT2000_CACHEATTR_DEFAULT /* default setting to enable caches (no writeback!) */ - -/*---------------------------------------------------------------------- - GENERIC - ----------------------------------------------------------------------*/ - -/* For the following, a 512MB region is used if it contains a system (PIF) RAM, - * system (PIF) ROM, local memory, or XLMI. */ - -/* These set any unused 512MB region to cache-BYPASS attribute: */ -#define XSHAL_ALLVALID_CACHEATTR_WRITEBACK 0x22442222 /* enable caches in write-back mode */ -#define XSHAL_ALLVALID_CACHEATTR_WRITEALLOC 0x22112222 /* enable caches in write-allocate mode */ -#define XSHAL_ALLVALID_CACHEATTR_WRITETHRU 0x22112222 /* enable caches in write-through mode */ -#define XSHAL_ALLVALID_CACHEATTR_BYPASS 0x22222222 /* disable caches in bypass mode */ -#define XSHAL_ALLVALID_CACHEATTR_DEFAULT XSHAL_ALLVALID_CACHEATTR_WRITEBACK /* default setting to enable caches */ - -/* These set any unused 512MB region to ILLEGAL attribute: */ -#define XSHAL_STRICT_CACHEATTR_WRITEBACK 0xFF44FFFF /* enable caches in write-back mode */ -#define XSHAL_STRICT_CACHEATTR_WRITEALLOC 0xFF11FFFF /* enable caches in write-allocate mode */ -#define XSHAL_STRICT_CACHEATTR_WRITETHRU 0xFF11FFFF /* enable caches in write-through mode */ -#define XSHAL_STRICT_CACHEATTR_BYPASS 0xFF22FFFF /* disable caches in bypass mode */ -#define XSHAL_STRICT_CACHEATTR_DEFAULT XSHAL_STRICT_CACHEATTR_WRITEBACK /* default setting to enable caches */ - -/* These set the first 512MB, if unused, to ILLEGAL attribute to help catch - * NULL-pointer dereference bugs; all other unused 512MB regions are set - * to cache-BYPASS attribute: */ -#define XSHAL_TRAPNULL_CACHEATTR_WRITEBACK 0x2244222F /* enable caches in write-back mode */ -#define XSHAL_TRAPNULL_CACHEATTR_WRITEALLOC 0x2211222F /* enable caches in write-allocate mode */ -#define XSHAL_TRAPNULL_CACHEATTR_WRITETHRU 0x2211222F /* enable caches in write-through mode */ -#define XSHAL_TRAPNULL_CACHEATTR_BYPASS 0x2222222F /* disable caches in bypass mode */ -#define XSHAL_TRAPNULL_CACHEATTR_DEFAULT XSHAL_TRAPNULL_CACHEATTR_WRITEBACK /* default setting to enable caches */ - -/*---------------------------------------------------------------------- - ISS (Instruction Set Simulator) SPECIFIC ... - ----------------------------------------------------------------------*/ - -/* For now, ISS defaults to the TRAPNULL settings: */ -#define XSHAL_ISS_CACHEATTR_WRITEBACK XSHAL_TRAPNULL_CACHEATTR_WRITEBACK -#define XSHAL_ISS_CACHEATTR_WRITEALLOC XSHAL_TRAPNULL_CACHEATTR_WRITEALLOC -#define XSHAL_ISS_CACHEATTR_WRITETHRU XSHAL_TRAPNULL_CACHEATTR_WRITETHRU -#define XSHAL_ISS_CACHEATTR_BYPASS XSHAL_TRAPNULL_CACHEATTR_BYPASS -#define XSHAL_ISS_CACHEATTR_DEFAULT XSHAL_TRAPNULL_CACHEATTR_WRITEBACK - -#define XSHAL_ISS_PIPE_REGIONS 0 -#define XSHAL_ISS_SDRAM_REGIONS 0 - - -/*---------------------------------------------------------------------- - XT2000 BOARD SPECIFIC ... - ----------------------------------------------------------------------*/ - -/* For the following, a 512MB region is used if it contains any system RAM, - * system ROM, local memory, XLMI, or other XT2000 board device or memory. - * Regions containing devices are forced to cache-BYPASS mode regardless - * of whether the macro is _WRITEBACK vs. _BYPASS etc. */ - -/* These set any 512MB region unused on the XT2000 to ILLEGAL attribute: */ -#define XSHAL_XT2000_CACHEATTR_WRITEBACK 0xFF44422F /* enable caches in write-back mode */ -#define XSHAL_XT2000_CACHEATTR_WRITEALLOC 0xFF11122F /* enable caches in write-allocate mode */ -#define XSHAL_XT2000_CACHEATTR_WRITETHRU 0xFF11122F /* enable caches in write-through mode */ -#define XSHAL_XT2000_CACHEATTR_BYPASS 0xFF22222F /* disable caches in bypass mode */ -#define XSHAL_XT2000_CACHEATTR_DEFAULT XSHAL_XT2000_CACHEATTR_WRITEBACK /* default setting to enable caches */ - -#define XSHAL_XT2000_PIPE_REGIONS 0x00000000 /* BusInt pipeline regions */ -#define XSHAL_XT2000_SDRAM_REGIONS 0x00000104 /* BusInt SDRAM regions */ - - -/*---------------------------------------------------------------------- - VECTOR INFO AND SIZES - ----------------------------------------------------------------------*/ - -#define XSHAL_VECTORS_PACKED 0 -#define XSHAL_STATIC_VECTOR_SELECT 0 -#define XSHAL_RESET_VECTOR_VADDR 0xBEFE0000 -#define XSHAL_RESET_VECTOR_PADDR 0xBEFE0000 -#define XSHAL_MEMERROR_VECTOR_VADDR 0xBEFE0400 -#define XSHAL_MEMERROR_VECTOR_PADDR 0xBEFE0400 - -/* - * Sizes allocated to vectors by the system (memory map) configuration. - * These sizes are constrained by core configuration (eg. one vector's - * code cannot overflow into another vector) but are dependent on the - * system or board (or LSP) memory map configuration. - * - * Whether or not each vector happens to be in a system ROM is also - * a system configuration matter, sometimes useful, included here also: - */ -#define XSHAL_RESET_VECTOR_SIZE 0x00000300 -#define XSHAL_RESET_VECTOR_ISROM 1 -#define XSHAL_USER_VECTOR_SIZE 0x00000038 -#define XSHAL_USER_VECTOR_ISROM 1 -#define XSHAL_PROGRAMEXC_VECTOR_SIZE XSHAL_USER_VECTOR_SIZE /* for backward compatibility */ -#define XSHAL_USEREXC_VECTOR_SIZE XSHAL_USER_VECTOR_SIZE /* for backward compatibility */ -#define XSHAL_KERNEL_VECTOR_SIZE 0x00000038 -#define XSHAL_KERNEL_VECTOR_ISROM 1 -#define XSHAL_STACKEDEXC_VECTOR_SIZE XSHAL_KERNEL_VECTOR_SIZE /* for backward compatibility */ -#define XSHAL_KERNELEXC_VECTOR_SIZE XSHAL_KERNEL_VECTOR_SIZE /* for backward compatibility */ -#define XSHAL_DOUBLEEXC_VECTOR_SIZE 0x00000040 -#define XSHAL_DOUBLEEXC_VECTOR_ISROM 1 -#define XSHAL_WINDOW_VECTORS_SIZE 0x00000178 -#define XSHAL_WINDOW_VECTORS_ISROM 1 -#define XSHAL_INTLEVEL2_VECTOR_SIZE 0x00000038 -#define XSHAL_INTLEVEL2_VECTOR_ISROM 1 -#define XSHAL_INTLEVEL3_VECTOR_SIZE 0x00000038 -#define XSHAL_INTLEVEL3_VECTOR_ISROM 1 -#define XSHAL_INTLEVEL4_VECTOR_SIZE 0x00000038 -#define XSHAL_INTLEVEL4_VECTOR_ISROM 1 -#define XSHAL_INTLEVEL5_VECTOR_SIZE 0x00000038 -#define XSHAL_INTLEVEL5_VECTOR_ISROM 1 -#define XSHAL_INTLEVEL6_VECTOR_SIZE 0x00000038 -#define XSHAL_INTLEVEL6_VECTOR_ISROM 1 -#define XSHAL_DEBUG_VECTOR_SIZE XSHAL_INTLEVEL6_VECTOR_SIZE -#define XSHAL_DEBUG_VECTOR_ISROM XSHAL_INTLEVEL6_VECTOR_ISROM -#define XSHAL_NMI_VECTOR_SIZE 0x00000038 -#define XSHAL_NMI_VECTOR_ISROM 1 -#define XSHAL_INTLEVEL7_VECTOR_SIZE XSHAL_NMI_VECTOR_SIZE - - -#endif /*XTENSA_CONFIG_SYSTEM_H*/ - -#else - -#error "xcc should not use this header" - -#endif /* __XCC__ */ diff --git a/src/platform/apollolake/include/arch/xtensa/config/tie-asm.h b/src/platform/apollolake/include/arch/xtensa/config/tie-asm.h deleted file mode 100644 index 0d1279a805c3..000000000000 --- a/src/platform/apollolake/include/arch/xtensa/config/tie-asm.h +++ /dev/null @@ -1,293 +0,0 @@ -/* - * tie-asm.h -- compile-time HAL assembler definitions dependent on CORE & TIE - * - * NOTE: This header file is not meant to be included directly. - */ - -/* This header file contains assembly-language definitions (assembly - macros, etc.) for this specific Xtensa processor's TIE extensions - and options. It is customized to this Xtensa processor configuration. - - Copyright (c) 1999-2018 Cadence Design Systems Inc. - - Permission is hereby granted, free of charge, to any person obtaining - a copy of this software and associated documentation files (the - "Software"), to deal in the Software without restriction, including - without limitation the rights to use, copy, modify, merge, publish, - distribute, sublicense, and/or sell copies of the Software, and to - permit persons to whom the Software is furnished to do so, subject to - the following conditions: - - The above copyright notice and this permission notice shall be included - in all copies or substantial portions of the Software. - - THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. - IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY - CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, - TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE - SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ - -#if !defined __XCC__ - -#ifndef _XTENSA_CORE_TIE_ASM_H -#define _XTENSA_CORE_TIE_ASM_H - -/* Selection parameter values for save-area save/restore macros: */ -/* Option vs. TIE: */ -#define XTHAL_SAS_TIE 0x0001 /* custom extension or coprocessor */ -#define XTHAL_SAS_OPT 0x0002 /* optional (and not a coprocessor) */ -#define XTHAL_SAS_ANYOT 0x0003 /* both of the above */ -/* Whether used automatically by compiler: */ -#define XTHAL_SAS_NOCC 0x0004 /* not used by compiler w/o special opts/code */ -#define XTHAL_SAS_CC 0x0008 /* used by compiler without special opts/code */ -#define XTHAL_SAS_ANYCC 0x000C /* both of the above */ -/* ABI handling across function calls: */ -#define XTHAL_SAS_CALR 0x0010 /* caller-saved */ -#define XTHAL_SAS_CALE 0x0020 /* callee-saved */ -#define XTHAL_SAS_GLOB 0x0040 /* global across function calls (in thread) */ -#define XTHAL_SAS_ANYABI 0x0070 /* all of the above three */ -/* Misc */ -#define XTHAL_SAS_ALL 0xFFFF /* include all default NCP contents */ -#define XTHAL_SAS3(optie,ccuse,abi) ( ((optie) & XTHAL_SAS_ANYOT) \ - | ((ccuse) & XTHAL_SAS_ANYCC) \ - | ((abi) & XTHAL_SAS_ANYABI) ) - - - /* - * Macro to store all non-coprocessor (extra) custom TIE and optional state - * (not including zero-overhead loop registers). - * Required parameters: - * ptr Save area pointer address register (clobbered) - * (register must contain a 4 byte aligned address). - * at1..at4 Four temporary address registers (first XCHAL_NCP_NUM_ATMPS - * registers are clobbered, the remaining are unused). - * Optional parameters: - * continue If macro invoked as part of a larger store sequence, set to 1 - * if this is not the first in the sequence. Defaults to 0. - * ofs Offset from start of larger sequence (from value of first ptr - * in sequence) at which to store. Defaults to next available space - * (or 0 if is 0). - * select Select what category(ies) of registers to store, as a bitmask - * (see XTHAL_SAS_xxx constants). Defaults to all registers. - * alloc Select what category(ies) of registers to allocate; if any - * category is selected here that is not in , space for - * the corresponding registers is skipped without doing any load. - */ - .macro xchal_ncp_load ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0 - xchal_sa_start \continue, \ofs - // Optional global registers used by default by the compiler: - .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~(\select) - xchal_sa_align \ptr, 0, 1016, 4, 4 - l32i \at1, \ptr, .Lxchal_ofs_+0 - wur.THREADPTR \at1 // threadptr option - .set .Lxchal_ofs_, .Lxchal_ofs_ + 4 - .elseif ((XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~(\alloc)) == 0 - xchal_sa_align \ptr, 0, 1016, 4, 4 - .set .Lxchal_ofs_, .Lxchal_ofs_ + 4 - .endif - // Optional caller-saved registers not used by default by the compiler: - .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select) - xchal_sa_align \ptr, 0, 1012, 4, 4 - l32i \at1, \ptr, .Lxchal_ofs_+0 - wsr.BR \at1 // boolean option - l32i \at1, \ptr, .Lxchal_ofs_+4 - wsr.SCOMPARE1 \at1 // conditional store option - .set .Lxchal_ofs_, .Lxchal_ofs_ + 8 - .elseif ((XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0 - xchal_sa_align \ptr, 0, 1012, 4, 4 - .set .Lxchal_ofs_, .Lxchal_ofs_ + 8 - .endif - .endm // xchal_ncp_load - - -#define XCHAL_NCP_NUM_ATMPS 1 - - /* - * Macro to store the state of TIE coprocessor AudioEngineLX. - * Required parameters: - * ptr Save area pointer address register (clobbered) - * (register must contain a 8 byte aligned address). - * at1..at4 Four temporary address registers (first XCHAL_CP1_NUM_ATMPS - * registers are clobbered, the remaining are unused). - * Optional parameters are the same as for xchal_ncp_store. - */ -#define xchal_cp_AudioEngineLX_store xchal_cp1_store - .macro xchal_cp1_store ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0 - xchal_sa_start \continue, \ofs - // Custom caller-saved registers not used by default by the compiler: - .ifeq (XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select) - xchal_sa_align \ptr, 0, 0, 8, 8 - rur.AE_OVF_SAR \at1 // ureg 240 - s32i \at1, \ptr, .Lxchal_ofs_+0 - rur.AE_BITHEAD \at1 // ureg 241 - s32i \at1, \ptr, .Lxchal_ofs_+4 - rur.AE_TS_FTS_BU_BP \at1 // ureg 242 - s32i \at1, \ptr, .Lxchal_ofs_+8 - rur.AE_CW_SD_NO \at1 // ureg 243 - s32i \at1, \ptr, .Lxchal_ofs_+12 - rur.AE_CBEGIN0 \at1 // ureg 246 - s32i \at1, \ptr, .Lxchal_ofs_+16 - rur.AE_CEND0 \at1 // ureg 247 - s32i \at1, \ptr, .Lxchal_ofs_+20 - ae_s64.i aed0, \ptr, .Lxchal_ofs_+24 - ae_s64.i aed1, \ptr, .Lxchal_ofs_+32 - ae_s64.i aed2, \ptr, .Lxchal_ofs_+40 - ae_s64.i aed3, \ptr, .Lxchal_ofs_+48 - ae_s64.i aed4, \ptr, .Lxchal_ofs_+56 - addi \ptr, \ptr, 64 - ae_s64.i aed5, \ptr, .Lxchal_ofs_+0 - ae_s64.i aed6, \ptr, .Lxchal_ofs_+8 - ae_s64.i aed7, \ptr, .Lxchal_ofs_+16 - ae_s64.i aed8, \ptr, .Lxchal_ofs_+24 - ae_s64.i aed9, \ptr, .Lxchal_ofs_+32 - ae_s64.i aed10, \ptr, .Lxchal_ofs_+40 - ae_s64.i aed11, \ptr, .Lxchal_ofs_+48 - ae_s64.i aed12, \ptr, .Lxchal_ofs_+56 - addi \ptr, \ptr, 64 - ae_s64.i aed13, \ptr, .Lxchal_ofs_+0 - ae_s64.i aed14, \ptr, .Lxchal_ofs_+8 - ae_s64.i aed15, \ptr, .Lxchal_ofs_+16 - ae_salign64.i u0, \ptr, .Lxchal_ofs_+24 - ae_salign64.i u1, \ptr, .Lxchal_ofs_+32 - ae_salign64.i u2, \ptr, .Lxchal_ofs_+40 - ae_salign64.i u3, \ptr, .Lxchal_ofs_+48 - .set .Lxchal_pofs_, .Lxchal_pofs_ + 128 - .set .Lxchal_ofs_, .Lxchal_ofs_ + 56 - .elseif ((XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0 - xchal_sa_align \ptr, 0, 0, 8, 8 - .set .Lxchal_ofs_, .Lxchal_ofs_ + 184 - .endif - .endm // xchal_cp1_store - - /* - * Macro to load the state of TIE coprocessor AudioEngineLX. - * Required parameters: - * ptr Save area pointer address register (clobbered) - * (register must contain a 8 byte aligned address). - * at1..at4 Four temporary address registers (first XCHAL_CP1_NUM_ATMPS - * registers are clobbered, the remaining are unused). - * Optional parameters are the same as for xchal_ncp_load. - */ -#define xchal_cp_AudioEngineLX_load xchal_cp1_load - .macro xchal_cp1_load ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0 - xchal_sa_start \continue, \ofs - // Custom caller-saved registers not used by default by the compiler: - .ifeq (XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select) - xchal_sa_align \ptr, 0, 0, 8, 8 - l32i \at1, \ptr, .Lxchal_ofs_+0 - wur.AE_OVF_SAR \at1 // ureg 240 - l32i \at1, \ptr, .Lxchal_ofs_+4 - wur.AE_BITHEAD \at1 // ureg 241 - l32i \at1, \ptr, .Lxchal_ofs_+8 - wur.AE_TS_FTS_BU_BP \at1 // ureg 242 - l32i \at1, \ptr, .Lxchal_ofs_+12 - wur.AE_CW_SD_NO \at1 // ureg 243 - l32i \at1, \ptr, .Lxchal_ofs_+16 - wur.AE_CBEGIN0 \at1 // ureg 246 - l32i \at1, \ptr, .Lxchal_ofs_+20 - wur.AE_CEND0 \at1 // ureg 247 - ae_l64.i aed0, \ptr, .Lxchal_ofs_+24 - ae_l64.i aed1, \ptr, .Lxchal_ofs_+32 - ae_l64.i aed2, \ptr, .Lxchal_ofs_+40 - ae_l64.i aed3, \ptr, .Lxchal_ofs_+48 - ae_l64.i aed4, \ptr, .Lxchal_ofs_+56 - addi \ptr, \ptr, 64 - ae_l64.i aed5, \ptr, .Lxchal_ofs_+0 - ae_l64.i aed6, \ptr, .Lxchal_ofs_+8 - ae_l64.i aed7, \ptr, .Lxchal_ofs_+16 - ae_l64.i aed8, \ptr, .Lxchal_ofs_+24 - ae_l64.i aed9, \ptr, .Lxchal_ofs_+32 - ae_l64.i aed10, \ptr, .Lxchal_ofs_+40 - ae_l64.i aed11, \ptr, .Lxchal_ofs_+48 - ae_l64.i aed12, \ptr, .Lxchal_ofs_+56 - addi \ptr, \ptr, 64 - ae_l64.i aed13, \ptr, .Lxchal_ofs_+0 - ae_l64.i aed14, \ptr, .Lxchal_ofs_+8 - ae_l64.i aed15, \ptr, .Lxchal_ofs_+16 - addi \ptr, \ptr, 24 - ae_lalign64.i u0, \ptr, .Lxchal_ofs_+0 - ae_lalign64.i u1, \ptr, .Lxchal_ofs_+8 - ae_lalign64.i u2, \ptr, .Lxchal_ofs_+16 - ae_lalign64.i u3, \ptr, .Lxchal_ofs_+24 - .set .Lxchal_pofs_, .Lxchal_pofs_ + 152 - .set .Lxchal_ofs_, .Lxchal_ofs_ + 32 - .elseif ((XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0 - xchal_sa_align \ptr, 0, 0, 8, 8 - .set .Lxchal_ofs_, .Lxchal_ofs_ + 184 - .endif - .endm // xchal_cp1_load - -#define XCHAL_CP1_NUM_ATMPS 1 -#define XCHAL_SA_NUM_ATMPS 1 - - /* Empty macros for unconfigured coprocessors: */ - .macro xchal_cp0_store p a b c d continue=0 ofs=-1 select=-1 ; .endm - .macro xchal_cp0_load p a b c d continue=0 ofs=-1 select=-1 ; .endm - .macro xchal_cp2_store p a b c d continue=0 ofs=-1 select=-1 ; .endm - .macro xchal_cp2_load p a b c d continue=0 ofs=-1 select=-1 ; .endm - .macro xchal_cp3_store p a b c d continue=0 ofs=-1 select=-1 ; .endm - .macro xchal_cp3_load p a b c d continue=0 ofs=-1 select=-1 ; .endm - .macro xchal_cp4_store p a b c d continue=0 ofs=-1 select=-1 ; .endm - .macro xchal_cp4_load p a b c d continue=0 ofs=-1 select=-1 ; .endm - .macro xchal_cp5_store p a b c d continue=0 ofs=-1 select=-1 ; .endm - .macro xchal_cp5_load p a b c d continue=0 ofs=-1 select=-1 ; .endm - .macro xchal_cp6_store p a b c d continue=0 ofs=-1 select=-1 ; .endm - .macro xchal_cp6_load p a b c d continue=0 ofs=-1 select=-1 ; .endm - .macro xchal_cp7_store p a b c d continue=0 ofs=-1 select=-1 ; .endm - .macro xchal_cp7_load p a b c d continue=0 ofs=-1 select=-1 ; .endm - -#endif /*_XTENSA_CORE_TIE_ASM_H*/ - -#else - -#error "xcc should not use this header" - -#endif /* __XCC__ */ diff --git a/src/platform/apollolake/include/arch/xtensa/config/tie.h b/src/platform/apollolake/include/arch/xtensa/config/tie.h deleted file mode 100644 index c0ca1a44a71a..000000000000 --- a/src/platform/apollolake/include/arch/xtensa/config/tie.h +++ /dev/null @@ -1,188 +0,0 @@ -/* - * tie.h -- compile-time HAL definitions dependent on CORE & TIE configuration - * - * NOTE: This header file is not meant to be included directly. - */ - -/* This header file describes this specific Xtensa processor's TIE extensions - that extend basic Xtensa core functionality. It is customized to this - Xtensa processor configuration. - - Copyright (c) 1999-2018 Cadence Design Systems Inc. - - Permission is hereby granted, free of charge, to any person obtaining - a copy of this software and associated documentation files (the - "Software"), to deal in the Software without restriction, including - without limitation the rights to use, copy, modify, merge, publish, - distribute, sublicense, and/or sell copies of the Software, and to - permit persons to whom the Software is furnished to do so, subject to - the following conditions: - - The above copyright notice and this permission notice shall be included - in all copies or substantial portions of the Software. - - THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. - IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY - CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, - TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE - SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ - -#if !defined __XCC__ - -#ifndef _XTENSA_CORE_TIE_H -#define _XTENSA_CORE_TIE_H - -#define XCHAL_CP_NUM 1 /* number of coprocessors */ -#define XCHAL_CP_MAX 2 /* max CP ID + 1 (0 if none) */ -#define XCHAL_CP_MASK 0x02 /* bitmask of all CPs by ID */ -#define XCHAL_CP_PORT_MASK 0x00 /* bitmask of only port CPs */ - -/* Basic parameters of each coprocessor: */ -#define XCHAL_CP1_NAME "AudioEngineLX" -#define XCHAL_CP1_IDENT AudioEngineLX -#define XCHAL_CP1_SA_SIZE 184 /* size of state save area */ -#define XCHAL_CP1_SA_ALIGN 8 /* min alignment of save area */ -#define XCHAL_CP_ID_AUDIOENGINELX 1 /* coprocessor ID (0..7) */ - -/* Filler info for unassigned coprocessors, to simplify arrays etc: */ -#define XCHAL_CP0_SA_SIZE 0 -#define XCHAL_CP0_SA_ALIGN 1 -#define XCHAL_CP2_SA_SIZE 0 -#define XCHAL_CP2_SA_ALIGN 1 -#define XCHAL_CP3_SA_SIZE 0 -#define XCHAL_CP3_SA_ALIGN 1 -#define XCHAL_CP4_SA_SIZE 0 -#define XCHAL_CP4_SA_ALIGN 1 -#define XCHAL_CP5_SA_SIZE 0 -#define XCHAL_CP5_SA_ALIGN 1 -#define XCHAL_CP6_SA_SIZE 0 -#define XCHAL_CP6_SA_ALIGN 1 -#define XCHAL_CP7_SA_SIZE 0 -#define XCHAL_CP7_SA_ALIGN 1 - -/* Save area for non-coprocessor optional and custom (TIE) state: */ -#define XCHAL_NCP_SA_SIZE 12 -#define XCHAL_NCP_SA_ALIGN 4 - -/* Total save area for optional and custom state (NCP + CPn): */ -#define XCHAL_TOTAL_SA_SIZE 208 /* with 16-byte align padding */ -#define XCHAL_TOTAL_SA_ALIGN 8 /* actual minimum alignment */ - -/* - * Detailed contents of save areas. - * NOTE: caller must define the XCHAL_SA_REG macro (not defined here) - * before expanding the XCHAL_xxx_SA_LIST() macros. - * - * XCHAL_SA_REG(s,ccused,abikind,kind,opt,name,galign,align,asize, - * dbnum,base,regnum,bitsz,gapsz,reset,x...) - * - * s = passed from XCHAL_*_LIST(s), eg. to select how to expand - * ccused = set if used by compiler without special options or code - * abikind = 0 (caller-saved), 1 (callee-saved), or 2 (thread-global) - * kind = 0 (special reg), 1 (TIE user reg), or 2 (TIE regfile reg) - * opt = 0 (custom TIE extension or coprocessor), or 1 (optional reg) - * name = lowercase reg name (no quotes) - * galign = group byte alignment (power of 2) (galign >= align) - * align = register byte alignment (power of 2) - * asize = allocated size in bytes (asize*8 == bitsz + gapsz + padsz) - * (not including any pad bytes required to galign this or next reg) - * dbnum = unique target number f/debug (see ) - * base = reg shortname w/o index (or sr=special, ur=TIE user reg) - * regnum = reg index in regfile, or special/TIE-user reg number - * bitsz = number of significant bits (regfile width, or ur/sr mask bits) - * gapsz = intervening bits, if bitsz bits not stored contiguously - * (padsz = pad bits at end [TIE regfile] or at msbits [ur,sr] of asize) - * reset = register reset value (or 0 if undefined at reset) - * x = reserved for future use (0 until then) - * - * To filter out certain registers, e.g. to expand only the non-global - * registers used by the compiler, you can do something like this: - * - * #define XCHAL_SA_REG(s,ccused,p...) SELCC##ccused(p) - * #define SELCC0(p...) - * #define SELCC1(abikind,p...) SELAK##abikind(p) - * #define SELAK0(p...) REG(p) - * #define SELAK1(p...) REG(p) - * #define SELAK2(p...) - * #define REG(kind,tie,name,galn,aln,asz,csz,dbnum,base,rnum,bsz,rst,x...) \ - * ...what you want to expand... - */ - -#define XCHAL_NCP_SA_NUM 3 -#define XCHAL_NCP_SA_LIST(s) \ - XCHAL_SA_REG(s,1,2,1,1, threadptr, 4, 4, 4,0x03E7, ur,231, 32,0,0,0) \ - XCHAL_SA_REG(s,0,0,0,1, br, 4, 4, 4,0x0204, sr,4 , 16,0,0,0) \ - XCHAL_SA_REG(s,0,0,0,1, scompare1, 4, 4, 4,0x020C, sr,12 , 32,0,0,0) - -#define XCHAL_CP0_SA_NUM 0 -#define XCHAL_CP0_SA_LIST(s) /* empty */ - -#define XCHAL_CP1_SA_NUM 26 -#define XCHAL_CP1_SA_LIST(s) \ - XCHAL_SA_REG(s,0,0,1,0, ae_ovf_sar, 8, 4, 4,0x03F0, ur,240, 8,0,0,0) \ - XCHAL_SA_REG(s,0,0,1,0, ae_bithead, 4, 4, 4,0x03F1, ur,241, 32,0,0,0) \ - XCHAL_SA_REG(s,0,0,1,0,ae_ts_fts_bu_bp, 4, 4, 4,0x03F2, ur,242, 16,0,0,0) \ - XCHAL_SA_REG(s,0,0,1,0, ae_cw_sd_no, 4, 4, 4,0x03F3, ur,243, 29,0,0,0) \ - XCHAL_SA_REG(s,0,0,1,0, ae_cbegin0, 4, 4, 4,0x03F6, ur,246, 32,0,0,0) \ - XCHAL_SA_REG(s,0,0,1,0, ae_cend0, 4, 4, 4,0x03F7, ur,247, 32,0,0,0) \ - XCHAL_SA_REG(s,0,0,2,0, aed0, 8, 8, 8,0x1000, aed,0 , 64,0,0,0) \ - XCHAL_SA_REG(s,0,0,2,0, aed1, 8, 8, 8,0x1001, aed,1 , 64,0,0,0) \ - XCHAL_SA_REG(s,0,0,2,0, aed2, 8, 8, 8,0x1002, aed,2 , 64,0,0,0) \ - XCHAL_SA_REG(s,0,0,2,0, aed3, 8, 8, 8,0x1003, aed,3 , 64,0,0,0) \ - XCHAL_SA_REG(s,0,0,2,0, aed4, 8, 8, 8,0x1004, aed,4 , 64,0,0,0) \ - XCHAL_SA_REG(s,0,0,2,0, aed5, 8, 8, 8,0x1005, aed,5 , 64,0,0,0) \ - XCHAL_SA_REG(s,0,0,2,0, aed6, 8, 8, 8,0x1006, aed,6 , 64,0,0,0) \ - XCHAL_SA_REG(s,0,0,2,0, aed7, 8, 8, 8,0x1007, aed,7 , 64,0,0,0) \ - XCHAL_SA_REG(s,0,0,2,0, aed8, 8, 8, 8,0x1008, aed,8 , 64,0,0,0) \ - XCHAL_SA_REG(s,0,0,2,0, aed9, 8, 8, 8,0x1009, aed,9 , 64,0,0,0) \ - XCHAL_SA_REG(s,0,0,2,0, aed10, 8, 8, 8,0x100A, aed,10 , 64,0,0,0) \ - XCHAL_SA_REG(s,0,0,2,0, aed11, 8, 8, 8,0x100B, aed,11 , 64,0,0,0) \ - XCHAL_SA_REG(s,0,0,2,0, aed12, 8, 8, 8,0x100C, aed,12 , 64,0,0,0) \ - XCHAL_SA_REG(s,0,0,2,0, aed13, 8, 8, 8,0x100D, aed,13 , 64,0,0,0) \ - XCHAL_SA_REG(s,0,0,2,0, aed14, 8, 8, 8,0x100E, aed,14 , 64,0,0,0) \ - XCHAL_SA_REG(s,0,0,2,0, aed15, 8, 8, 8,0x100F, aed,15 , 64,0,0,0) \ - XCHAL_SA_REG(s,0,0,2,0, u0, 8, 8, 8,0x1010, u,0 , 64,0,0,0) \ - XCHAL_SA_REG(s,0,0,2,0, u1, 8, 8, 8,0x1011, u,1 , 64,0,0,0) \ - XCHAL_SA_REG(s,0,0,2,0, u2, 8, 8, 8,0x1012, u,2 , 64,0,0,0) \ - XCHAL_SA_REG(s,0,0,2,0, u3, 8, 8, 8,0x1013, u,3 , 64,0,0,0) - -#define XCHAL_CP2_SA_NUM 0 -#define XCHAL_CP2_SA_LIST(s) /* empty */ - -#define XCHAL_CP3_SA_NUM 0 -#define XCHAL_CP3_SA_LIST(s) /* empty */ - -#define XCHAL_CP4_SA_NUM 0 -#define XCHAL_CP4_SA_LIST(s) /* empty */ - -#define XCHAL_CP5_SA_NUM 0 -#define XCHAL_CP5_SA_LIST(s) /* empty */ - -#define XCHAL_CP6_SA_NUM 0 -#define XCHAL_CP6_SA_LIST(s) /* empty */ - -#define XCHAL_CP7_SA_NUM 0 -#define XCHAL_CP7_SA_LIST(s) /* empty */ - -/* Byte length of instruction from its first nibble (op0 field), per FLIX. */ -#define XCHAL_OP0_FORMAT_LENGTHS 3,3,3,3,3,3,3,3,2,2,2,2,2,2,8,8 -/* Byte length of instruction from its first byte, per FLIX. */ -#define XCHAL_BYTE0_FORMAT_LENGTHS \ - 3,3,3,3,3,3,3,3,2,2,2,2,2,2,8,8, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,8,8,\ - 3,3,3,3,3,3,3,3,2,2,2,2,2,2,8,8, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,8,8,\ - 3,3,3,3,3,3,3,3,2,2,2,2,2,2,8,8, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,8,8,\ - 3,3,3,3,3,3,3,3,2,2,2,2,2,2,8,8, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,8,8,\ - 3,3,3,3,3,3,3,3,2,2,2,2,2,2,8,8, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,8,8,\ - 3,3,3,3,3,3,3,3,2,2,2,2,2,2,8,8, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,8,8,\ - 3,3,3,3,3,3,3,3,2,2,2,2,2,2,8,8, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,8,8,\ - 3,3,3,3,3,3,3,3,2,2,2,2,2,2,8,8, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,8,8 - -#endif /*_XTENSA_CORE_TIE_H*/ - -#else - -#error "xcc should not use this header" - -#endif /* __XCC__ */ diff --git a/src/platform/apollolake/include/platform/drivers/dw-dma.h b/src/platform/apollolake/include/platform/drivers/dw-dma.h deleted file mode 100644 index 26d781ac8844..000000000000 --- a/src/platform/apollolake/include/platform/drivers/dw-dma.h +++ /dev/null @@ -1,21 +0,0 @@ -/* SPDX-License-Identifier: BSD-3-Clause - * - * Copyright(c) 2019 Intel Corporation. All rights reserved. - * - * Author: Tomasz Lauda - */ - -#ifdef __SOF_DRIVERS_DW_DMA_H__ - -#ifndef __PLATFORM_DRIVERS_DW_DMA_H__ -#define __PLATFORM_DRIVERS_DW_DMA_H__ - -#include - -#endif /* __PLATFORM_DW_DMA_H__ */ - -#else - -#error "This file shouldn't be included from outside of sof/drivers/dw-dma.h" - -#endif /* __PLATFORM_DRIVERS_DW_DMA_H__ */ diff --git a/src/platform/apollolake/include/platform/drivers/idc.h b/src/platform/apollolake/include/platform/drivers/idc.h deleted file mode 100644 index 49d7e60f2cc4..000000000000 --- a/src/platform/apollolake/include/platform/drivers/idc.h +++ /dev/null @@ -1,21 +0,0 @@ -/* SPDX-License-Identifier: BSD-3-Clause - * - * Copyright(c) 2018 Intel Corporation. All rights reserved. - * - * Author: Tomasz Lauda - */ - -#if defined(__XTOS_RTOS_IDC_H__) || defined(__ZEPHYR_RTOS_IDC_H__) - -#ifndef __PLATFORM_DRIVERS_IDC_H__ -#define __PLATFORM_DRIVERS_IDC_H__ - -#include - -#endif /* __PLATFORM_DRIVERS_IDC_H__ */ - -#else - -#error "This file shouldn't be included from outside of Zephyr/XTOS's rtos/idc.h" - -#endif diff --git a/src/platform/apollolake/include/platform/drivers/interrupt.h b/src/platform/apollolake/include/platform/drivers/interrupt.h deleted file mode 100644 index 74a1a33dacdd..000000000000 --- a/src/platform/apollolake/include/platform/drivers/interrupt.h +++ /dev/null @@ -1,152 +0,0 @@ -/* SPDX-License-Identifier: BSD-3-Clause - * - * Copyright(c) 2016 Intel Corporation. All rights reserved. - * - * Author: Liam Girdwood - * Keyon Jie - */ - -#ifdef __SOF_DRIVERS_INTERRUPT_H__ - -#ifndef __PLATFORM_DRIVERS_INTERRUPT_H__ -#define __PLATFORM_DRIVERS_INTERRUPT_H__ - -#include -#include - -#define PLATFORM_IRQ_HW_NUM XCHAL_NUM_INTERRUPTS -#define PLATFORM_IRQ_FIRST_CHILD PLATFORM_IRQ_HW_NUM -#define PLATFORM_IRQ_CHILDREN 32 - -/* IRQ numbers - wrt Tensilica DSP */ -#if CONFIG_XT_INTERRUPT_LEVEL_1 - -#define IRQ_NUM_SOFTWARE0 0 /* level 1 */ -#define IRQ_NUM_TIMER1 1 /* level 1 */ -#define IRQ_NUM_EXT_LEVEL1 2 /* level 1 */ -#define IRQ_NUM_SOFTWARE1 3 /* level 1 */ - -#define IRQ_MASK_SOFTWARE0 BIT(IRQ_NUM_SOFTWARE0) -#define IRQ_MASK_TIMER1 BIT(IRQ_NUM_TIMER1) -#define IRQ_MASK_EXT_LEVEL1 BIT(IRQ_NUM_EXT_LEVEL1) -#define IRQ_MASK_SOFTWARE1 BIT(IRQ_NUM_SOFTWARE1) - -#endif - -#if CONFIG_XT_INTERRUPT_LEVEL_2 - -#define IRQ_NUM_SOFTWARE2 4 /* level 2 */ -#define IRQ_NUM_TIMER2 5 /* level 2 */ -#define IRQ_NUM_EXT_LEVEL2 6 /* level 2 */ -#define IRQ_NUM_SOFTWARE3 7 /* level 2 */ - -/* IRQ Level 2 bits */ -#define IRQ_BIT_LVL2_HP_GP_DMA0(x) (x + 24) -#define IRQ_BIT_LVL2_WALL_CLK1 23 -#define IRQ_BIT_LVL2_WALL_CLK0 22 -#define IRQ_BIT_LVL2_L2_MEMERR 21 -#define IRQ_BIT_LVL2_SHA256 16 -#define IRQ_BIT_LVL2_L2_CACHE 15 -#define IRQ_BIT_LVL2_IDC 8 -#define IRQ_BIT_LVL2_HOST_IPC 7 -#define IRQ_BIT_LVL2_CSME_IPC 6 -#define IRQ_BIT_LVL2_PMC_IPC 5 - -/* Level 2 Peripheral IRQ mappings */ -#define IRQ_EXT_HP_GPDMA_LVL2 IRQ_BIT_LVL2_HP_GP_DMA0(0) -#define IRQ_EXT_IDC_LVL2 IRQ_BIT_LVL2_IDC -#define IRQ_EXT_IPC_LVL2 IRQ_BIT_LVL2_HOST_IPC -#define IRQ_EXT_TSTAMP1_LVL2 IRQ_BIT_LVL2_WALL_CLK1 -#define IRQ_EXT_TSTAMP0_LVL2 IRQ_BIT_LVL2_WALL_CLK0 -#define IRQ_EXT_MERR_LVL2 IRQ_BIT_LVL2_L2_MEMERR -#define IRQ_EXT_L2CACHE_LVL2 IRQ_BIT_LVL2_L2_CACHE -#define IRQ_EXT_SHA256_LVL2 IRQ_BIT_LVL2_SHA256 - -#define IRQ_MASK_SOFTWARE2 BIT(IRQ_NUM_SOFTWARE2) -#define IRQ_MASK_TIMER2 BIT(IRQ_NUM_TIMER2) -#define IRQ_MASK_EXT_LEVEL2 BIT(IRQ_NUM_EXT_LEVEL2) -#define IRQ_MASK_SOFTWARE3 BIT(IRQ_NUM_SOFTWARE3) - -#endif - -#if CONFIG_XT_INTERRUPT_LEVEL_3 - -#define IRQ_NUM_SOFTWARE4 8 /* level 3 */ -#define IRQ_NUM_TIMER3 9 /* level 3 */ -#define IRQ_NUM_EXT_LEVEL3 10 /* level 3 */ -#define IRQ_NUM_SOFTWARE5 11 /* level 3 */ - -/* IRQ Level 3 bits */ -#define IRQ_BIT_LVL3_CODE_LOADER 31 -#define IRQ_BIT_LVL3_HOST_STREAM_OUT(x) (16 + x) -#define IRQ_BIT_LVL3_HOST_STREAM_IN(x) (0 + x) - -/* Level 3 Peripheral IRQ mappings */ -#define IRQ_EXT_CODE_DMA_LVL3 IRQ_BIT_LVL3_CODE_LOADER -#define IRQ_EXT_HOST_DMA_IN_LVL3(channel) IRQ_BIT_LVL3_HOST_STREAM_IN(channel) -#define IRQ_EXT_HOST_DMA_OUT_LVL3(channel) IRQ_BIT_LVL3_HOST_STREAM_OUT(channel) - -#define IRQ_MASK_SOFTWARE4 BIT(IRQ_NUM_SOFTWARE4) -#define IRQ_MASK_TIMER3 BIT(IRQ_NUM_TIMER3) -#define IRQ_MASK_EXT_LEVEL3 BIT(IRQ_NUM_EXT_LEVEL3) -#define IRQ_MASK_SOFTWARE5 BIT(IRQ_NUM_SOFTWARE5) - -#endif - -#if CONFIG_XT_INTERRUPT_LEVEL_4 - -#define IRQ_NUM_SOFTWARE6 12 /* level 4 */ -#define IRQ_NUM_EXT_LEVEL4 13 /* level 4 */ -#define IRQ_NUM_SOFTWARE7 14 /* level 4 */ - -/* IRQ Level 4 bits */ -#define IRQ_BIT_LVL4_LINK_STREAM_OUT(x) (16 + x) -#define IRQ_BIT_LVL4_LINK_STREAM_IN(x) (0 + x) - -/* Level 4 Peripheral IRQ mappings */ -#define IRQ_EXT_LINK_DMA_IN_LVL4(channel) IRQ_BIT_LVL4_LINK_STREAM_IN(channel) -#define IRQ_EXT_LINK_DMA_OUT_LVL4(channel) IRQ_BIT_LVL4_LINK_STREAM_OUT(channel) - -#define IRQ_MASK_SOFTWARE6 BIT(IRQ_NUM_SOFTWARE6) -#define IRQ_MASK_EXT_LEVEL4 BIT(IRQ_NUM_EXT_LEVEL4) -#define IRQ_MASK_SOFTWARE7 BIT(IRQ_NUM_SOFTWARE7) - -#endif - -#if CONFIG_XT_INTERRUPT_LEVEL_5 - -#define IRQ_NUM_SOFTWARE8 15 /* level 5 */ -#define IRQ_NUM_EXT_LEVEL5 16 /* level 5 */ -#define IRQ_NUM_EXT_LEVEL6 17 /* level 5 */ -#define IRQ_NUM_EXT_LEVEL7 18 /* level 5 */ -#define IRQ_NUM_SOFTWARE9 19 /* level 5 */ - -/* IRQ Level 5 bits */ -#define IRQ_BIT_LVL5_LP_GP_DMA1(x) (24 + x) -#define IRQ_BIT_LVL5_LP_GP_DMA0(x) (16 + x) -#define IRQ_BIT_LVL5_DMIC(x) 6 -#define IRQ_BIT_LVL5_SSP(x) (0 + x) - -/* Level 5 Peripheral IRQ mappings */ -#define IRQ_EXT_LP_GPDMA0_LVL5(channel) IRQ_BIT_LVL5_LP_GP_DMA0(channel) -#define IRQ_EXT_LP_GPDMA1_LVL5(channel) IRQ_BIT_LVL5_LP_GP_DMA1(channel) -#define IRQ_EXT_SSPx_LVL5(x) IRQ_BIT_LVL5_SSP(x) -#define IRQ_EXT_DMIC_LVL5(x) IRQ_BIT_LVL5_DMIC(x) - -#define IRQ_MASK_SOFTWARE8 BIT(IRQ_NUM_SOFTWARE8) -#define IRQ_MASK_EXT_LEVEL5 BIT(IRQ_NUM_EXT_LEVEL5) -#define IRQ_MASK_EXT_LEVEL6 BIT(IRQ_NUM_EXT_LEVEL6) -#define IRQ_MASK_EXT_LEVEL7 BIT(IRQ_NUM_EXT_LEVEL7) -#define IRQ_MASK_SOFTWARE9 BIT(IRQ_NUM_SOFTWARE9) - -#endif - -#define IRQ_NUM_NMI 20 /* level 7 */ - -#endif /* __PLATFORM_DRIVERS_INTERRUPT_H__ */ - -#else - -#error "This file shouldn't be included from outside of sof/drivers/interrupt.h" - -#endif /* __SOF_DRIVERS_INTERRUPT_H__ */ diff --git a/src/platform/apollolake/include/platform/drivers/mn.h b/src/platform/apollolake/include/platform/drivers/mn.h deleted file mode 100644 index 55f36475e21e..000000000000 --- a/src/platform/apollolake/include/platform/drivers/mn.h +++ /dev/null @@ -1,21 +0,0 @@ -/* SPDX-License-Identifier: BSD-3-Clause - * - * Copyright(c) 2020 Intel Corporation. All rights reserved. - * - * Author: Janusz Jankowski - */ - -#ifdef __SOF_DRIVERS_MN_H__ - -#ifndef __PLATFORM_DRIVERS_MN_H__ -#define __PLATFORM_DRIVERS_MN_H__ - -#include - -#endif /* __PLATFORM_DRIVERS_MN_H__ */ - -#else - -#error "This file shouldn't be included from outside of sof/drivers/mn.h" - -#endif /* __SOF_DRIVERS_MN_H__ */ diff --git a/src/platform/apollolake/include/platform/drivers/timestamp.h b/src/platform/apollolake/include/platform/drivers/timestamp.h deleted file mode 100644 index 594c99493184..000000000000 --- a/src/platform/apollolake/include/platform/drivers/timestamp.h +++ /dev/null @@ -1,42 +0,0 @@ -/* SPDX-License-Identifier: BSD-3-Clause - * - * Copyright(c) 2020 Intel Corporation. All rights reserved. - * - * Author: Tomasz Lauda - */ - -#ifdef __SOF_DRIVERS_TIMESTAMP_H__ - -#ifndef __PLATFORM_DRIVERS_TIMESTAMP_H__ -#define __PLATFORM_DRIVERS_TIMESTAMP_H__ - -#include - -#define TS_DMIC_LOCAL_TSCTRL 0x000 -#define TS_DMIC_LOCAL_OFFS 0x004 -#define TS_DMIC_LOCAL_SAMPLE 0x008 -#define TS_DMIC_LOCAL_WALCLK 0x010 -#define TS_DMIC_TSCC 0x018 -#define TS_I2S_LOCAL_TSCTRL(x) (0x040 + 0x20 * (x) + 0x00) -#define TS_I2S_LOCAL_OFFS(x) (0x040 + 0x20 * (x) + 0x04) -#define TS_I2S_LOCAL_SAMPLE(x) (0x040 + 0x20 * (x) + 0x08) -#define TS_I2S_LOCAL_WALCLK(x) (0x040 + 0x20 * (x) + 0x10) -#define TS_I2S_TSCC(x) (0x040 + 0x20 * (x) + 0x18) -#define TS_HDA_LOCAL_TSCTRL (0x0e0 + 0x00) -#define TS_HDA_LOCAL_OFFS (0x0e0 + 0x04) -#define TS_HDA_LOCAL_SAMPLE (0x0e0 + 0x08) -#define TS_HDA_LOCAL_WALCLK (0x0e0 + 0x10) -#define TS_HDA_TSCC (0x0e0 + 0x18) -#define TS_I2SE_LOCAL_TSCTRL(x) (0x120 + 0x20 * ((x) - 4) + 0x00) -#define TS_I2SE_LOCAL_OFFS(x) (0x120 + 0x20 * ((x) - 4) + 0x04) -#define TS_I2SE_LOCAL_SAMPLE(x) (0x120 + 0x20 * ((x) - 4) + 0x08) -#define TS_I2SE_LOCAL_WALCLK(x) (0x120 + 0x20 * ((x) - 4) + 0x10) -#define TS_I2SE_TSCC(x) (0x120 + 0x20 * ((x) - 4) + 0x18) - -#endif /* __PLATFORM_DRIVERS_TIMESTAMP_H__ */ - -#else - -#error "This file shouldn't be included from outside of sof/drivers/timestamp.h" - -#endif /* __SOF_DRIVERS_TIMESTAMP_H__ */ diff --git a/src/platform/apollolake/include/platform/lib/asm_ldo_management.h b/src/platform/apollolake/include/platform/lib/asm_ldo_management.h deleted file mode 100644 index 549a47b850cd..000000000000 --- a/src/platform/apollolake/include/platform/lib/asm_ldo_management.h +++ /dev/null @@ -1,20 +0,0 @@ -/* SPDX-License-Identifier: BSD-3-Clause - * - * Copyright(c) 2019 Intel Corporation. All rights reserved. - * - * Author: Lech Betlej - */ - -/** - * \file - * \brief Macros for controlling LDO state specific for cAVS 1.5. The header is - * intended to be used in Apollolake specific implementation of power_down - * routine - */ - -#ifndef __PLATFORM_LIB_ASM_LDO_MANAGEMENT_H__ -#define __PLATFORM_LIB_ASM_LDO_MANAGEMENT_H__ - -#include - -#endif /* __PLATFORM_LIB_ASM_LDO_MANAGEMENT_H__ */ diff --git a/src/platform/apollolake/include/platform/lib/asm_memory_management.h b/src/platform/apollolake/include/platform/lib/asm_memory_management.h deleted file mode 100644 index 68b3abcf29ba..000000000000 --- a/src/platform/apollolake/include/platform/lib/asm_memory_management.h +++ /dev/null @@ -1,70 +0,0 @@ -/* SPDX-License-Identifier: BSD-3-Clause - * - * Copyright(c) 2018 Intel Corporation. All rights reserved. - * - * Author: Lech Betlej - */ - -/** - * \file platform/apollolake/include/platform/lib/asm_memory_management.h - * \brief Macros for power gating memory banks specific for Apollolake - * \author Lech Betlej - */ - -#ifndef __PLATFORM_LIB_ASM_MEMORY_MANAGEMENT_H__ -#define __PLATFORM_LIB_ASM_MEMORY_MANAGEMENT_H__ - -#ifndef ASSEMBLY -#warning "ASSEMBLY macro not defined." -#endif - -#include -#include - - /* Macro powers down entire hpsram. on entry literals and code for - * section from where this code is executed needs to be placed in - * memory which is not HPSRAM (in case when this code is located in - * HPSRAM lock memory in L1$ or L1 SRAM) - */ - .macro m_cavs_hpsram_power_off ax, ay, az - // SEGMENT #0 - movi \az, (SHIM_BASE + SHIM_HSPGISTS) - movi \ax, (SHIM_BASE + SHIM_HSPGCTL) - movi \ay, HPSRAM_MASK(0) - s32i \ay, \ax, 0 - memw - /* since HPSRAM EBB bank #0 might be used as buffer for legacy - * streaming, should not be checked in status - */ - movi \ax, 0xfffffffe - and \ay, \ay, \ax - 1 : - l32i \ax, \az, 0 - and \ax, \ax, \ay - bne \ax, \ay, 1b - /* there is no possibility to check from DSP whether EBB #0 is actually - * in use therefore wait additional 4K DSP cycles as chicken check - - * after that time EBB #0 should be already power gated unless is used - * by other HW components (like HD-A) - */ - l32i \ax, \az, 0 - beq \ax, \ay, m_cavs_hpsram_power_off_end - movi \ax, 4096 - 1 : - addi \ax, \ax, -1 - bnez \ax, 1b - m_cavs_hpsram_power_off_end : - .endm - - .macro m_cavs_lpsram_power_off ax, ay, az - movi \az, (SHIM_BASE + SHIM_LSPGISTS) - movi \ax, (SHIM_BASE + SHIM_LSPGCTL) - movi \ay, LPSRAM_MASK() - s32i \ay, \ax, 0 - memw - 1 : - l32i \ax, \az, 0 - bne \ax, \ay, 1b - .endm - -#endif /* __PLATFORM_LIB_ASM_MEMORY_MANAGEMENT_H__ */ diff --git a/src/platform/apollolake/include/platform/lib/clk.h b/src/platform/apollolake/include/platform/lib/clk.h deleted file mode 100644 index 0b5e87b34055..000000000000 --- a/src/platform/apollolake/include/platform/lib/clk.h +++ /dev/null @@ -1,42 +0,0 @@ -/* SPDX-License-Identifier: BSD-3-Clause - * - * Copyright(c) 2016 Intel Corporation. All rights reserved. - * - * Author: Liam Girdwood - * Keyon Jie - */ - -#ifdef __SOF_LIB_CLK_H__ - -#ifndef __PLATFORM_LIB_CLK_H__ -#define __PLATFORM_LIB_CLK_H__ - -#include - -#define CLK_MAX_CPU_HZ 400000000 - -#define CPU_LPRO_FREQ_IDX 0 - -#define CPU_HPRO_FREQ_IDX 2 - -#define CPU_LOWEST_FREQ_IDX CPU_LPRO_FREQ_IDX - -#if CONFIG_CAVS_LPRO_ONLY -#define CPU_DEFAULT_IDX CPU_LPRO_FREQ_IDX -#else -#define CPU_DEFAULT_IDX CPU_HPRO_FREQ_IDX -#endif - -#define SSP_DEFAULT_IDX 0 - -#define NUM_CPU_FREQ 3 - -#define NUM_SSP_FREQ 3 - -#endif /* __PLATFORM_LIB_CLK_H__ */ - -#else - -#error "This file shouldn't be included from outside of sof/lib/clk.h" - -#endif /* __SOF_LIB_CLK_H__ */ diff --git a/src/platform/apollolake/include/platform/lib/cpu.h b/src/platform/apollolake/include/platform/lib/cpu.h deleted file mode 100644 index 8cd110966e66..000000000000 --- a/src/platform/apollolake/include/platform/lib/cpu.h +++ /dev/null @@ -1,26 +0,0 @@ -/* SPDX-License-Identifier: BSD-3-Clause - * - * Copyright(c) 2019 Intel Corporation. All rights reserved. - * - * Author: Tomasz Lauda - */ - -/** - * \file - * \brief DSP core parameters. - */ - -#ifdef __SOF_LIB_CPU_H__ - -#ifndef __PLATFORM_LIB_CPU_H__ -#define __PLATFORM_LIB_CPU_H__ - -#include - -#endif /* __PLATFORM_LIB_CPU_H__ */ - -#else - -#error "This file shouldn't be included from outside of sof/lib/cpu.h" - -#endif /* __SOF_LIB_CPU_H__ */ diff --git a/src/platform/apollolake/include/platform/lib/dai.h b/src/platform/apollolake/include/platform/lib/dai.h deleted file mode 100644 index 60d6ddce9b92..000000000000 --- a/src/platform/apollolake/include/platform/lib/dai.h +++ /dev/null @@ -1,46 +0,0 @@ -/* SPDX-License-Identifier: BSD-3-Clause - * - * Copyright(c) 2018 Intel Corporation. All rights reserved. - * - * Author: Marcin Maka - */ - -#ifdef __SOF_LIB_DAI_H__ - -#ifndef __PLATFORM_LIB_DAI_H__ -#define __PLATFORM_LIB_DAI_H__ - -/* APOLLOLAKE */ - -/* SSP */ - -/* - * Number of base and extended SSP ports must be defined separately - * since some HW registers are in two groups, one for base and one - * for extended. - */ - -/** \brief Number of 'base' SSP ports available */ -#define DAI_NUM_SSP_BASE 4 - -/** \brief Number of 'extended' SSP ports available */ -#define DAI_NUM_SSP_EXT 2 - -/** \brief Number of SSP MCLKs available */ -#define DAI_NUM_SSP_MCLK 2 - -/* HD/A */ - -/** \brief Number of HD/A Link Outputs */ -#define DAI_NUM_HDA_OUT 6 - -/** \brief Number of HD/A Link Inputs */ -#define DAI_NUM_HDA_IN 7 - -#endif /* __PLATFORM_LIB_DAI_H__ */ - -#else - -#error "This file shouldn't be included from outside of sof/lib/dai.h" - -#endif /* __SOF_LIB_DAI_H__ */ diff --git a/src/platform/apollolake/include/platform/lib/dma.h b/src/platform/apollolake/include/platform/lib/dma.h deleted file mode 100644 index d8793eab9baa..000000000000 --- a/src/platform/apollolake/include/platform/lib/dma.h +++ /dev/null @@ -1,65 +0,0 @@ -/* SPDX-License-Identifier: BSD-3-Clause - * - * Copyright(c) 2016 Intel Corporation. All rights reserved. - * - * Author: Liam Girdwood - * Keyon Jie - */ - -#ifdef __SOF_LIB_DMA_H__ - -#ifndef __PLATFORM_LIB_DMA_H__ -#define __PLATFORM_LIB_DMA_H__ - -/* number of supported DMACs */ -#define PLATFORM_NUM_DMACS 6 - -/* max number of supported DMA channels */ -#define PLATFORM_MAX_DMA_CHAN 8 - -/* available DMACs */ -#define DMA_GP_LP_DMAC0 0 -#define DMA_GP_LP_DMAC1 1 -#define DMA_GP_HP_DMAC0 2 -#define DMA_GP_HP_DMAC1 3 -#define DMA_HOST_IN_DMAC 4 -#define DMA_HOST_OUT_DMAC 5 -#define DMA_LINK_IN_DMAC 6 -#define DMA_LINK_OUT_DMAC 7 - -/* mappings - TODO improve API to get type */ -#define DMA_ID_DMAC0 DMA_HOST_IN_DMAC -#define DMA_ID_DMAC1 DMA_GP_LP_DMAC0 -#define DMA_ID_DMAC2 DMA_HOST_OUT_DMAC -#define DMA_ID_DMAC3 DMA_GP_HP_DMAC0 -#define DMA_ID_DMAC4 DMA_GP_LP_DMAC1 -#define DMA_ID_DMAC5 DMA_GP_HP_DMAC1 -#define DMA_ID_DMAC6 DMA_LINK_IN_DMAC -#define DMA_ID_DMAC7 DMA_LINK_OUT_DMAC - -/* handshakes */ -#define DMA_HANDSHAKE_DMIC_CH0 0 -#define DMA_HANDSHAKE_DMIC_CH1 1 -#define DMA_HANDSHAKE_SSP0_TX 2 -#define DMA_HANDSHAKE_SSP0_RX 3 -#define DMA_HANDSHAKE_SSP1_TX 4 -#define DMA_HANDSHAKE_SSP1_RX 5 -#define DMA_HANDSHAKE_SSP2_TX 6 -#define DMA_HANDSHAKE_SSP2_RX 7 -#define DMA_HANDSHAKE_SSP3_TX 8 -#define DMA_HANDSHAKE_SSP3_RX 9 -#define DMA_HANDSHAKE_SSP4_TX 10 -#define DMA_HANDSHAKE_SSP4_RX 11 -#define DMA_HANDSHAKE_SSP5_TX 12 -#define DMA_HANDSHAKE_SSP5_RX 13 - -#define dma_chan_irq(dma, chan) (dma_irq(dma) + chan) -#define dma_chan_irq_name(dma, chan) dma_irq_name(dma) - -#endif /* __PLATFORM_LIB_DMA_H__ */ - -#else - -#error "This file shouldn't be included from outside of sof/lib/dma.h" - -#endif /* __SOF_LIB_DMA_H__ */ diff --git a/src/platform/apollolake/include/platform/lib/mailbox.h b/src/platform/apollolake/include/platform/lib/mailbox.h deleted file mode 100644 index baf6539a9fc3..000000000000 --- a/src/platform/apollolake/include/platform/lib/mailbox.h +++ /dev/null @@ -1,22 +0,0 @@ -/* SPDX-License-Identifier: BSD-3-Clause - * - * Copyright(c) 2016 Intel Corporation. All rights reserved. - * - * Author: Liam Girdwood - * Keyon Jie - */ - -#ifdef __SOF_LIB_MAILBOX_H__ - -#ifndef __PLATFORM_LIB_MAILBOX_H__ -#define __PLATFORM_LIB_MAILBOX_H__ - -#include - -#endif /* __PLATFORM_LIB_MAILBOX_H__ */ - -#else - -#error "This file shouldn't be included from outside of sof/lib/mailbox.h" - -#endif /* __SOF_LIB_MAILBOX_H__ */ diff --git a/src/platform/apollolake/include/platform/lib/memory.h b/src/platform/apollolake/include/platform/lib/memory.h deleted file mode 100644 index 7b41cfff821e..000000000000 --- a/src/platform/apollolake/include/platform/lib/memory.h +++ /dev/null @@ -1,494 +0,0 @@ -/* SPDX-License-Identifier: BSD-3-Clause - * - * Copyright(c) 2016 Intel Corporation. All rights reserved. - * - * Author: Liam Girdwood - * Keyon Jie - */ - -#ifdef __SOF_LIB_MEMORY_H__ - -#ifndef __PLATFORM_LIB_MEMORY_H__ -#define __PLATFORM_LIB_MEMORY_H__ - -#include -#include - -/* prioritize definitions in Zephyr SoC layer */ -#ifdef __ZEPHYR__ -#include -#endif - -/* physical DSP addresses */ - -/* shim */ -#define SHIM_BASE 0x00001000 -#define SHIM_SIZE 0x00000100 - -/* cmd IO to audio codecs */ -#define CMD_BASE 0x00001100 -#define CMD_SIZE 0x00000010 - -/* resource allocation */ -#define RES_BASE 0x00001110 -#define RES_SIZE 0x00000010 - -/* IPC to the host */ -#define IPC_HOST_BASE 0x00001180 -#define IPC_HOST_SIZE 0x00000020 - -/* intra DSP IPC */ -#define IPC_DSP_SIZE 0x00000080 -#define IPC_DSP_BASE(x) (0x00001200 + x * IPC_DSP_SIZE) - -/* SRAM window for HOST */ -#define HOST_WIN_SIZE 0x00000008 -#define HOST_WIN_BASE(x) (0x00001580 + x * HOST_WIN_SIZE) - -/* IRQ controller */ -#define IRQ_BASE 0x00001600 -#define IRQ_SIZE 0x00000200 - -/* time stamping */ -#define TIME_BASE 0x00001800 -#define TIME_SIZE 0x00000200 - -/* M/N dividers */ -#define MN_BASE 0x00008E00 -#define MN_SIZE 0x00000200 - -/* low power DMA position */ -#define LP_GP_DMA_LINK_SIZE 0x00000010 -#define LP_GP_DMA_LINK_BASE(x) (0x00001C00 + x * LP_GP_DMA_LINK_SIZE) - -/* high performance DMA position */ -#define HP_GP_DMA_LINK_SIZE 0x00000010 -#define HP_GP_DMA_LINK_BASE(x) (0x00001D00 + x * HP_GP_DMA_LINK_SIZE) - -/* link DMAC stream */ -#define GTW_LINK_OUT_STREAM_SIZE 0x00000020 -#define GTW_LINK_OUT_STREAM_BASE(x) \ - (0x00002400 + x * GTW_LINK_OUT_STREAM_SIZE) - -#define GTW_LINK_IN_STREAM_SIZE 0x00000020 -#define GTW_LINK_IN_STREAM_BASE(x) \ - (0x00002600 + x * GTW_LINK_IN_STREAM_SIZE) - -/* host DMAC stream */ -#define GTW_HOST_OUT_STREAM_SIZE 0x00000040 -#define GTW_HOST_OUT_STREAM_BASE(x) \ - (0x00002800 + x * GTW_HOST_OUT_STREAM_SIZE) - -#define GTW_HOST_IN_STREAM_SIZE 0x00000040 -#define GTW_HOST_IN_STREAM_BASE(x) \ - (0x00002C00 + x * GTW_HOST_IN_STREAM_SIZE) - -/* code loader */ -#define GTW_CODE_LDR_SIZE 0x00000040 -#define GTW_CODE_LDR_BASE 0x00002BC0 - -/* L2 TLBs */ -#define L2_HP_SRAM_TLB_SIZE 0x00001000 -#define L2_HP_SRAM_TLB_BASE 0x00003000 - -/* DMICs */ -#define DMIC_BASE 0x00004000 -#define DMIC_SIZE 0x00004000 - -/* SSP */ -#define SSP_SIZE 0x0000200 -#define SSP_BASE(x) (0x00008000 + x * SSP_SIZE) - -/* Timestamp */ -#define TIMESTAMP_BASE 0x00001800 - -/* low power DMACs */ -#define LP_GP_DMA_SIZE 0x00001000 -#define LP_GP_DMA_BASE(x) (0x0000C000 + x * LP_GP_DMA_SIZE) - -/* high performance DMACs */ -#define HP_GP_DMA_SIZE 0x00001000 -#define HP_GP_DMA_BASE(x) (0x0000E000 + x * HP_GP_DMA_SIZE) - -/* ROM */ -#define ROM_BASE 0xBEFE0000 -#define ROM_SIZE 0x00002000 - -/* IMR accessible via L2$ */ -#ifndef L2_SRAM_BASE -#define L2_SRAM_BASE 0xA000A000 -#endif -#ifndef L2_SRAM_SIZE -#define L2_SRAM_SIZE 0x00056000 -#endif - -#define L2_VECTOR_SIZE 0x1000 - -#define UUID_ENTRY_ELF_BASE 0x1FFFA000 -#define UUID_ENTRY_ELF_SIZE 0x6000 - -#define LOG_ENTRY_ELF_BASE 0x20000000 -#define LOG_ENTRY_ELF_SIZE 0x2000000 - -#define EXT_MANIFEST_ELF_BASE (LOG_ENTRY_ELF_BASE + LOG_ENTRY_ELF_SIZE) -#define EXT_MANIFEST_ELF_SIZE 0x2000000 - -/* - * The HP SRAM Region Apollolake is organised like this. Lower - * addresses are first. See also mailbox.h. - * - * +--------------------------------------------------------------------------+ - * | Offset | Region | Size | - * +------------------+-------------------------+-----------------------------+ - * | SRAM_TRACE_BASE | Trace Buffer W3 | SRAM_TRACE_SIZE | - * +------------------+-------------------------+-----------------------------+ - * | SRAM_DEBUG_BASE | Debug data W2 | SRAM_DEBUG_SIZE | - * +------------------+-------------------------+-----------------------------+ - * | SRAM_EXCEPT_BASE | Debug data W2 | SRAM_EXCEPT_SIZE | - * +------------------+-------------------------+-----------------------------+ - * | SRAM_STREAM_BASE | Stream data W2 | SRAM_STREAM_SIZE | - * +------------------+-------------------------+-----------------------------+ - * | SRAM_INBOX_BASE | Inbox W1 | SRAM_INBOX_SIZE | - * +------------------+-------------------------+-----------------------------+ - * | SRAM_SW_REG_BASE | SW Registers W0 | SRAM_SW_REG_SIZE | - * +------------------+-------------------------+-----------------------------+ - * | SRAM_OUTBOX_BASE | Outbox W0 | SRAM_OUTBOX_SIZE | - * +------------------+-------------------------+-----------------------------+ - * - * +------------------+-------------------------+-----------------------------+ - * | SOF_FW_START | text | | - * | | data | | - * | | ----------------------- | | - * | ||BSS: || | - * | ||-----------------------++-----------------------------+ - * | ||Runtime Heap || HEAP_RUNTIME_SIZE | - * | ||-----------------------++-----------------------------+ - * | ||Runtime shared Heap || HEAP_RUNTIME_SHARED_SIZE | - * | ||-----------------------++-----------------------------+ - * | ||System shared Heap || HEAP_SYSTEM_SHARED_SIZE | - * | ||-----------------------++-----------------------------+ - * | ||Module Buffers || HEAP_BUFFER_SIZE | - * | ||-----------------------++-----------------------------+ - * | ||Primary core Sys Heap || HEAP_SYSTEM_M_SIZE | - * | ||-----------------------++-----------------------------+ - * | ||Pri. Sys Runtime Heap || HEAP_SYS_RUNTIME_M_SIZE | - * | ||-----------------------++-----------------------------+ - * | ||Primary core Stack || SOF_STACK_SIZE | - * | ||-----------------------++-----------------------------+ - * | ||Sec. core Sys Heap || SOF_CORE_S_T_SIZE | - * | ||Sec. Sys Runtime Heap || | - * | ||Secondary core Stack || | - * | | ----------------------- | | - * +------------------+-------------------------+-----------------------------+ - */ - -/* HP SRAM */ - -#define HP_SRAM_BASE 0xBE000000 - -/* HP SRAM windows */ - -/* window 3 */ -#define SRAM_TRACE_BASE SRAM_WND_BASE -#if CONFIG_TRACE -#define SRAM_TRACE_SIZE 0x2000 -#else -#define SRAM_TRACE_SIZE 0 -#endif - -/* window 2 */ -#define SRAM_DEBUG_BASE (SRAM_TRACE_BASE + SRAM_TRACE_SIZE) -#define SRAM_DEBUG_SIZE 0x800 - -#define SRAM_EXCEPT_BASE (SRAM_DEBUG_BASE + SRAM_DEBUG_SIZE) -#define SRAM_EXCEPT_SIZE 0x800 - -#define SRAM_STREAM_BASE (SRAM_EXCEPT_BASE + SRAM_EXCEPT_SIZE) -#define SRAM_STREAM_SIZE 0x1000 - -/* window 1 */ -#define SRAM_INBOX_BASE (SRAM_STREAM_BASE + SRAM_STREAM_SIZE) -#define SRAM_INBOX_SIZE 0x2000 - -/* window 0 */ -#define SRAM_SW_REG_BASE (SRAM_INBOX_BASE + SRAM_INBOX_SIZE) -#define SRAM_SW_REG_SIZE 0x1000 - -#define SRAM_OUTBOX_BASE (SRAM_SW_REG_BASE + SRAM_SW_REG_SIZE) -#define SRAM_OUTBOX_SIZE 0x1000 - -#define HP_SRAM_WIN0_BASE SRAM_SW_REG_BASE -#define HP_SRAM_WIN0_SIZE (SRAM_SW_REG_SIZE + SRAM_OUTBOX_SIZE) -#define HP_SRAM_WIN1_BASE SRAM_INBOX_BASE -#define HP_SRAM_WIN1_SIZE SRAM_INBOX_SIZE -#define HP_SRAM_WIN2_BASE SRAM_DEBUG_BASE -#define HP_SRAM_WIN2_SIZE (SRAM_DEBUG_SIZE + SRAM_EXCEPT_SIZE + \ - SRAM_STREAM_SIZE) -#define HP_SRAM_WIN3_BASE SRAM_TRACE_BASE -#define HP_SRAM_WIN3_SIZE SRAM_TRACE_SIZE - -/* Apollolake HP-SRAM config */ -#if CONFIG_APOLLOLAKE && !(CONFIG_KABYLAKE || CONFIG_SKYLAKE) - -#define SRAM_WND_BASE (HP_SRAM_BASE) - -#define HP_SRAM_VECBASE_RESET (HP_SRAM_WIN0_BASE + HP_SRAM_WIN0_SIZE) -#define HP_SRAM_VECBASE_OFFSET 0x0 - -#define SOF_FW_START (HP_SRAM_VECBASE_RESET + 0x400) -#define SOF_FW_BASE (SOF_FW_START) - -/* Skylake or kabylake HP-SRAM config */ -#elif CONFIG_KABYLAKE || CONFIG_SKYLAKE - -#define SRAM_WND_BASE 0xBE058000 - -#define HP_SRAM_VECBASE_RESET 0xBE0A0000 -#define HP_SRAM_VECBASE_OFFSET 0x800 -#define HP_SRAM_RESET_TEXT_SIZE 0x400 -#define HP_SRAM_RESET_LIT_SIZE 0x100 - -#define SOF_FW_START HP_SRAM_VECBASE_RESET -#define SOF_FW_BASE (SOF_FW_START + 0x1000) - -#else -#error Platform not specified -#endif - -/* max size for all var-size sections (text/rodata/bss) */ -#define SOF_FW_MAX_SIZE (HP_SRAM_BASE + HP_SRAM_SIZE - SOF_FW_BASE) - -/* TODO: the last 4KB is not usable with QEMU, need to debug it. */ -#define SOF_FW_END (HP_SRAM_BASE + HP_SRAM_SIZE - 0x1000) - -#define SOF_TEXT_START (SOF_FW_START) -#define SOF_TEXT_BASE (SOF_FW_START) - -/* Heap section sizes for system runtime heap for primary core */ -#define HEAP_SYS_RT_0_COUNT64 64 -#define HEAP_SYS_RT_0_COUNT512 8 -#define HEAP_SYS_RT_0_COUNT1024 2 - -/* Heap section sizes for system runtime heap for secondary core */ -#define HEAP_SYS_RT_X_COUNT64 32 -#define HEAP_SYS_RT_X_COUNT512 4 -#define HEAP_SYS_RT_X_COUNT1024 2 - -/* Heap section counts base */ -#define HEAP_COUNT64 128 -#define HEAP_COUNT128 96 -#define HEAP_COUNT256 112 -#define HEAP_COUNT512 12 -#define HEAP_COUNT1024 3 -#define HEAP_COUNT2048 1 -#define HEAP_COUNT4096 0 - -#define RT_TIMES 1 -#define RT_SHARED_TIMES 1 - -/* Heap section sizes for module pool */ -#define HEAP_RT_COUNT64 (HEAP_COUNT64 * RT_TIMES) -#define HEAP_RT_COUNT128 (HEAP_COUNT128 * RT_TIMES) -#define HEAP_RT_COUNT256 (HEAP_COUNT256 * RT_TIMES) -#define HEAP_RT_COUNT512 (HEAP_COUNT512 * RT_TIMES) -#define HEAP_RT_COUNT1024 (HEAP_COUNT1024 * RT_TIMES) -#define HEAP_RT_COUNT2048 (HEAP_COUNT2048 * RT_TIMES) -#define HEAP_RT_COUNT4096 (HEAP_COUNT4096 * RT_TIMES) - -/* Heap configuration */ -#define HEAP_RUNTIME_SIZE \ - (HEAP_RT_COUNT64 * 64 + HEAP_RT_COUNT128 * 128 + \ - HEAP_RT_COUNT256 * 256 + HEAP_RT_COUNT512 * 512 + \ - HEAP_RT_COUNT1024 * 1024 + HEAP_RT_COUNT2048 * 2048 + \ - HEAP_RT_COUNT4096 * 4096) - -/* Heap section sizes for runtime shared heap */ -#define HEAP_RUNTIME_SHARED_COUNT64 (HEAP_COUNT64 * RT_SHARED_TIMES) -#define HEAP_RUNTIME_SHARED_COUNT128 (HEAP_COUNT128 * RT_SHARED_TIMES) -#define HEAP_RUNTIME_SHARED_COUNT256 (HEAP_COUNT256 * RT_SHARED_TIMES) -#define HEAP_RUNTIME_SHARED_COUNT512 (HEAP_COUNT512 * RT_SHARED_TIMES) -#define HEAP_RUNTIME_SHARED_COUNT1024 (HEAP_COUNT1024 * RT_SHARED_TIMES) - -#define HEAP_RUNTIME_SHARED_SIZE \ - (HEAP_RUNTIME_SHARED_COUNT64 * 64 + HEAP_RUNTIME_SHARED_COUNT128 * 128 + \ - HEAP_RUNTIME_SHARED_COUNT256 * 256 + HEAP_RUNTIME_SHARED_COUNT512 * 512 + \ - HEAP_RUNTIME_SHARED_COUNT1024 * 1024) - -/* Heap section sizes for system shared heap */ -#define HEAP_SYSTEM_SHARED_SIZE 0x1500 - -#define HEAP_BUFFER_BLOCK_SIZE 0x100 -/* - * The buffer zone will not occupy more than half of the HP SRAM on APL, - * enforcing this limit due to the the SRAM size limitations on APL. - */ -#define HEAP_BUFFER_COUNT_MAX (HP_SRAM_SIZE / (HEAP_BUFFER_BLOCK_SIZE * 2)) - -#define HEAP_SYSTEM_M_SIZE 0x4000 /* heap primary core size */ -#define HEAP_SYSTEM_S_SIZE 0x3000 /* heap secondary core size */ -#define HEAP_SYSTEM_T_SIZE \ - (HEAP_SYSTEM_M_SIZE + ((CONFIG_CORE_COUNT - 1) * HEAP_SYSTEM_S_SIZE)) - -#define HEAP_SYS_RUNTIME_M_SIZE \ - (HEAP_SYS_RT_0_COUNT64 * 64 + HEAP_SYS_RT_0_COUNT512 * 512 + \ - HEAP_SYS_RT_0_COUNT1024 * 1024) - -#define HEAP_SYS_RUNTIME_S_SIZE \ - (HEAP_SYS_RT_X_COUNT64 * 64 + HEAP_SYS_RT_X_COUNT512 * 512 + \ - HEAP_SYS_RT_X_COUNT1024 * 1024) - -#define HEAP_SYS_RUNTIME_T_SIZE \ - (HEAP_SYS_RUNTIME_M_SIZE + ((CONFIG_CORE_COUNT - 1) * \ - HEAP_SYS_RUNTIME_S_SIZE)) - -/* Stack configuration */ -#define SOF_STACK_SIZE (CONFIG_SOF_STACK_SIZE) -#define SOF_STACK_TOTAL_SIZE (CONFIG_CORE_COUNT * SOF_STACK_SIZE) - -/* SOF Core S configuration */ -#define SOF_CORE_S_SIZE \ - ALIGN((HEAP_SYSTEM_S_SIZE + HEAP_SYS_RUNTIME_S_SIZE + SOF_STACK_SIZE),\ - SRAM_BANK_SIZE) -#define SOF_CORE_S_T_SIZE ((CONFIG_CORE_COUNT - 1) * SOF_CORE_S_SIZE) - -/* - * The LP SRAM Heap and Stack on Apollolake are organised like this :- - * - * +--------------------------------------------------------------------------+ - * | Offset | Region | Size | - * +---------------------+----------------+-----------------------------------+ - * | LP_SRAM_BASE | RO Data | SOF_LP_DATA_SIZE | - * | | Data | | - * | | BSS | | - * +---------------------+----------------+-----------------------------------+ - * | HEAP_LP_SYSTEM_BASE | System Heap | HEAP_LP_SYSTEM_SIZE | - * +---------------------+----------------+-----------------------------------+ - * | HEAP_LP_RUNTIME_BASE| Runtime Heap | HEAP_LP_RUNTIME_SIZE | - * +---------------------+----------------+-----------------------------------+ - * | HEAP_LP_BUFFER_BASE | Module Buffers | HEAP_LP_BUFFER_SIZE | - * +---------------------+----------------+-----------------------------------+ - * | SOF_LP_STACK_END | Stack | SOF_LP_STACK_SIZE | - * +---------------------+----------------+-----------------------------------+ - * | SOF_STACK_BASE | | | - * +---------------------+----------------+-----------------------------------+ - */ - -/* LP SRAM */ -#ifndef LP_SRAM_BASE -#define LP_SRAM_BASE 0xBE800000 -#endif - -/* Heap section sizes for module pool */ -#define HEAP_RT_LP_COUNT8 0 -#define HEAP_RT_LP_COUNT16 256 -#define HEAP_RT_LP_COUNT32 128 -#define HEAP_RT_LP_COUNT64 64 -#define HEAP_RT_LP_COUNT128 64 -#define HEAP_RT_LP_COUNT256 96 -#define HEAP_RT_LP_COUNT512 8 -#define HEAP_RT_LP_COUNT1024 4 - -/* Heap configuration */ -#define SOF_LP_DATA_SIZE 0x4000 - -#define HEAP_LP_SYSTEM_BASE (LP_SRAM_BASE + SOF_LP_DATA_SIZE) -#define HEAP_LP_SYSTEM_SIZE 0x1000 - -#define HEAP_LP_RUNTIME_BASE \ - (HEAP_LP_SYSTEM_BASE + HEAP_LP_SYSTEM_SIZE) -#define HEAP_LP_RUNTIME_SIZE \ - (HEAP_RT_LP_COUNT8 * 8 + HEAP_RT_LP_COUNT16 * 16 + \ - HEAP_RT_LP_COUNT32 * 32 + HEAP_RT_LP_COUNT64 * 64 + \ - HEAP_RT_LP_COUNT128 * 128 + HEAP_RT_LP_COUNT256 * 256 + \ - HEAP_RT_LP_COUNT512 * 512 + HEAP_RT_LP_COUNT1024 * 1024) - -#define HEAP_LP_BUFFER_BASE LP_SRAM_BASE -#define HEAP_LP_BUFFER_SIZE LP_SRAM_SIZE - -#define HEAP_LP_BUFFER_BLOCK_SIZE 0x180 - -#if CONFIG_LP_MEMORY_BANKS -#define HEAP_LP_BUFFER_COUNT \ - (HEAP_LP_BUFFER_SIZE / HEAP_LP_BUFFER_BLOCK_SIZE) -#else -#define HEAP_LP_BUFFER_COUNT 0 -#endif - -#define PLATFORM_HEAP_SYSTEM CONFIG_CORE_COUNT /* one per core */ -#define PLATFORM_HEAP_SYSTEM_RUNTIME CONFIG_CORE_COUNT /* one per core */ -#define PLATFORM_HEAP_RUNTIME 1 -#define PLATFORM_HEAP_RUNTIME_SHARED 1 -#define PLATFORM_HEAP_SYSTEM_SHARED 1 -#define PLATFORM_HEAP_BUFFER 2 - -/* Stack configuration */ -#define SOF_LP_STACK_SIZE 0x1000 -#define SOF_LP_STACK_BASE (LP_SRAM_BASE + LP_SRAM_SIZE) -#define SOF_LP_STACK_END (SOF_LP_STACK_BASE - SOF_LP_STACK_SIZE) - -/* Vector and literal sizes - not in core-isa.h */ -#define SOF_MEM_VECT_LIT_SIZE 0x8 -#define SOF_MEM_VECT_TEXT_SIZE 0x38 -#define SOF_MEM_VECT_SIZE (SOF_MEM_VECT_TEXT_SIZE + \ - SOF_MEM_VECT_LIT_SIZE) - -#define SOF_MEM_ERROR_TEXT_SIZE 0x180 -#define SOF_MEM_ERROR_LIT_SIZE 0x8 - -#define SOF_MEM_VECBASE \ - (HP_SRAM_VECBASE_RESET + HP_SRAM_VECBASE_OFFSET) -#define SOF_MEM_VECBASE_LIT_SIZE 0x178 - -#define SOF_MEM_RO_SIZE 0x8 - -/* VM ROM sizes */ -#define ROM_RESET_TEXT_SIZE 0x400 -#define ROM_RESET_LIT_SIZE 0x200 - -/* boot loader in IMR - APL uses manifest v1.8 and SKL/KBL use v1.5 */ -#ifndef IMR_BOOT_LDR_TEXT_ENTRY_BASE -#if CONFIG_APOLLOLAKE && !(CONFIG_KABYLAKE || CONFIG_SKYLAKE) -#define IMR_BOOT_LDR_TEXT_ENTRY_BASE 0xB000A000 -#elif CONFIG_KABYLAKE || CONFIG_SKYLAKE -#define IMR_BOOT_LDR_TEXT_ENTRY_BASE 0xBE0A0000 -#else -#error Platform not specified -#endif -#endif /* IMR_BOOT_LDR_TEXT_ENTRY_BASE */ - -#define IMR_BOOT_LDR_TEXT_ENTRY_SIZE 0x86 -#define IMR_BOOT_LDR_LIT_BASE (IMR_BOOT_LDR_TEXT_ENTRY_BASE + \ - IMR_BOOT_LDR_TEXT_ENTRY_SIZE) -#define IMR_BOOT_LDR_LIT_SIZE 0x70 -#define IMR_BOOT_LDR_TEXT_BASE (IMR_BOOT_LDR_LIT_BASE + \ - IMR_BOOT_LDR_LIT_SIZE) -#define IMR_BOOT_LDR_TEXT_SIZE 0x1C00 -#define IMR_BOOT_LDR_TEXT1_BASE (IMR_BOOT_LDR_TEXT_BASE + \ - IMR_BOOT_LDR_TEXT_SIZE) -#define IMR_BOOT_LDR_TEXT1_SIZE 0x2000 -#define IMR_BOOT_LDR_DATA_BASE 0xB0002000 -#define IMR_BOOT_LDR_DATA_SIZE 0x1000 -#define IMR_BOOT_LDR_BSS_BASE 0xB0100000 -#define IMR_BOOT_LDR_BSS_SIZE 0x10000 - -/* Temporary stack place for boot_ldr */ -#define BOOT_LDR_STACK_BASE (HP_SRAM_BASE + HP_SRAM_SIZE - \ - SOF_STACK_TOTAL_SIZE) -#define BOOT_LDR_STACK_SIZE SOF_STACK_TOTAL_SIZE - -/** \brief Manifest base address in IMR - used by boot loader copy procedure. */ -#define IMR_BOOT_LDR_MANIFEST_BASE 0xB0004000 - -/** \brief Manifest size (seems unused). */ -#define IMR_BOOT_LDR_MANIFEST_SIZE 0x6000 - -#define host_to_local(addr) (addr) -#define local_to_host(addr) (addr) - -#endif /* __PLATFORM_LIB_MEMORY_H__ */ - -#else - -#error "This file shouldn't be included from outside of sof/lib/memory.h" - -#endif /* __SOF_LIB_MEMORY_H__ */ diff --git a/src/platform/apollolake/include/platform/lib/pm_runtime.h b/src/platform/apollolake/include/platform/lib/pm_runtime.h deleted file mode 100644 index 94bfc87b43df..000000000000 --- a/src/platform/apollolake/include/platform/lib/pm_runtime.h +++ /dev/null @@ -1,27 +0,0 @@ -/* SPDX-License-Identifier: BSD-3-Clause - * - * Copyright(c) 2018 Intel Corporation. All rights reserved. - * - * Author: Tomasz Lauda - */ - -/** - * \file platform/apollolake/include/platform/lib/pm_runtime.h - * \brief Runtime power management header file for Apollolake - * \author Tomasz Lauda - */ - -#ifdef __SOF_LIB_PM_RUNTIME_H__ - -#ifndef __PLATFORM_LIB_PM_RUNTIME_H__ -#define __PLATFORM_LIB_PM_RUNTIME_H__ - -#include - -#endif /* __PLATFORM_LIB_PM_RUNTIME_H__ */ - -#else - -#error "This file shouldn't be included from outside of sof/lib/pm_runtime.h" - -#endif /* __SOF_LIB_PM_RUNTIME_H__ */ diff --git a/src/platform/apollolake/include/platform/lib/shim.h b/src/platform/apollolake/include/platform/lib/shim.h deleted file mode 100644 index de2a81bd675b..000000000000 --- a/src/platform/apollolake/include/platform/lib/shim.h +++ /dev/null @@ -1,268 +0,0 @@ -/* SPDX-License-Identifier: BSD-3-Clause - * - * Copyright(c) 2016 Intel Corporation. All rights reserved. - * - * Author: Liam Girdwood - * Keyon Jie - */ - -#ifdef __SOF_LIB_SHIM_H__ - -#ifndef __PLATFORM_LIB_SHIM_H__ -#define __PLATFORM_LIB_SHIM_H__ - -#include -#include -#include - -/* DSP IPC for Host Registers */ -#define IPC_DIPCT 0x00 -#define IPC_DIPCTE 0x04 -#define IPC_DIPCI 0x08 -#define IPC_DIPCIE 0x0c -#define IPC_DIPCCTL 0x10 - -/* DIPCT */ -#define IPC_DIPCT_BUSY BIT(31) -#define IPC_DIPCT_MSG_MASK 0x7FFFFFFF - -/* DIPCTE */ -#define IPC_DIPCTE_MSG_MASK 0x3FFFFFFF - -/* DIPCI */ -#define IPC_DIPCI_BUSY BIT(31) -#define IPC_DIPCI_MSG_MASK 0x7FFFFFFF - -/* DIPCIE */ -#define IPC_DIPCIE_DONE BIT(30) -#define IPC_DIPCIE_MSG_MASK 0x3FFFFFFF - -/* DIPCCTL */ -#define IPC_DIPCCTL_IPCIDIE BIT(1) -#define IPC_DIPCCTL_IPCTBIE BIT(0) - -#define IPC_DSP_OFFSET 0x10 - -/* DSP IPC for intra DSP communication */ -#define IPC_IDCTFC(x) (0x0 + x * IPC_DSP_OFFSET) -#define IPC_IDCTEFC(x) (0x4 + x * IPC_DSP_OFFSET) -#define IPC_IDCITC(x) (0x8 + x * IPC_DSP_OFFSET) -#define IPC_IDCIETC(x) (0xc + x * IPC_DSP_OFFSET) -#define IPC_IDCCTL 0x50 - -/* IDCTFC */ -#define IPC_IDCTFC_BUSY BIT(31) -#define IPC_IDCTFC_MSG_MASK 0x7FFFFFFF - -/* IDCTEFC */ -#define IPC_IDCTEFC_MSG_MASK 0x3FFFFFFF - -/* IDCITC */ -#define IPC_IDCITC_BUSY BIT(31) -#define IPC_IDCITC_MSG_MASK 0x7FFFFFFF - -/* IDCIETC */ -#define IPC_IDCIETC_DONE BIT(30) -#define IPC_IDCIETC_MSG_MASK 0x3FFFFFFF - -/* IDCCTL */ -#define IPC_IDCCTL_IDCIDIE(x) (0x100 << (x)) -#define IPC_IDCCTL_IDCTBIE(x) BIT(x) - -#define IRQ_CPU_OFFSET 0x40 - -#define REG_IRQ_IL2MSD(xcpu) (0x0 + (xcpu * IRQ_CPU_OFFSET)) -#define REG_IRQ_IL2MCD(xcpu) (0x4 + (xcpu * IRQ_CPU_OFFSET)) -#define REG_IRQ_IL2MD(xcpu) (0x8 + (xcpu * IRQ_CPU_OFFSET)) -#define REG_IRQ_IL2SD(xcpu) (0xc + (xcpu * IRQ_CPU_OFFSET)) - -/* all mask valid bits */ -#define REG_IRQ_IL2MD_ALL 0x03F181F0 - -#define REG_IRQ_IL3MSD(xcpu) (0x10 + (xcpu * IRQ_CPU_OFFSET)) -#define REG_IRQ_IL3MCD(xcpu) (0x14 + (xcpu * IRQ_CPU_OFFSET)) -#define REG_IRQ_IL3MD(xcpu) (0x18 + (xcpu * IRQ_CPU_OFFSET)) -#define REG_IRQ_IL3SD(xcpu) (0x1c + (xcpu * IRQ_CPU_OFFSET)) - -/* all mask valid bits */ -#define REG_IRQ_IL3MD_ALL 0x807F81FF - -#define REG_IRQ_IL4MSD(xcpu) (0x20 + (xcpu * IRQ_CPU_OFFSET)) -#define REG_IRQ_IL4MCD(xcpu) (0x24 + (xcpu * IRQ_CPU_OFFSET)) -#define REG_IRQ_IL4MD(xcpu) (0x28 + (xcpu * IRQ_CPU_OFFSET)) -#define REG_IRQ_IL4SD(xcpu) (0x2c + (xcpu * IRQ_CPU_OFFSET)) - -/* all mask valid bits */ -#define REG_IRQ_IL4MD_ALL 0x807F81FF - -#define REG_IRQ_IL5MSD(xcpu) (0x30 + (xcpu * IRQ_CPU_OFFSET)) -#define REG_IRQ_IL5MCD(xcpu) (0x34 + (xcpu * IRQ_CPU_OFFSET)) -#define REG_IRQ_IL5MD(xcpu) (0x38 + (xcpu * IRQ_CPU_OFFSET)) -#define REG_IRQ_IL5SD(xcpu) (0x3c + (xcpu * IRQ_CPU_OFFSET)) - -/* all mask valid bits */ -#define REG_IRQ_IL5MD_ALL 0xFFFFC0CF - -#define REG_IRQ_IL2RSD 0x100 -#define REG_IRQ_IL3RSD 0x104 -#define REG_IRQ_IL4RSD 0x108 -#define REG_IRQ_IL5RSD 0x10c - -#define REG_IRQ_LVL5_LP_GPDMA0_MASK (0xff << 16) -#define REG_IRQ_LVL5_LP_GPDMA1_MASK (0xff << 24) - -/* DSP Shim Registers */ -#define SHIM_DSPWC 0x20 /* DSP Wall Clock */ -#define SHIM_DSPWCL 0x20 /* DSP Wall Clock Low */ -#define SHIM_DSPWCH 0x24 /* DSP Wall Clock High */ -#define SHIM_DSPWCTCS 0x28 /* DSP Wall Clock Timer Control & Status */ -#define SHIM_DSPWCT0C 0x30 /* DSP Wall Clock Timer 0 Compare */ -#define SHIM_DSPWCT1C 0x38 /* DSP Wall Clock Timer 1 Compare */ - -#define SHIM_DSPWCTCS_T1T BIT(5) /* Timer 1 triggered */ -#define SHIM_DSPWCTCS_T0T BIT(4) /* Timer 0 triggered */ -#define SHIM_DSPWCTCS_T1A BIT(1) /* Timer 1 armed */ -#define SHIM_DSPWCTCS_T0A BIT(0) /* Timer 0 armed */ - -/** \brief Clock control */ -#define SHIM_CLKCTL 0x78 - -/** \brief Clock status */ -#define SHIM_CLKSTS 0x7C - -/** \brief Request Audio PLL Clock */ -#define SHIM_CLKCTL_RAPLLC BIT(31) - -/** \brief Request XTAL Oscillator Clock */ -#define SHIM_CLKCTL_RXOSCC BIT(30) - -/** \brief Request Fast RING Oscillator Clock */ -#define SHIM_CLKCTL_RFROSCC BIT(29) - -/** \brief LP GPDMA Force Dynamic Clock Gating bits, 0: enable */ -#define SHIM_CLKCTL_LPGPDMAFDCGB(x) BIT(26 + x) - -/** \brief DMIC Force Dynamic Clock Gating */ -#define SHIM_CLKCTL_DMICFDCGB BIT(24) - -/** \brief I2S Force Dynamic Clock Gating */ -#define SHIM_CLKCTL_I2SFDCGB(x) BIT(20 + x) - -/** \brief I2S Extension Force Dynamic Clock Gating */ -#define SHIM_CLKCTL_I2SEFDCGB(x) BIT(18 + x) - -/** \brief Tensilica Core Prevent Local Clock Gating */ -#define SHIM_CLKCTL_TCPLCG_EN(x) BIT(16 + (x)) -#define SHIM_CLKCTL_TCPLCG_DIS(x) 0 - -/** \brief Core clock PLL divisor */ -#define SHIM_CLKCTL_DPCS_MASK(x) (0x3 << (8 + x * 2)) -#define SHIM_CLKCTL_DPCS_DIV1(x) (0x0 << (8 + x * 2)) -#define SHIM_CLKCTL_DPCS_DIV2(x) (0x1 << (8 + x * 2)) -#define SHIM_CLKCTL_DPCS_DIV4(x) (0x3 << (8 + x * 2)) - -/** \brief Tensilica Core Prevent Audio PLL Shutdown */ -#define SHIM_CLKCTL_TCPAPLLS_EN BIT(7) -#define SHIM_CLKCTL_TCPAPLLS_DIS 0 - -/** \brief LP domain clock select, 0: PLL, 1: oscillator */ -#define SHIM_CLKCTL_LDCS_XTAL BIT(5) -#define SHIM_CLKCTL_LDCS_PLL 0 - -/** \brief HP domain clock select */ -#define SHIM_CLKCTL_HDCS BIT(4) -#define SHIM_CLKCTL_HDCS_XTAL BIT(4) -#define SHIM_CLKCTL_HDCS_PLL 0 - -/** \brief LP domain oscillator clock select select, 0: XTAL, 1: Fast RING */ -#define SHIM_CLKCTL_LDOCS BIT(3) - -/** \brief HP domain oscillator clock select select, 0: XTAL, 1: Fast RING */ -#define SHIM_CLKCTL_HDOCS BIT(2) - -/** \brief LP memory clock PLL divisor, 0: div by 2, 1: div by 4 */ -#define SHIM_CLKCTL_LPMPCS_DIV4 BIT(1) -#define SHIM_CLKCTL_LPMPCS_DIV2 0 - -/** \brief HP memory clock PLL divisor, 0: div by 2, 1: div by 4 */ -#define SHIM_CLKCTL_HPMPCS_DIV4 BIT(0) -#define SHIM_CLKCTL_HPMPCS_DIV2 0 - -#define SHIM_PWRCTL 0x90 -#define SHIM_PWRSTS 0x92 -#define SHIM_LPSCTL 0x94 - -/* HP & LP SRAM Power Gating */ -#define SHIM_HSPGCTL 0x80 -#define SHIM_LSPGCTL 0x84 -#define SHIM_SPSREQ 0xa0 -#define LSPGCTL (SHIM_BASE + SHIM_LSPGCTL) - -#define SHIM_SPSREQ_RVNNP BIT(0) - -/** \brief GPDMA shim registers Control */ -#define SHIM_GPDMA_BASE_OFFSET 0xC00 -#define SHIM_GPDMA_BASE(x) (SHIM_GPDMA_BASE_OFFSET + (x) * 0x80) - -/** \brief GPDMA Channel Linear Link Position Control */ -#define SHIM_GPDMA_CHLLPC(x, y) (SHIM_GPDMA_BASE(x) + (y) * 0x10) -#define SHIM_GPDMA_CHLLPC_EN BIT(5) -#define SHIM_GPDMA_CHLLPC_DHRS(x) SET_BITS(4, 0, x) - -#define SHIM_GPDMA_CHLLPL(x, y) (SHIM_GPDMA_BASE(x) + 0x18 + (y) * 0x10) -#define SHIM_GPDMA_CHLLPU(x, y) (SHIM_GPDMA_BASE(x) + 0x1c + (y) * 0x10) - -/** \brief LDO Control */ -#define SHIM_LDOCTL 0xA4 -#define SHIM_LDOCTL_HPSRAM_MASK (3 << 0) -#define SHIM_LDOCTL_LPSRAM_MASK (3 << 2) -#define SHIM_LDOCTL_HPSRAM_LDO_ON (3 << 0) -#define SHIM_LDOCTL_LPSRAM_LDO_ON (3 << 2) -#define SHIM_LDOCTL_HPSRAM_LDO_BYPASS BIT(0) -#define SHIM_LDOCTL_LPSRAM_LDO_BYPASS BIT(2) -#define SHIM_LDOCTL_HPSRAM_LDO_OFF (0 << 0) -#define SHIM_LDOCTL_LPSRAM_LDO_OFF (0 << 2) - -#define SHIM_HSPGISTS 0xb0 -#define SHIM_LSPGISTS 0xb4 -#define LSPGISTS (SHIM_BASE + SHIM_LSPGISTS) - -#define SHIM_LPSCTL_FDSPRUN BIT(9) -#define SHIM_LPSCTL_FDMARUN BIT(8) - -#define SHIM_L2_MECS (SHIM_BASE + 0xd0) - -#define SHIM_LPGPDMAC(x) (0x1110 + (2 * x)) -#define SHIM_LPGPDMAC_CTLOSEL BIT(15) -#define SHIM_LPGPDMAC_CHOSEL 0xFF - -#define SHIM_DSPIOPO 0x1118 -#define SHIM_DSPIOPO_DMICOSEL BIT(0) -#define SHIM_DSPIOPO_I2SOSEL (0x3F << 8) - -#define SHIM_GENO 0x111C -#define SHIM_GENO_SHIMOSEL BIT(0) -#define SHIM_GENO_MDIVOSEL BIT(1) -#define SHIM_GENO_DIOPTOSEL BIT(2) - -#define SHIM_L2_CACHE_CTRL (SHIM_BASE + 0x500) -#define SHIM_L2_PREF_CFG (SHIM_BASE + 0x508) -#define SHIM_L2_CACHE_PREF (SHIM_BASE + 0x510) - -#define SHIM_SVCFG 0xF4 -#define SHIM_SVCFG_FORCE_L1_EXIT BIT(1) - -/* host windows */ -#define DMWBA(x) (HOST_WIN_BASE(x) + 0x0) -#define DMWLO(x) (HOST_WIN_BASE(x) + 0x4) - -#define DMWBA_ENABLE BIT(0) -#define DMWBA_READONLY BIT(1) - -#endif /* __PLATFORM_LIB_SHIM_H__ */ - -#else - -#error "This file shouldn't be included from outside of sof/lib/shim.h" - -#endif /* __SOF_LIB_SHIM_H__ */ diff --git a/src/platform/apollolake/include/platform/platform.h b/src/platform/apollolake/include/platform/platform.h deleted file mode 100644 index 22369cbdd6a4..000000000000 --- a/src/platform/apollolake/include/platform/platform.h +++ /dev/null @@ -1,120 +0,0 @@ -/* SPDX-License-Identifier: BSD-3-Clause - * - * Copyright(c) 2016 Intel Corporation. All rights reserved. - * - * Author: Liam Girdwood - * Keyon Jie - * Xiuli Pan - */ - -#ifdef __SOF_PLATFORM_H__ - -#ifndef __PLATFORM_PLATFORM_H__ -#define __PLATFORM_PLATFORM_H__ - -#define PLATFORM_RESET_MHE_AT_BOOT 1 - -#define PLATFORM_DISABLE_L2CACHE_AT_BOOT 1 - -#if !defined(__ASSEMBLER__) && !defined(LINKER) - -#include -#include -#include -#include -#include - -struct ll_schedule_domain; -struct timer; - -/*! \def PLATFORM_DEFAULT_CLOCK - * \brief clock source for audio pipeline - * - * There are two types of clock: cpu clock which is a internal clock in - * xtensa core, and ssp clock which is provided by external HW IP. - * The choice depends on HW features on different platform - */ -#define PLATFORM_DEFAULT_CLOCK CLK_SSP - -/* Host page size */ -#define HOST_PAGE_SIZE 4096 -#define PLATFORM_PAGE_TABLE_SIZE 256 - -/* IDC Interrupt */ -#define PLATFORM_IDC_INTERRUPT IRQ_EXT_IDC_LVL2 -#define PLATFORM_IDC_INTERRUPT_NAME irq_name_level2 - -/* IPC Interrupt */ -#define PLATFORM_IPC_INTERRUPT IRQ_BIT_LVL2_HOST_IPC -#define PLATFORM_IPC_INTERRUPT_NAME irq_name_level2 - -/* pipeline IRQ */ -#define PLATFORM_SCHEDULE_IRQ IRQ_NUM_SOFTWARE2 -#define PLATFORM_SCHEDULE_IRQ_NAME NULL - -/* Platform stream capabilities */ -#define PLATFORM_MAX_CHANNELS 8 -#define PLATFORM_MAX_STREAMS 16 - -/* local buffer size of DMA tracing */ -#define DMA_TRACE_LOCAL_SIZE (HOST_PAGE_SIZE * 2) - -/* trace bytes flushed during panic */ -#define DMA_FLUSH_TRACE_SIZE (MAILBOX_TRACE_SIZE >> 2) - -/* the interval of DMA trace copying */ -#define DMA_TRACE_PERIOD 500000 - -/* - * the interval of reschedule DMA trace copying in special case like half - * fullness of local DMA trace buffer - */ -#define DMA_TRACE_RESCHEDULE_TIME 500 - -/* platform has DMA memory type */ -#define PLATFORM_MEM_HAS_DMA - -/* platform has low power memory type */ -#define PLATFORM_MEM_HAS_LP_RAM - -/* DSP default delay in cycles */ -#define PLATFORM_DEFAULT_DELAY 12 - -/* minimal L1 exit time in cycles */ -#define PLATFORM_FORCE_L1_EXIT_TIME 585 - -/* the SSP port fifo depth */ -#define SSP_FIFO_DEPTH 16 - -/* the watermark for the SSP fifo depth setting */ -#define SSP_FIFO_WATERMARK 8 - -/* minimal SSP port delay in cycles */ -#define PLATFORM_SSP_DELAY 800 - -/* Platform defined panic code */ -static inline void platform_panic(uint32_t p) -{ - mailbox_sw_reg_write(SRAM_REG_FW_STATUS, p & 0x3fffffff); - ipc_write(IPC_DIPCIE, MAILBOX_EXCEPTION_OFFSET + 2 * 0x20000); - ipc_write(IPC_DIPCI, 0x80000000 | (p & 0x3fffffff)); -} - -/** - * \brief Platform specific CPU entering idle. - * May be power-optimized using platform specific capabilities. - * @param level Interrupt level. - */ -void platform_wait_for_interrupt(int level); - -extern intptr_t _module_init_start; -extern intptr_t _module_init_end; - -#endif -#endif /* __PLATFORM_PLATFORM_H__ */ - -#else - -#error "This file shouldn't be included from outside of sof/platform.h" - -#endif /* __SOF_PLATFORM_H__ */ diff --git a/src/platform/apollolake/include/platform/trace/trace.h b/src/platform/apollolake/include/platform/trace/trace.h deleted file mode 100644 index 771a13dbfe54..000000000000 --- a/src/platform/apollolake/include/platform/trace/trace.h +++ /dev/null @@ -1,21 +0,0 @@ -/* SPDX-License-Identifier: BSD-3-Clause - * - * Copyright(c) 2019 Intel Corporation. All rights reserved. - * - * Author: Tomasz Lauda - */ - -#ifdef __SOF_TRACE_TRACE_H__ - -#ifndef __PLATFORM_TRACE_TRACE_H__ -#define __PLATFORM_TRACE_TRACE_H__ - -#include - -#endif /* __PLATFORM_TRACE_TRACE_H__ */ - -#else - -#error "This file shouldn't be included from outside of sof/trace/trace.h" - -#endif /* __SOF_TRACE_TRACE_H__ */ diff --git a/src/platform/apollolake/lib/CMakeLists.txt b/src/platform/apollolake/lib/CMakeLists.txt deleted file mode 100644 index c60199960955..000000000000 --- a/src/platform/apollolake/lib/CMakeLists.txt +++ /dev/null @@ -1,6 +0,0 @@ -# SPDX-License-Identifier: BSD-3-Clause - -add_local_sources(sof - clk.c - power_down.S -) diff --git a/src/platform/apollolake/lib/clk.c b/src/platform/apollolake/lib/clk.c deleted file mode 100644 index 54d7187c80f6..000000000000 --- a/src/platform/apollolake/lib/clk.c +++ /dev/null @@ -1,48 +0,0 @@ -// SPDX-License-Identifier: BSD-3-Clause -// -// Copyright(c) 2019 Intel Corporation. All rights reserved. -// -// Author: Tomasz Lauda -// Janusz Jankowski - -#include -#include -#include - -static const struct freq_table platform_cpu_freq[] = { - { 100000000, 100000 }, - { 200000000, 200000 }, - { CLK_MAX_CPU_HZ, 400000 }, -}; - -const uint32_t cpu_freq_enc[] = { - 0x3, - 0x1, - 0x0, -}; - -STATIC_ASSERT(NUM_CPU_FREQ == ARRAY_SIZE(platform_cpu_freq), - invalid_number_of_cpu_frequencies); - -const struct freq_table *cpu_freq = platform_cpu_freq; - -/* IMPORTANT: array should be filled in increasing order - * (regarding to .freq field) - */ -static const struct freq_table platform_ssp_freq[] = { - { 19200000, 19200 }, - { 24576000, 24576 }, - { 96000000, 96000 }, -}; - -static const uint32_t platform_ssp_freq_sources[] = { - SSP_CLOCK_XTAL_OSCILLATOR, - SSP_CLOCK_AUDIO_CARDINAL, - SSP_CLOCK_PLL_FIXED, -}; - -STATIC_ASSERT(NUM_SSP_FREQ == ARRAY_SIZE(platform_ssp_freq), - invalid_number_of_ssp_frequencies); - -const struct freq_table *ssp_freq = platform_ssp_freq; -const uint32_t *ssp_freq_sources = platform_ssp_freq_sources; diff --git a/src/platform/apollolake/lib/power_down.S b/src/platform/apollolake/lib/power_down.S deleted file mode 100644 index 1c4ef7841078..000000000000 --- a/src/platform/apollolake/lib/power_down.S +++ /dev/null @@ -1,152 +0,0 @@ -/* SPDX-License-Identifier: BSD-3-Clause - * - * Copyright(c) 2016 Intel Corporation. All rights reserved. - * - * Author: Lech Betlej - */ - -/** - * \file platform/apollolake/lib/power_down.S - * \brief Power gating memory banks - implementation specific for Apollolake - * \author Lech Betlej - */ -#include -#include -#include -#include - - .section .text, "ax" - .align 64 -literals: - .literal_position - .global power_down - .type power_down, @function -/** - * Perform power down. - * - * Depending on arguments, memories are switched off. - * A2 - argument for LPSRAM - * A3 - pointer to array containing power gating mask. - * - * Finally, core enters waiti. - */ - -#define b_enable_lpsram a2 -#define pu32_hpsram_mask a3 -#define temp_reg0 a6 -#define temp_reg1 a7 -#define temp_reg2 a8 -#define temp_reg3 a9 -#define host_base a10 -#define pfl_reg a15 - - .align 64 -power_down: - entry sp, 32 - // effectively executes: - // xthal_dcache_region_lock(&literals, 128); - // xthal_dcache_region_lock(&power_down, 384); - // xthal_dcache_region_lock(&pu32_hpsram_mask, 64); - movi pfl_reg, literals - dpfl pfl_reg, 0 - dpfl pfl_reg, 64 - - movi pfl_reg, power_down - ipfl pfl_reg, 0 - ipfl pfl_reg, 64 - ipfl pfl_reg, 128 - ipfl pfl_reg, 192 - addi pfl_reg, pfl_reg, 256 - ipfl pfl_reg, 0 - ipfl pfl_reg, 64 - - mov pfl_reg, pu32_hpsram_mask - dpfl pfl_reg, 0 - - // if b_enable_lpsram = 0 (bool disable_lpsram) - do not disable lpsram. - beqz b_enable_lpsram, _PD_DISABLE_HPSRAM - -_PD_DISABLE_LPSRAM: - movi host_base, IPC_HOST_BASE - - movi temp_reg0, SHIM_LDOCTL_LPSRAM_LDO_ON - m_cavs_set_lpldo_state temp_reg0, temp_reg1, temp_reg2 - - m_cavs_lpsram_power_off temp_reg0, temp_reg1, temp_reg2 - - movi temp_reg0, SHIM_LDOCTL_LPSRAM_LDO_OFF - m_cavs_set_lpldo_state temp_reg0, temp_reg1, temp_reg2 - - // DISABLE_HPSRAM is aligned so there can be zeros between - //it and last instr. - j _PD_DISABLE_HPSRAM - - // workaround for incidental gnu assembler bug - no alignment here - // (see comment before IPFL) ... - // .align 64 -_PD_DISABLE_HPSRAM: - // if value in memory pointed by pu32_hpsram_mask = 0 - // (hpsram_pwrgating_mask) - do not disable hpsram. - l32i temp_reg0, pu32_hpsram_mask, 0 - beqz temp_reg0, _PD_SLEEP - - movi temp_reg0, SHIM_LDOCTL_HPSRAM_LDO_ON - m_cavs_set_hpldo_state temp_reg0, temp_reg1, temp_reg2 - // Disable L2 cache in case it would be enabled - - m_cavs_hpsram_power_off temp_reg0, temp_reg1, temp_reg2 - - movi temp_reg0, SHIM_LDOCTL_HPSRAM_LDO_OFF - m_cavs_set_hpldo_state temp_reg0, temp_reg1, temp_reg2 - - // For BXT-P we need to deassert VNN request and select slow XTAL - // as clock source - // APL specific code _PD_SWITCH_TO_XTAL_CLOCK: and _PD_RELEASE_VNN -_PD_SWITCH_TO_XTAL_CLOCK: - // TODO: move to CLOCK hal macros - movi temp_reg0, (SHIM_BASE + SHIM_CLKCTL) - movi temp_reg1, ~(SHIM_CLKCTL_HDOCS | SHIM_CLKCTL_LDOCS) - movi temp_reg2, (SHIM_CLKCTL_LDCS_XTAL | SHIM_CLKCTL_HDCS_XTAL) - l32i temp_reg3, temp_reg0, 0 - // Reset LDOCS & HDOCS bits to select XTAL - and temp_reg3, temp_reg3, temp_reg1 - // Set LDCS & HDCS so clock selection depends on LDOCS & HDOCS - or temp_reg3, temp_reg3, temp_reg2 - s32i temp_reg3, temp_reg0, 0 - -_PD_RELEASE_VNN: - // TODO: move to VNN/SHIM hal macros - movi temp_reg0, (SHIM_BASE + SHIM_SPSREQ) - movi temp_reg1, ~SHIM_SPSREQ_RVNNP - l32i temp_reg2, temp_reg0, 0 - and temp_reg2, temp_reg2, temp_reg1 - s32i temp_reg2, temp_reg0, 0 - l32i temp_reg2, temp_reg0, 0 - // We cannot wait for VNN to drop since it can be held by something else - // and never drop - -_PD_SEND_IPC: - // Send IPC to host informing of PD completion - Clear BUSY bit by - // writting IPC_DIPCT_BUSY to IPC_DIPCT - l32i temp_reg1, host_base, IPC_DIPCT - movi temp_reg2, IPC_DIPCT_BUSY - or temp_reg1, temp_reg1, temp_reg2 - s32i temp_reg1, host_base, IPC_DIPCT - -_PD_SLEEP: - // effecfively executes: - // xmp_spin() - // waiti 5 - movi temp_reg0, 128 -loop: - addi temp_reg0, temp_reg0, -1 - bnez temp_reg0, loop - - extw - extw - waiti 5 - j _PD_SLEEP - - .size power_down , . - power_down - - diff --git a/src/platform/apollolake/rom.x.in b/src/platform/apollolake/rom.x.in deleted file mode 100644 index 890814718202..000000000000 --- a/src/platform/apollolake/rom.x.in +++ /dev/null @@ -1,347 +0,0 @@ -/* - * Linker Script for Apollolake Bootloader. - * - * This script is run through the GNU C preprocessor to align the memory - * offsets with headers. - * - * Use spaces for formatting as cpp ignore tab sizes. - */ - - -#include -#include - -OUTPUT_ARCH(xtensa) - -MEMORY -{ - vector_reset_text : - org = ROM_BASE, - len = ROM_RESET_TEXT_SIZE - vector_reset_lit : - org = ROM_BASE + ROM_RESET_TEXT_SIZE, - len = ROM_RESET_LIT_SIZE - vector_base_text : - org = ROM_BASE + ROM_RESET_TEXT_SIZE + ROM_RESET_LIT_SIZE, - len = SOF_MEM_VECBASE_LIT_SIZE - vector_int2_lit : - org = ROM_BASE + XCHAL_INTLEVEL2_VECOFS - SOF_MEM_VECT_LIT_SIZE, - len = SOF_MEM_VECT_LIT_SIZE - vector_int2_text : - org = ROM_BASE + XCHAL_INTLEVEL2_VECOFS, - len = SOF_MEM_VECT_TEXT_SIZE - vector_int3_lit : - org = ROM_BASE + XCHAL_INTLEVEL3_VECOFS - SOF_MEM_VECT_LIT_SIZE, - len = SOF_MEM_VECT_LIT_SIZE - vector_int3_text : - org = ROM_BASE + XCHAL_INTLEVEL3_VECOFS, - len = SOF_MEM_VECT_TEXT_SIZE - vector_int4_lit : - org = ROM_BASE + XCHAL_INTLEVEL4_VECOFS - SOF_MEM_VECT_LIT_SIZE, - len = SOF_MEM_VECT_LIT_SIZE - vector_int4_text : - org = ROM_BASE + XCHAL_INTLEVEL4_VECOFS, - len = SOF_MEM_VECT_TEXT_SIZE - vector_int5_lit : - org = ROM_BASE + XCHAL_INTLEVEL5_VECOFS - SOF_MEM_VECT_LIT_SIZE, - len = SOF_MEM_VECT_LIT_SIZE - vector_int5_text : - org = ROM_BASE + XCHAL_INTLEVEL5_VECOFS, - len = SOF_MEM_VECT_TEXT_SIZE - vector_int6_lit : - org = ROM_BASE + XCHAL_INTLEVEL6_VECOFS - SOF_MEM_VECT_LIT_SIZE, - len = SOF_MEM_VECT_LIT_SIZE - vector_int6_text : - org = ROM_BASE + XCHAL_INTLEVEL6_VECOFS, - len = SOF_MEM_VECT_TEXT_SIZE - vector_int7_lit : - org = ROM_BASE + XCHAL_INTLEVEL7_VECOFS - SOF_MEM_VECT_LIT_SIZE, - len = SOF_MEM_VECT_LIT_SIZE - vector_int7_text : - org = ROM_BASE + XCHAL_INTLEVEL7_VECOFS, - len = SOF_MEM_VECT_TEXT_SIZE - vector_kernel_lit : - org = ROM_BASE + XCHAL_KERNEL_VECOFS - SOF_MEM_VECT_LIT_SIZE, - len = SOF_MEM_VECT_LIT_SIZE - vector_kernel_text : - org = ROM_BASE + XCHAL_KERNEL_VECOFS, - len = SOF_MEM_VECT_TEXT_SIZE - vector_user_lit : - org = ROM_BASE + XCHAL_USER_VECOFS - SOF_MEM_VECT_LIT_SIZE, - len = SOF_MEM_VECT_LIT_SIZE - vector_user_text : - org = ROM_BASE + XCHAL_USER_VECOFS, - len = SOF_MEM_VECT_TEXT_SIZE - vector_double_lit : - org = ROM_BASE + XCHAL_DOUBLEEXC_VECOFS - SOF_MEM_VECT_LIT_SIZE, - len = SOF_MEM_VECT_LIT_SIZE - vector_double_text : - org = ROM_BASE + XCHAL_DOUBLEEXC_VECOFS, - len = SOF_MEM_VECT_TEXT_SIZE - sof_text : - org = ROM_BASE + 0x800, - len = ROM_SIZE, - sof_stack : - org = BOOT_LDR_STACK_BASE, - len = BOOT_LDR_STACK_SIZE -} - -PHDRS -{ - vector_reset_text_phdr PT_LOAD; - vector_reset_lit_phdr PT_LOAD; - vector_base_text_phdr PT_LOAD; - vector_int2_lit_phdr PT_LOAD; - vector_int2_text_phdr PT_LOAD; - vector_int3_lit_phdr PT_LOAD; - vector_int3_text_phdr PT_LOAD; - vector_int4_lit_phdr PT_LOAD; - vector_int4_text_phdr PT_LOAD; - vector_int5_lit_phdr PT_LOAD; - vector_int5_text_phdr PT_LOAD; - vector_int6_lit_phdr PT_LOAD; - vector_int6_text_phdr PT_LOAD; - vector_int7_lit_phdr PT_LOAD; - vector_int7_text_phdr PT_LOAD; - vector_kernel_lit_phdr PT_LOAD; - vector_kernel_text_phdr PT_LOAD; - vector_user_lit_phdr PT_LOAD; - vector_user_text_phdr PT_LOAD; - vector_double_lit_phdr PT_LOAD; - vector_double_text_phdr PT_LOAD; - sof_text_phdr PT_LOAD; - sof_stack_phdr PT_LOAD; -} - -_rom_store_table = 0; - -/* ABI0 does not use Window base */ -PROVIDE(_memmap_vecbase_reset = ROM_BASE); - -/* Various memory-map dependent cache attribute settings: */ -_memmap_cacheattr_wbna_trapnull = 0xFF42FFF2; -PROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_wbna_trapnull); - -SECTIONS -{ - .ResetVector.text : ALIGN(4) - { - _ResetVector_text_start = ABSOLUTE(.); - KEEP (*(.ResetVector.text)) - _ResetVector_text_end = ABSOLUTE(.); - } >vector_reset_text :vector_reset_text_phdr - - .ResetVector.literal : ALIGN(4) - { - _ResetVector_literal_start = ABSOLUTE(.); - *(.ResetVector.literal) - _ResetVector_literal_end = ABSOLUTE(.); - } >vector_reset_lit :vector_reset_lit_phdr - - .WindowVectors.text : ALIGN(4) - { - _WindowVectors_text_start = ABSOLUTE(.); - KEEP (*(.WindowVectors.text)) - _WindowVectors_text_end = ABSOLUTE(.); - } >vector_base_text :vector_base_text_phdr - - .Level2InterruptVector.literal : ALIGN(4) - { - _Level2InterruptVector_literal_start = ABSOLUTE(.); - *(.Level2InterruptVector.literal) - _Level2InterruptVector_literal_end = ABSOLUTE(.); - } >vector_int2_lit :vector_int2_lit_phdr - - .Level2InterruptVector.text : ALIGN(4) - { - _Level2InterruptVector_text_start = ABSOLUTE(.); - KEEP (*(.Level2InterruptVector.text)) - _Level2InterruptVector_text_end = ABSOLUTE(.); - } >vector_int2_text :vector_int2_text_phdr - - .Level3InterruptVector.literal : ALIGN(4) - { - _Level3InterruptVector_literal_start = ABSOLUTE(.); - *(.Level3InterruptVector.literal) - _Level3InterruptVector_literal_end = ABSOLUTE(.); - } >vector_int3_lit :vector_int3_lit_phdr - - .Level3InterruptVector.text : ALIGN(4) - { - _Level3InterruptVector_text_start = ABSOLUTE(.); - KEEP (*(.Level3InterruptVector.text)) - _Level3InterruptVector_text_end = ABSOLUTE(.); - } >vector_int3_text :vector_int3_text_phdr - - .Level4InterruptVector.literal : ALIGN(4) - { - _Level4InterruptVector_literal_start = ABSOLUTE(.); - *(.Level4InterruptVector.literal) - _Level4InterruptVector_literal_end = ABSOLUTE(.); - } >vector_int4_lit :vector_int4_lit_phdr - - .Level4InterruptVector.text : ALIGN(4) - { - _Level4InterruptVector_text_start = ABSOLUTE(.); - KEEP (*(.Level4InterruptVector.text)) - _Level4InterruptVector_text_end = ABSOLUTE(.); - } >vector_int4_text :vector_int4_text_phdr - - .Level5InterruptVector.literal : ALIGN(4) - { - _Level5InterruptVector_literal_start = ABSOLUTE(.); - *(.Level5InterruptVector.literal) - _Level5InterruptVector_literal_end = ABSOLUTE(.); - } >vector_int5_lit :vector_int5_lit_phdr - - .Level5InterruptVector.text : ALIGN(4) - { - _Level5InterruptVector_text_start = ABSOLUTE(.); - KEEP (*(.Level5InterruptVector.text)) - _Level5InterruptVector_text_end = ABSOLUTE(.); - } >vector_int5_text :vector_int5_text_phdr - - .DebugExceptionVector.literal : ALIGN(4) - { - _DebugExceptionVector_literal_start = ABSOLUTE(.); - *(.DebugExceptionVector.literal) - _DebugExceptionVector_literal_end = ABSOLUTE(.); - } >vector_int6_lit :vector_int6_lit_phdr - - .DebugExceptionVector.text : ALIGN(4) - { - _DebugExceptionVector_text_start = ABSOLUTE(.); - KEEP (*(.DebugExceptionVector.text)) - _DebugExceptionVector_text_end = ABSOLUTE(.); - } >vector_int6_text :vector_int6_text_phdr - - .NMIExceptionVector.literal : ALIGN(4) - { - _NMIExceptionVector_literal_start = ABSOLUTE(.); - *(.NMIExceptionVector.literal) - _NMIExceptionVector_literal_end = ABSOLUTE(.); - } >vector_int7_lit :vector_int7_lit_phdr - - .NMIExceptionVector.text : ALIGN(4) - { - _NMIExceptionVector_text_start = ABSOLUTE(.); - KEEP (*(.NMIExceptionVector.text)) - _NMIExceptionVector_text_end = ABSOLUTE(.); - } >vector_int7_text :vector_int7_text_phdr - - .KernelExceptionVector.literal : ALIGN(4) - { - _KernelExceptionVector_literal_start = ABSOLUTE(.); - *(.KernelExceptionVector.literal) - _KernelExceptionVector_literal_end = ABSOLUTE(.); - } >vector_kernel_lit :vector_kernel_lit_phdr - - .KernelExceptionVector.text : ALIGN(4) - { - _KernelExceptionVector_text_start = ABSOLUTE(.); - KEEP (*(.KernelExceptionVector.text)) - _KernelExceptionVector_text_end = ABSOLUTE(.); - } >vector_kernel_text :vector_kernel_text_phdr - - .UserExceptionVector.literal : ALIGN(4) - { - _UserExceptionVector_literal_start = ABSOLUTE(.); - *(.UserExceptionVector.literal) - _UserExceptionVector_literal_end = ABSOLUTE(.); - } >vector_user_lit :vector_user_lit_phdr - - .UserExceptionVector.text : ALIGN(4) - { - _UserExceptionVector_text_start = ABSOLUTE(.); - KEEP (*(.UserExceptionVector.text)) - _UserExceptionVector_text_end = ABSOLUTE(.); - } >vector_user_text :vector_user_text_phdr - - .DoubleExceptionVector.literal : ALIGN(4) - { - _DoubleExceptionVector_literal_start = ABSOLUTE(.); - *(.DoubleExceptionVector.literal) - _DoubleExceptionVector_literal_end = ABSOLUTE(.); - } >vector_double_lit :vector_double_lit_phdr - - .DoubleExceptionVector.text : ALIGN(4) - { - _DoubleExceptionVector_text_start = ABSOLUTE(.); - KEEP (*(.DoubleExceptionVector.text)) - _DoubleExceptionVector_text_end = ABSOLUTE(.); - } >vector_double_text :vector_double_text_phdr - - .text : ALIGN(4) - { - _stext = .; - _text_start = ABSOLUTE(.); - KEEP (*(.MainEntry.text)) - *(.entry.text) - *(.init.literal) - KEEP(*(.init)) - *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*) - *(.fini.literal) - KEEP(*(.fini)) - *(.gnu.version) - _text_end = ABSOLUTE(.); - _etext = .; - } >sof_text :sof_text_phdr - - /* stack */ - _end = BOOT_LDR_STACK_BASE; - PROVIDE(end = BOOT_LDR_STACK_BASE); - _stack_sentry = BOOT_LDR_STACK_BASE; - __stack = BOOT_LDR_STACK_BASE + BOOT_LDR_STACK_SIZE; - - .debug 0 : { *(.debug) } - .line 0 : { *(.line) } - .debug_srcinfo 0 : { *(.debug_srcinfo) } - .debug_sfnames 0 : { *(.debug_sfnames) } - .debug_aranges 0 : { *(.debug_aranges) } - .debug_pubnames 0 : { *(.debug_pubnames) } - .debug_info 0 : { *(.debug_info) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_line 0 : { *(.debug_line) } - .debug_frame 0 : { *(.debug_frame) } - .debug_str 0 : { *(.debug_str) } - .debug_loc 0 : { *(.debug_loc) } - .debug_macinfo 0 : { *(.debug_macinfo) } - .debug_weaknames 0 : { *(.debug_weaknames) } - .debug_funcnames 0 : { *(.debug_funcnames) } - .debug_typenames 0 : { *(.debug_typenames) } - .debug_varnames 0 : { *(.debug_varnames) } - - .xt.insn 0 : - { - KEEP (*(.xt.insn)) - KEEP (*(.gnu.linkonce.x.*)) - } - .xt.prop 0 : - { - KEEP (*(.xt.prop)) - KEEP (*(.xt.prop.*)) - KEEP (*(.gnu.linkonce.prop.*)) - } - .xt.lit 0 : - { - KEEP (*(.xt.lit)) - KEEP (*(.xt.lit.*)) - KEEP (*(.gnu.linkonce.p.*)) - } - .xt.profile_range 0 : - { - KEEP (*(.xt.profile_range)) - KEEP (*(.gnu.linkonce.profile_range.*)) - } - .xt.profile_ranges 0 : - { - KEEP (*(.xt.profile_ranges)) - KEEP (*(.gnu.linkonce.xt.profile_ranges.*)) - } - .xt.profile_files 0 : - { - KEEP (*(.xt.profile_files)) - KEEP (*(.gnu.linkonce.xt.profile_files.*)) - } -} - diff --git a/src/platform/cannonlake/rom.x.in b/src/platform/cannonlake/rom.x.in index 890814718202..54b20f163c48 100644 --- a/src/platform/cannonlake/rom.x.in +++ b/src/platform/cannonlake/rom.x.in @@ -1,5 +1,5 @@ /* - * Linker Script for Apollolake Bootloader. + * Linker Script for Cannonlake Bootloader. * * This script is run through the GNU C preprocessor to align the memory * offsets with headers. diff --git a/src/platform/icelake/rom.x.in b/src/platform/icelake/rom.x.in index 890814718202..8bbe59672e4e 100644 --- a/src/platform/icelake/rom.x.in +++ b/src/platform/icelake/rom.x.in @@ -1,5 +1,5 @@ /* - * Linker Script for Apollolake Bootloader. + * Linker Script for Icelake Bootloader. * * This script is run through the GNU C preprocessor to align the memory * offsets with headers. diff --git a/src/platform/intel/cavs/include/cavs/lib/asm_memory_management.h b/src/platform/intel/cavs/include/cavs/lib/asm_memory_management.h index 0066260e2681..804539402a76 100644 --- a/src/platform/intel/cavs/include/cavs/lib/asm_memory_management.h +++ b/src/platform/intel/cavs/include/cavs/lib/asm_memory_management.h @@ -25,7 +25,6 @@ #include #include -#if CAVS_VERSION >= CAVS_VERSION_1_8 /** * Macro powers down entire HPSRAM. On entry literals and code for section from * where this code is executed need to be placed in memory which is not @@ -79,5 +78,4 @@ bnez \ax, 1b .endm -#endif /* CAVS_VERSION == CAVS_VERSION_1_8 */ #endif /* __CAVS_LIB_ASM_MEMORY_MANAGEMENT_H__ */ diff --git a/src/platform/intel/cavs/include/cavs/lib/pm_memory.h b/src/platform/intel/cavs/include/cavs/lib/pm_memory.h index 74196c431f99..34c1d7618ca3 100644 --- a/src/platform/intel/cavs/include/cavs/lib/pm_memory.h +++ b/src/platform/intel/cavs/include/cavs/lib/pm_memory.h @@ -29,8 +29,6 @@ #define MEMORY_POWER_CHANGE_DELAY 256 #define MEMORY_POWER_CHANGE_TIMEOUT (256 * MEMORY_POWER_CHANGE_DELAY) -#if CAVS_VERSION >= CAVS_VERSION_1_8 - /** * \brief Retrieves register mask for given segment. * \param[in] start_bank Start bank id. @@ -122,8 +120,6 @@ static inline void cavs_pm_memory_hp_sram_banks_power_gate( */ void cavs_pm_memory_hp_sram_power_gate(void *ptr, uint32_t size, bool enabled); -#endif /* CAVS_VERSION >= CAVS_VERSION_1_8 */ - #if CONFIG_LP_SRAM /** diff --git a/src/platform/intel/cavs/include/cavs/version.h b/src/platform/intel/cavs/include/cavs/version.h index 6f06d7802a31..6a3c6c56907f 100644 --- a/src/platform/intel/cavs/include/cavs/version.h +++ b/src/platform/intel/cavs/include/cavs/version.h @@ -8,15 +8,12 @@ #ifndef __CAVS_VERSION_H__ #define __CAVS_VERSION_H__ -#define CAVS_VERSION_1_5 0x10500 #define CAVS_VERSION_1_8 0x10800 #define CAVS_VERSION_2_0 0x20000 #define CAVS_VERSION_2_5 0x20500 /* CAVS version defined by CONFIG_CAVS_VER_*/ -#if CONFIG_CAVS_VERSION_1_5 -#define CAVS_VERSION CAVS_VERSION_1_5 -#elif CONFIG_CAVS_VERSION_1_8 +#if CONFIG_CAVS_VERSION_1_8 #define CAVS_VERSION CAVS_VERSION_1_8 #elif CONFIG_CAVS_VERSION_2_0 #define CAVS_VERSION CAVS_VERSION_2_0 diff --git a/src/platform/intel/cavs/lib/clk.c b/src/platform/intel/cavs/lib/clk.c index 6c8258a7c862..8132f49fbe3b 100644 --- a/src/platform/intel/cavs/lib/clk.c +++ b/src/platform/intel/cavs/lib/clk.c @@ -17,17 +17,6 @@ static SHARED_DATA struct clock_info platform_clocks_info[NUM_CLOCKS]; -#if CAVS_VERSION == CAVS_VERSION_1_5 -static inline void select_cpu_clock_hw(int freq_idx, bool release_unused) -{ - uint32_t enc = cpu_freq_enc[freq_idx]; - - io_reg_update_bits(SHIM_BASE + SHIM_CLKCTL, SHIM_CLKCTL_HDCS, 0); - io_reg_update_bits(SHIM_BASE + SHIM_CLKCTL, - SHIM_CLKCTL_DPCS_MASK(cpu_get_id()), - enc); -} -#else static inline void select_cpu_clock_hw(int freq_idx, bool release_unused) { uint32_t enc = cpu_freq_enc[freq_idx]; @@ -74,7 +63,6 @@ static inline void select_cpu_clock_hw(int freq_idx, bool release_unused) } #endif } -#endif static inline void select_cpu_clock(int freq_idx, bool release_unused) { diff --git a/src/platform/intel/cavs/lib/dma.c b/src/platform/intel/cavs/lib/dma.c index abeab816ea86..40e36573642d 100644 --- a/src/platform/intel/cavs/lib/dma.c +++ b/src/platform/intel/cavs/lib/dma.c @@ -19,14 +19,7 @@ #include #endif -#if CONFIG_APOLLOLAKE -#define DMAC0_CLASS 1 -#define DMAC1_CLASS 2 -#define DMAC_HOST_IN_CHANNELS_COUNT 7 -#define DMAC_HOST_OUT_CHANNELS_COUNT 6 -#define DMAC_LINK_IN_CHANNELS_COUNT 7 -#define DMAC_LINK_OUT_CHANNELS_COUNT 6 -#elif CONFIG_CANNONLAKE || CONFIG_ICELAKE || CONFIG_TIGERLAKE +#if CONFIG_CANNONLAKE || CONFIG_ICELAKE || CONFIG_TIGERLAKE #define DMAC0_CLASS 6 #define DMAC1_CLASS 7 #define DMAC_HOST_IN_CHANNELS_COUNT 7 diff --git a/src/platform/intel/cavs/lib/pm_memory.c b/src/platform/intel/cavs/lib/pm_memory.c index d4d61e17097a..7f9dba10b95c 100644 --- a/src/platform/intel/cavs/lib/pm_memory.c +++ b/src/platform/intel/cavs/lib/pm_memory.c @@ -24,7 +24,6 @@ DECLARE_SOF_UUID("pm-memory", pm_mem_uuid, 0x14f25ab6, 0x3a4b, 0x4e5d, DECLARE_TR_CTX(pm_mem_tr, SOF_UUID(pm_mem_uuid), LOG_LEVEL_INFO); -#if (CAVS_VERSION >= CAVS_VERSION_1_8) || CONFIG_LP_SRAM /** * \brief Retrieves memory banks based on start and end pointer. * \param[in,out] start Start address of memory range. @@ -58,9 +57,6 @@ static void memory_banks_get(void *start, void *end, uint32_t base, */ *end_bank = ((uintptr_t)end - base) / SRAM_BANK_SIZE - 1; } -#endif - -#if CAVS_VERSION >= CAVS_VERSION_1_8 void cavs_pm_memory_hp_sram_power_gate(void *ptr, uint32_t size, bool enabled) { @@ -73,8 +69,6 @@ void cavs_pm_memory_hp_sram_power_gate(void *ptr, uint32_t size, bool enabled) cavs_pm_memory_hp_sram_banks_power_gate(start_bank, end_bank, enabled); } -#endif /* CAVS_VERSION >= CAVS_VERSION_1_8 */ - #if CONFIG_LP_SRAM void cavs_pm_memory_lp_sram_power_gate(void *ptr, uint32_t size, bool enabled) diff --git a/src/platform/intel/cavs/lib/pm_runtime.c b/src/platform/intel/cavs/lib/pm_runtime.c index 20a729b9c46f..e15f9a97ca96 100644 --- a/src/platform/intel/cavs/lib/pm_runtime.c +++ b/src/platform/intel/cavs/lib/pm_runtime.c @@ -7,7 +7,7 @@ /** * \file - * \brief Runtime power management implementation for Apollolake, Cannonlake + * \brief Runtime power management implementation for Cannonlake * and Icelake * \author Tomasz Lauda */ @@ -29,9 +29,7 @@ #include #include #include -#if CAVS_VERSION >= CAVS_VERSION_1_8 #include -#endif #include #include @@ -142,40 +140,6 @@ static inline bool cavs_pm_runtime_is_active_dsp(void) } #if CONFIG_INTEL_SSP -static inline void cavs_pm_runtime_dis_ssp_clk_gating(uint32_t index) -{ -#if CONFIG_APOLLOLAKE - uint32_t shim_reg; - - shim_reg = shim_read(SHIM_CLKCTL) | - (index < DAI_NUM_SSP_BASE ? - SHIM_CLKCTL_I2SFDCGB(index) : - SHIM_CLKCTL_I2SEFDCGB(index - DAI_NUM_SSP_BASE)); - - shim_write(SHIM_CLKCTL, shim_reg); - - tr_info(&power_tr, "dis-ssp-clk-gating index %d CLKCTL %08x", - index, shim_reg); -#endif -} - -static inline void cavs_pm_runtime_en_ssp_clk_gating(uint32_t index) -{ -#if CONFIG_APOLLOLAKE - uint32_t shim_reg; - - shim_reg = shim_read(SHIM_CLKCTL) & - ~(index < DAI_NUM_SSP_BASE ? - SHIM_CLKCTL_I2SFDCGB(index) : - SHIM_CLKCTL_I2SEFDCGB(index - DAI_NUM_SSP_BASE)); - - shim_write(SHIM_CLKCTL, shim_reg); - - tr_info(&power_tr, "en-ssp-clk-gating index %d CLKCTL %08x", - index, shim_reg); -#endif -} - static inline void cavs_pm_runtime_en_ssp_power(uint32_t index) { #if CONFIG_TIGERLAKE @@ -216,7 +180,7 @@ static inline void cavs_pm_runtime_dis_ssp_power(uint32_t index) #if CONFIG_INTEL_DMIC static inline void cavs_pm_runtime_dis_dmic_clk_gating(uint32_t index) { -#if CONFIG_APOLLOLAKE || CONFIG_CANNONLAKE +#if CONFIG_CANNONLAKE (void)index; uint32_t shim_reg; @@ -236,7 +200,7 @@ static inline void cavs_pm_runtime_dis_dmic_clk_gating(uint32_t index) static inline void cavs_pm_runtime_en_dmic_clk_gating(uint32_t index) { -#if CONFIG_APOLLOLAKE || CONFIG_CANNONLAKE +#if CONFIG_CANNONLAKE (void)index; uint32_t shim_reg; @@ -275,16 +239,7 @@ static inline void cavs_pm_runtime_dis_dmic_power(uint32_t index) static inline void cavs_pm_runtime_dis_dwdma_clk_gating(uint32_t index) { -#if CONFIG_APOLLOLAKE - uint32_t shim_reg; - - shim_reg = shim_read(SHIM_CLKCTL) | SHIM_CLKCTL_LPGPDMAFDCGB(index); - - shim_write(SHIM_CLKCTL, shim_reg); - - tr_info(&power_tr, "dis-dwdma-clk-gating index %d CLKCTL %08x", index, - shim_reg); -#elif CONFIG_CANNONLAKE +#if CONFIG_CANNONLAKE uint32_t shim_reg; shim_reg = shim_read(SHIM_GPDMA_CLKCTL(index)) | @@ -299,16 +254,7 @@ static inline void cavs_pm_runtime_dis_dwdma_clk_gating(uint32_t index) static inline void cavs_pm_runtime_en_dwdma_clk_gating(uint32_t index) { -#if CONFIG_APOLLOLAKE - uint32_t shim_reg; - - shim_reg = shim_read(SHIM_CLKCTL) & ~SHIM_CLKCTL_LPGPDMAFDCGB(index); - - shim_write(SHIM_CLKCTL, shim_reg); - - tr_info(&power_tr, "en-dwdma-clk-gating index %d CLKCTL %08x", index, - shim_reg); -#elif CONFIG_CANNONLAKE +#if CONFIG_CANNONLAKE uint32_t shim_reg; shim_reg = shim_read(SHIM_GPDMA_CLKCTL(index)) & @@ -335,7 +281,6 @@ static inline void cavs_pm_runtime_core_en_memory(uint32_t index) static inline void cavs_pm_runtime_core_dis_memory(uint32_t index) { -#if CAVS_VERSION >= CAVS_VERSION_1_8 void *core_memory_ptr; extern uintptr_t _sof_core_s_start; @@ -347,13 +292,10 @@ static inline void cavs_pm_runtime_core_dis_memory(uint32_t index) cavs_pm_memory_hp_sram_power_gate(core_memory_ptr, SOF_CORE_S_SIZE, false); - -#endif } static inline void cavs_pm_runtime_core_en_memory(uint32_t index) { -#if CAVS_VERSION >= CAVS_VERSION_1_8 void *core_memory_ptr; extern uintptr_t _sof_core_s_start; @@ -365,8 +307,6 @@ static inline void cavs_pm_runtime_core_en_memory(uint32_t index) cavs_pm_memory_hp_sram_power_gate(core_memory_ptr, SOF_CORE_S_SIZE, true); - -#endif } #endif @@ -407,7 +347,6 @@ static inline void cavs_pm_runtime_core_en_hp_clk(uint32_t index) static inline void cavs_pm_runtime_dis_dsp_pg(uint32_t index) { -#if CAVS_VERSION >= CAVS_VERSION_1_8 struct pm_runtime_data *prd = pm_runtime_data_get(); struct cavs_pm_runtime_data *pprd = prd->platform_data; uint32_t lps_ctl, tries = PLATFORM_PM_RUNTIME_DSP_TRIES; @@ -451,12 +390,10 @@ static inline void cavs_pm_runtime_dis_dsp_pg(uint32_t index) index); pprd->dsp_client_bitmap[index] |= flag; } -#endif } static inline void cavs_pm_runtime_en_dsp_pg(uint32_t index) { -#if CAVS_VERSION >= CAVS_VERSION_1_8 struct pm_runtime_data *prd = pm_runtime_data_get(); struct cavs_pm_runtime_data *pprd = prd->platform_data; uint32_t lps_ctl; @@ -482,7 +419,6 @@ static inline void cavs_pm_runtime_en_dsp_pg(uint32_t index) shim_write16(SHIM_PWRCTL, shim_read16(SHIM_PWRCTL) & ~SHIM_PWRCTL_TCPDSPPG(index)); } -#endif } void platform_pm_runtime_init(struct pm_runtime_data *prd) @@ -503,7 +439,6 @@ void platform_pm_runtime_get(enum pm_runtime_context context, uint32_t index, break; #if CONFIG_INTEL_SSP case SSP_CLK: - cavs_pm_runtime_dis_ssp_clk_gating(index); break; case SSP_POW: cavs_pm_runtime_en_ssp_power(index); @@ -543,7 +478,6 @@ void platform_pm_runtime_put(enum pm_runtime_context context, uint32_t index, break; #if CONFIG_INTEL_SSP case SSP_CLK: - cavs_pm_runtime_en_ssp_clk_gating(index); break; case SSP_POW: cavs_pm_runtime_dis_ssp_power(index); @@ -645,7 +579,6 @@ bool platform_pm_runtime_is_active(uint32_t context, uint32_t index) void platform_pm_runtime_power_off(void) { uint32_t hpsram_mask[PLATFORM_HPSRAM_SEGMENTS], i; -#if CAVS_VERSION >= CAVS_VERSION_1_8 int ret; /* check if DSP is busy sending IPC for 2ms */ @@ -655,7 +588,7 @@ void platform_pm_runtime_power_off(void) /* did command succeed */ if (ret < 0) tr_err(&power_tr, "failed to wait for DSP sent IPC handled."); -#endif + /* power down entire HPSRAM */ for (i = 0; i < PLATFORM_HPSRAM_SEGMENTS; i++) hpsram_mask[i] = HPSRAM_MASK(i); diff --git a/src/platform/intel/cavs/lib/power_down.S b/src/platform/intel/cavs/lib/power_down.S index 8bdd01e842fc..3afa8bca9fda 100644 --- a/src/platform/intel/cavs/lib/power_down.S +++ b/src/platform/intel/cavs/lib/power_down.S @@ -20,8 +20,6 @@ #include #include -#if CAVS_VERSION >= CAVS_VERSION_1_8 - .section .text, "ax" .align 64 power_down_literals: @@ -187,6 +185,3 @@ loop: j 1b .size power_down , . - power_down - -#endif /* CAVS_VERSION >= CAVS_VERSION_1_8 */ - diff --git a/src/platform/intel/cavs/platform.c b/src/platform/intel/cavs/platform.c index c6c8be88713f..df68c03a6331 100644 --- a/src/platform/intel/cavs/platform.c +++ b/src/platform/intel/cavs/platform.c @@ -316,28 +316,17 @@ int platform_boot_complete(uint32_t boot_message) /* tell host we are ready */ #if CONFIG_IPC_MAJOR_3 -#if CAVS_VERSION == CAVS_VERSION_1_5 - ipc_write(IPC_DIPCIE, header.dat[1]); - ipc_write(IPC_DIPCI, IPC_DIPCI_BUSY | header.dat[0]); -#else ipc_write(IPC_DIPCIDD, header.dat[1]); ipc_write(IPC_DIPCIDR, IPC_DIPCIDR_BUSY | header.dat[0]); -#endif #elif CONFIG_IPC_MAJOR_4 -#if CAVS_VERSION == CAVS_VERSION_1_5 - ipc_write(IPC_DIPCIE, header.ext); - ipc_write(IPC_DIPCI, IPC_DIPCI_BUSY | header.pri); -#else ipc_write(IPC_DIPCIDD, header.ext); ipc_write(IPC_DIPCIDR, IPC_DIPCIDR_BUSY | header.pri); -#endif #endif return 0; } #endif -#if CAVS_VERSION >= CAVS_VERSION_1_8 /* init HW */ static void platform_init_hw(void) { @@ -355,7 +344,6 @@ static void platform_init_hw(void) io_reg_write(DSP_INIT_LPGPDMA(1), LPGPDMA_CHOSEL_FLAG | LPGPDMA_CTLOSEL_FLAG); } -#endif /* Runs on the primary core only */ int platform_init(struct sof *sof) @@ -387,10 +375,8 @@ int platform_init(struct sof *sof) */ pm_runtime_disable(PM_RUNTIME_DSP, 0); -#if CAVS_VERSION >= CAVS_VERSION_1_8 trace_point(TRACE_BOOT_PLATFORM_ENTRY); platform_init_hw(); -#endif trace_point(TRACE_BOOT_PLATFORM_IRQ); platform_interrupt_init(); @@ -422,27 +408,8 @@ int platform_init(struct sof *sof) /* Set CPU to max frequency for booting (single shim_write below) */ trace_point(TRACE_BOOT_PLATFORM_CPU_FREQ); -#if CONFIG_APOLLOLAKE - /* initialize PM for boot */ - - /* TODO: there are two clk freqs CRO & CRO/4 - * Running on CRO all the time atm - */ - - shim_write(SHIM_CLKCTL, - SHIM_CLKCTL_HDCS_PLL | /* HP domain clocked by PLL */ - SHIM_CLKCTL_LDCS_PLL | /* LP domain clocked by PLL */ - SHIM_CLKCTL_DPCS_DIV1(0) | /* Core 0 clk not divided */ - SHIM_CLKCTL_DPCS_DIV1(1) | /* Core 1 clk not divided */ - SHIM_CLKCTL_HPMPCS_DIV2 | /* HP mem clock div by 2 */ - SHIM_CLKCTL_LPMPCS_DIV4 | /* LP mem clock div by 4 */ - SHIM_CLKCTL_TCPAPLLS_DIS | - SHIM_CLKCTL_TCPLCG_DIS(0) | SHIM_CLKCTL_TCPLCG_DIS(1)); - - shim_write(SHIM_LPSCTL, shim_read(SHIM_LPSCTL)); - -#elif CONFIG_CANNONLAKE || CONFIG_ICELAKE || CONFIG_TIGERLAKE +#if CONFIG_CANNONLAKE || CONFIG_ICELAKE || CONFIG_TIGERLAKE /* initialize PM for boot */ /* request configured ring oscillator and wait for status ready */ @@ -473,7 +440,7 @@ int platform_init(struct sof *sof) init_dsp_r_state(r0_r_state); #endif /* CONFIG_CAVS_LPRO_ONLY */ #endif /* CONFIG_DSP_RESIDENCY_COUNTERS */ -#endif /* CONFIG_APOLLOLAKE */ +#endif /* CONFIG_CANNONLAKE || CONFIG_ICELAKE || CONFIG_TIGERLAKE */ /* init DMACs */ trace_point(TRACE_BOOT_PLATFORM_DMA); @@ -619,13 +586,7 @@ int platform_context_save(struct sof *sof) #endif #if CONFIG_CAVS_IMR_D3_PERSISTENT - /* - * Both runtime PM and S2Idle suspend works on APL, while S3 ([deep]) - * doesn't. Only support IMR restoring on cAVS 1.8 and onward at the - * moment. - * TODO: Root cause of why IMR restore doesn't work on APL during S3 - * cycle. - */ + /* Only support IMR restoring on cAVS 1.8 and onward at the moment. */ imr_layout_update((void *)IMR_BOOT_LDR_TEXT_ENTRY_BASE); #endif return 0; diff --git a/src/platform/tigerlake/rom.x.in b/src/platform/tigerlake/rom.x.in index 890814718202..253a70dc436b 100644 --- a/src/platform/tigerlake/rom.x.in +++ b/src/platform/tigerlake/rom.x.in @@ -1,5 +1,5 @@ /* - * Linker Script for Apollolake Bootloader. + * Linker Script for Tigerlake Bootloader. * * This script is run through the GNU C preprocessor to align the memory * offsets with headers. diff --git a/src/samples/audio/Kconfig b/src/samples/audio/Kconfig index 8ac6eb4a3c3e..3edac3bb8116 100644 --- a/src/samples/audio/Kconfig +++ b/src/samples/audio/Kconfig @@ -4,7 +4,7 @@ menu "Audio component samples" visible if SAMPLES config SAMPLE_SMART_AMP - depends on CAVS && !CAVS_VERSION_1_5 || ACE + depends on CAVS || ACE bool "Smart amplifier test component" default y help diff --git a/tools/README.md b/tools/README.md index d81636776a94..c74f411f8560 100644 --- a/tools/README.md +++ b/tools/README.md @@ -17,13 +17,13 @@ make install sof-logger is used to print logs delivered from FW dma_trace mechanism, by searching log entries in *.ldc file generated by smex. -Every entry declared in FW is placed in elf output file (e.g. sof-apl) in +Every entry declared in FW is placed in elf output file (e.g. sof-tgl) in .static_log_entries section in a form of struct defined in sof/src/include/sof/trace.h in sof fw repo. *.ldc file contains `snd_sof_logs_header` (defined in rmbox/logger\_convert.c) following by `.static_log_entries` section -incorporated from FW elf file (e.g. sof-apl). `snd_sof_logs_header` +incorporated from FW elf file (e.g. sof-tgl). `snd_sof_logs_header` contains basic information about `.static_log_entries` section like `base_address` and `data_length`. @@ -133,7 +133,7 @@ Usage sof-coredump-reader.py [-h] [-a ARCH] [-c] [-l COLUMNCOUNT] [-v] We read from dump file into sof-coredump-reader.py, then we pipe its output to xt-gdb, which operates on given elf-file. - $ ./sof-coredump-to-gdb.sh sof-apl dump_file + $ ./sof-coredump-to-gdb.sh sof-tgl dump_file ### tests diff --git a/tools/topology/topology1/CMakeLists.txt b/tools/topology/topology1/CMakeLists.txt index 878a8063eeba..9b4d5d06e81a 100644 --- a/tools/topology/topology1/CMakeLists.txt +++ b/tools/topology/topology1/CMakeLists.txt @@ -34,24 +34,9 @@ set(TPLGS "sof-hda-generic-idisp\;sof-hda-generic-idisp\;-DCHANNELS=0\;-DDYNAMIC=1" "sof-hda-generic-idisp\;sof-hda-generic-idisp-2ch\;-DCHANNELS=2\;-DDMICPROC_FILTER1=eq_iir_coef_highpass_40hz_20db_48khz.m4\;-DDMIC16KPROC_FILTER1=eq_iir_coef_highpass_40hz_20db_16khz.m4\;-DDYNAMIC=1" "sof-hda-generic-idisp\;sof-hda-generic-idisp-4ch\;-DCHANNELS=4\;-DDMICPROC_FILTER1=eq_iir_coef_highpass_40hz_20db_48khz.m4\;-DDMIC16KPROC_FILTER1=eq_iir_coef_highpass_40hz_20db_16khz.m4\;-DDYNAMIC=1" - "sof-apl-keyword-detect\;sof-apl-keyword-detect" "sof-cnl-rt274\;sof-cnl-rt274" - "sof-apl-tdf8532\;sof-apl-tdf8532" - "sof-apl-pcm512x\;sof-apl-pcm512x\;-DFSYNC=48000" - "sof-apl-pcm512x\;sof-apl-pcm512x-master\;-DCODEC_MASTER\;-DFSYNC=48000" - "sof-apl-pcm512x\;sof-apl-pcm512x-master-44100\;-DCODEC_MASTER\;-DFSYNC=44100" - "sof-apl-demux-pcm512x\;sof-apl-demux-pcm512x" - "sof-apl-rt298\;sof-apl-rt298" - "sof-apl-wm8804\;sof-apl-wm8804" - "sof-apl-da7219\;sof-apl-da7219" - "sof-glk-da7219-kwd\;sof-glk-da7219-kwd\;-DPLATFORM=glk" "sof-glk-da7219-kwd\;sof-cml-da7219-max98357a\;-DPLATFORM=cml" "sof-glk-da7219-kwd\;sof-cml-da7219-max98390\;-DCODEC=MAX98390\;-DPLATFORM=cml" - "sof-glk-da7219\;sof-glk-da7219\;-DHEADPHONE=da7219" - "sof-glk-da7219\;sof-glk-cs42l42\;-DHEADPHONE=cs42l42" - "sof-glk-rt5682\;sof-glk-rt5682" - "sof-cavs-nocodec\;sof-apl-nocodec\;-DPLATFORM=bxt\;-DDYNAMIC=1\;-DDISABLE_SSP0\;-DDISABLE_SSP1" - "sof-cavs-nocodec\;sof-glk-nocodec\;-DPLATFORM=bxt\;-DDYNAMIC=1\;-DDISABLE_SSP0\;-DDISABLE_SSP1" "sof-cavs-nocodec\;sof-cnl-nocodec\;-DPLATFORM=cnl\;-DDYNAMIC=1" "sof-cavs-nocodec\;sof-cml-nocodec\;-DPLATFORM=cml\;-DDYNAMIC=1" "sof-cavs-nocodec\;sof-icl-nocodec\;-DPLATFORM=icl\;-DDYNAMIC=1" @@ -174,34 +159,6 @@ set(TPLGS "sof-jsl-rt5682\;sof-jsl-cs42l42-mx98360a\;-DPLATFORM=jsl-dedede" "sof-jsl-rt5682\;sof-jsl-rt5682\;-DHEADPHONE=rt5682\;-DPLATFORM=icl\;-DNO_AMP" - "sof-glk-es8336\;sof-apl-es8336\;-DPLATFORM=bxt\;-DSSP_NUM=2\;-DCHANNELS=0" - "sof-glk-es8336\;sof-apl-es8336-ssp0\;-DPLATFORM=bxt\;-DSSP_NUM=0\;-DCHANNELS=0" - "sof-glk-es8336\;sof-apl-es8336-ssp1\;-DPLATFORM=bxt\;-DSSP_NUM=1\;-DCHANNELS=0" - "sof-glk-es8336\;sof-apl-es8336-ssp2\;-DPLATFORM=bxt\;-DSSP_NUM=2\;-DCHANNELS=0" - "sof-glk-es8336\;sof-apl-es8336-ssp5\;-DPLATFORM=bxt\;-DSSP_NUM=5\;-DCHANNELS=0" - "sof-glk-es8336\;sof-apl-es8336-dmic2ch-ssp0\;-DPLATFORM=bxt\;-DSSP_NUM=0\;-DCHANNELS=2" - "sof-glk-es8336\;sof-apl-es8336-dmic2ch-ssp1\;-DPLATFORM=bxt\;-DSSP_NUM=1\;-DCHANNELS=2" - "sof-glk-es8336\;sof-apl-es8336-dmic2ch-ssp2\;-DPLATFORM=bxt\;-DSSP_NUM=2\;-DCHANNELS=2" - "sof-glk-es8336\;sof-apl-es8336-dmic2ch-ssp5\;-DPLATFORM=bxt\;-DSSP_NUM=5\;-DCHANNELS=2" - "sof-glk-es8336\;sof-apl-es8336-dmic4ch-ssp0\;-DPLATFORM=bxt\;-DSSP_NUM=0\;-DCHANNELS=4" - "sof-glk-es8336\;sof-apl-es8336-dmic4ch-ssp1\;-DPLATFORM=bxt\;-DSSP_NUM=1\;-DCHANNELS=4" - "sof-glk-es8336\;sof-apl-es8336-dmic4ch-ssp2\;-DPLATFORM=bxt\;-DSSP_NUM=2\;-DCHANNELS=4" - "sof-glk-es8336\;sof-apl-es8336-dmic4ch-ssp5\;-DPLATFORM=bxt\;-DSSP_NUM=5\;-DCHANNELS=4" - - "sof-glk-es8336\;sof-glk-es8336\;-DPLATFORM=bxt\;-DSSP_NUM=2\;-DCHANNELS=0" - "sof-glk-es8336\;sof-glk-es8336-ssp0\;-DPLATFORM=bxt\;-DSSP_NUM=0\;-DCHANNELS=0" - "sof-glk-es8336\;sof-glk-es8336-ssp1\;-DPLATFORM=bxt\;-DSSP_NUM=1\;-DCHANNELS=0" - "sof-glk-es8336\;sof-glk-es8336-ssp2\;-DPLATFORM=bxt\;-DSSP_NUM=2\;-DCHANNELS=0" - "sof-glk-es8336\;sof-glk-es8336-ssp5\;-DPLATFORM=bxt\;-DSSP_NUM=5\;-DCHANNELS=0" - "sof-glk-es8336\;sof-glk-es8336-dmic2ch-ssp0\;-DPLATFORM=bxt\;-DSSP_NUM=0\;-DCHANNELS=2" - "sof-glk-es8336\;sof-glk-es8336-dmic2ch-ssp1\;-DPLATFORM=bxt\;-DSSP_NUM=1\;-DCHANNELS=2" - "sof-glk-es8336\;sof-glk-es8336-dmic2ch-ssp2\;-DPLATFORM=bxt\;-DSSP_NUM=2\;-DCHANNELS=2" - "sof-glk-es8336\;sof-glk-es8336-dmic2ch-ssp5\;-DPLATFORM=bxt\;-DSSP_NUM=5\;-DCHANNELS=2" - "sof-glk-es8336\;sof-glk-es8336-dmic4ch-ssp0\;-DPLATFORM=bxt\;-DSSP_NUM=0\;-DCHANNELS=4" - "sof-glk-es8336\;sof-glk-es8336-dmic4ch-ssp1\;-DPLATFORM=bxt\;-DSSP_NUM=1\;-DCHANNELS=4" - "sof-glk-es8336\;sof-glk-es8336-dmic4ch-ssp2\;-DPLATFORM=bxt\;-DSSP_NUM=2\;-DCHANNELS=4" - "sof-glk-es8336\;sof-glk-es8336-dmic4ch-ssp5\;-DPLATFORM=bxt\;-DSSP_NUM=5\;-DCHANNELS=4" - "sof-glk-es8336\;sof-jsl-es8336-ssp0\;-DPLATFORM=jsl\;-DSSP_NUM=0\;-DCHANNELS=0" "sof-glk-es8336\;sof-jsl-es8336-ssp1\;-DPLATFORM=jsl\;-DSSP_NUM=1\;-DCHANNELS=0" "sof-glk-es8336\;sof-jsl-es8336-ssp2\;-DPLATFORM=jsl\;-DSSP_NUM=2\;-DCHANNELS=0" diff --git a/tools/topology/topology1/development/CMakeLists.txt b/tools/topology/topology1/development/CMakeLists.txt index ec6e4278df2e..5a0d8c657459 100644 --- a/tools/topology/topology1/development/CMakeLists.txt +++ b/tools/topology/topology1/development/CMakeLists.txt @@ -1,23 +1,9 @@ # SPDX-License-Identifier: BSD-3-Clause set(TPLGS - "sof-apl-asrc-pcm512x\;sof-apl-asrc-pcm512x" - "sof-apl-asrc-wm8804\;sof-apl-asrc-wm8804" - "sof-apl-src-pcm512x\;sof-apl-src-pcm512x" - "sof-apl-dmic-a96k-b16k\;sof-apl-dmic-a96k-b16k" - "sof-apl-dmic-asymmetric\;sof-apl-dmic-a2ch-b2ch\;-DDMICSETTING=apl-dmic-a2b2" - "sof-apl-dmic-asymmetric\;sof-apl-dmic-a2ch-b4ch\;-DDMICSETTING=apl-dmic-a2b4" - "sof-apl-dmic-asymmetric\;sof-apl-dmic-a4ch-b2ch\;-DDMICSETTING=apl-dmic-a4b2" - "sof-apl-dmic\;sof-apl-dmic-2ch\;-DCHANNELS=2\;-DCPROC=volume" - "sof-apl-dmic\;sof-apl-dmic-4ch\;-DCHANNELS=4\;-DCPROC=volume" - "sof-apl-pcm512x-nohdmi\;sof-apl-pcm512x-nohdmi\;-DPPROC=volume" - "sof-apl-pcm512x-nohdmi\;sof-apl-pcm512x-drc\;-DPPROC=drc" - "sof-apl-pcm512x-nohdmi\;sof-apl-pcm512x-mdrc\;-DPPROC=multiband-drc" - "sof-apl-src-50khz-pcm512x\;sof-apl-src-50khz-pcm512x" "sof-cnl-rt5682-sdw2\;sof-cnl-rt5682-sdw2\;-DPLATFORM=cnl" "sof-cml-src-rt5682\;sof-cml-src-rt5682" "sof-hda-asrc\;sof-hda-asrc-2ch\;-DCHANNELS=2" - "sof-apl-nocodec-ci\;sof-apl-nocodec-ci" "sof-tgl-nocodec-ci\;sof-tgl-nocodec-ci" "sof-tgl-nocodec-ci\;sof-adl-nocodec-ci" "sof-cml-rt1011-rt5682-nokwd\;sof-cml-rt1011-rt5682-nokwd\;-DCHANNELS=2\;-DDMICPROC_FILTER1=eq_iir_coef_highpass_40hz_20db_48khz.m4\;-DDMIC16KPROC_FILTER1=eq_iir_coef_highpass_40hz_20db_16khz.m4" @@ -33,8 +19,6 @@ set(TPLGS "sof-imx8mp-compr-wm8960\;sof-imx8mp-compr-wm8960" "sof-imx8mp-compr-pcm-wm8960\;sof-imx8mp-compr-pcm-wm8960" "sof-imx8mp-compr-pcm-cap-wm8960\;sof-imx8mp-compr-pcm-cap-wm8960" - "sof-apl-nocodec-demux-eq-4ch4ch\;sof-apl-nocodec-demux-eq-4ch4ch" - "sof-apl-nocodec-demux-eq-2ch4ch\;sof-apl-nocodec-demux-eq-2ch4ch" "sof-hda-generic-kwd\;sof-hda-generic-2ch-kwd\;-DCHANNELS=2\;-DDYNAMIC=1" "sof-hda-generic-kwd\;sof-hda-generic-4ch-kwd\;-DCHANNELS=4\;-DDYNAMIC=1" ) @@ -42,13 +26,10 @@ set(TPLGS # The topologies those are built from topology in the parent directory set(TPLGS_UP - "sof-apl-pcm512x\;sof-apl-pcm512x-tdfb_28mm-4ch\;-DFSYNC=48000\;-DDMIC_PCM_CHANNELS=2\;-DDMIC_DAI_CHANNELS=4\;-DDMIC16K_PCM_CHANNELS=2\;-DDMIC16K_DAI_CHANNELS=4\;-DDMIC16KPROC=tdfb-eq-iir-volume\;-DDMIC16KPROC_FILTER1=tdfb/coef_line4_28mm_azm90_90_13el0_0_13deg_16khz.m4\;-DDMICPROC=tdfb-eq-iir-volume\;-DDMICPROC_FILTER1=tdfb/coef_line4_28mm_azm90_90_13el0_0_13deg_48khz.m4\;-DDMICPROC_FILTER2=eq_iir_coef_highpass_40hz_20db_48khz.m4\;-DDMIC16KPROC_FILTER2=eq_iir_coef_highpass_40hz_20db_16khz.m4" - "sof-apl-pcm512x\;sof-apl-pcm512x-mfcc-2ch\;-DFSYNC=48000\;-DCHANNELS=2\;-DDMIC16KPROC=eq-iir-mfcc\;-DDMICPROC_FILTER1=eq_iir_coef_highpass_40hz_20db_48khz.m4\;-DDMIC16KPROC_FILTER1=eq_iir_coef_highpass_40hz_20db_16khz.m4" "sof-cml-rt1011-rt5682\;sof-cml-eq-rt1011-rt5682\;-DPLATFORM=cml\;-DPPROC=eq-iir-eq-fir-volume" "sof-cml-rt5682\;sof-cml-eq-fir-loud-rt5682\;-DPLATFORM=cml\;-DHSEARPROC=eq-iir-volume\;-DPIPELINE_FILTER1=eq_iir_coef_loudness.m4\;-DHSMICPROC=eq-fir-volume\;-DPIPELINE_FILTER2=eq_fir_coef_loudness.m4\;-DDMICPROC=eq-iir-volume\;-DDMIC16KPROC=eq-iir-volume" "sof-cml-rt5682\;sof-cml-eq-fir-rt5682\;-DPLATFORM=cml\;-DHSMICPROC=eq-fir-volume\;-DDMICPROC=eq-iir-volume\;-DDMIC16KPROC=eq-iir-volume" "sof-cml-rt5682\;sof-cml-eq-iir-rt5682\;-DPLATFORM=cml\;-DHSEARPROC=eq-iir-volume\;-DDMICPROC=eq-iir-volume\;-DDMIC16KPROC=eq-iir-volume" - "sof-glk-da7219\;sof-glk-eq-da7219\;-DHEADPHONE=da7219\;-DDMICPROC=eq-iir-volume" "sof-hda-generic\;sof-hda-generic-tdfb_50mm-2ch\;-DCHANNELS=2\;-DHSPROC=volume\;-DDMIC16KPROC=tdfb-eq-iir-volume\;-DDMIC16KPROC_FILTER1=tdfb/coef_line2_50mm_azm90_90_13el0_0_13deg_16khz.m4\;-DDMICPROC=tdfb-eq-iir-volume\;-DDMICPROC_FILTER1=tdfb/coef_line2_50mm_azm90_90_13el0_0_13deg_48khz.m4\;-DDMICPROC_FILTER2=eq_iir_coef_highpass_40hz_20db_48khz.m4\;-DDMIC16KPROC_FILTER2=eq_iir_coef_highpass_40hz_20db_16khz.m4" "sof-hda-generic\;sof-hda-generic-tdfb_68mm-2ch\;-DCHANNELS=2\;-DHSPROC=volume\;-DDMIC16KPROC=tdfb-eq-iir-volume\;-DDMIC16KPROC_FILTER1=tdfb/coef_line2_68mm_azm90_90_13el0_0_13deg_16khz.m4\;-DDMICPROC=tdfb-eq-iir-volume\;-DDMICPROC_FILTER1=tdfb/coef_line2_68mm_azm90_90_13el0_0_13deg_48khz.m4\;-DDMICPROC_FILTER2=eq_iir_coef_highpass_40hz_20db_48khz.m4\;-DDMIC16KPROC_FILTER2=eq_iir_coef_highpass_40hz_20db_16khz.m4" "sof-hda-generic\;sof-hda-generic-tdfb_0mm36mm146mm182mm-4ch\;-DCHANNELS=2\;-DHSPROC=volume\;-DDMIC16KPROC=tdfb-eq-iir-volume\;-DDMIC16KPROC_FILTER1=tdfb/coef_line4_0mm36mm146mm182mm_azm90_90_13el0_0_13deg_16khz.m4\;-DDMICPROC=tdfb-eq-iir-volume\;-DDMICPROC_FILTER1=tdfb/coef_line4_0mm36mm146mm182mm_azm90_90_13el0_0_13deg_48khz.m4\;-DDMICPROC_FILTER2=eq_iir_coef_highpass_40hz_20db_48khz.m4\;-DDMIC16KPROC_FILTER2=eq_iir_coef_highpass_40hz_20db_16khz.m4" diff --git a/tools/topology/topology1/development/sof-apl-asrc-pcm512x.m4 b/tools/topology/topology1/development/sof-apl-asrc-pcm512x.m4 deleted file mode 100644 index 55ded863956b..000000000000 --- a/tools/topology/topology1/development/sof-apl-asrc-pcm512x.m4 +++ /dev/null @@ -1,117 +0,0 @@ -# -# Topology for Apollolake UP^2 with pcm512x codec for testing ASRC -# - -# Include topology builder -include(`utils.m4') -include(`dai.m4') -include(`pipeline.m4') -include(`ssp.m4') - -# Include TLV library -include(`common/tlv.m4') - -# Include Token library -include(`sof/tokens.m4') - -# Include Apollolake DSP configuration -include(`platform/intel/bxt.m4') -include(`platform/intel/dmic.m4') - -DEBUG_START - -# -# Define the pipelines -# -# PCM0 --> ASRC --> Volume --> SSP5 (pcm512x) -# PCM5 <-- ASRC <-- Volume <-- DMIC0 (DMIC) -# PCM6 <-- ASRC <-- Volume <-- DMIC1 (DMIC16kHz) - -dnl PIPELINE_PCM_ADD(pipeline, -dnl pipe id, pcm, max channels, format, -dnl period, priority, core, -dnl pcm_min_rate, pcm_max_rate, pipeline_rate, -dnl time_domain, sched_comp) - -# Playback pipeline 1 on PCM 0 using max 2 channels of s32le. -# Set 1000us deadline with priority 0 on core 0 -PIPELINE_PCM_ADD(sof/pipe-asrc-volume-playback.m4, - 1, 0, 2, s32le, - 1000, 0, 0, - 8000, 192000, 48000) - -# DMIC capture pipeline 2 on PCM 5 using max 2 channels. -# 1000us deadline with priority 0 on core 0 -PIPELINE_PCM_ADD(sof/pipe-asrc-volume-capture.m4, - 2, 5, 2, s32le, - 1000, 0, 0, - 8000, 192000, 48000) - -# DMIC16kHz capture pipeline 2 on PCM 6 using max 2 channels. -# 1000us deadline with priority 0 on core 0 -PIPELINE_PCM_ADD(sof/pipe-asrc-volume-capture.m4, - 3, 6, 2, s32le, - 1000, 0, 0, - 8000, 192000, 16000) - -# -# DAIs configuration -# - -dnl DAI_ADD(pipeline, -dnl pipe id, dai type, dai_index, dai_be, -dnl buffer, periods, format, -dnl deadline, priority, core, time_domain) - -# playback DAI is SSP5 using 2 periods -# Buffers use s24le format, 1000us deadline with priority 0 on core 0 -DAI_ADD(sof/pipe-dai-playback.m4, - 1, SSP, 5, SSP5-Codec, - PIPELINE_SOURCE_1, 2, s24le, - 1000, 0, 0, SCHEDULE_TIME_DOMAIN_TIMER) - -# capture DAI is DMIC using 2 periods -# Buffers use s32le format, 1000us deadline with priority 0 on core 0 -DAI_ADD(sof/pipe-dai-capture.m4, - 2, DMIC, 0, dmic01, - PIPELINE_SINK_2, 2, s32le, - 1000, 0, 0, SCHEDULE_TIME_DOMAIN_TIMER) - -# capture DAI is DMIC16kHz using 2 periods -# Buffers use s16le format, 1000us deadline with priority 0 on core 0 -DAI_ADD(sof/pipe-dai-capture.m4, - 3, DMIC, 1, dmic16k, - PIPELINE_SINK_3, 2, s32le, - 1000, 0, 0, SCHEDULE_TIME_DOMAIN_TIMER) - -# PCM, id 0 -dnl PCM_PLAYBACK_ADD(name, pcm_id, playback) -PCM_PLAYBACK_ADD(Port5, 0, PIPELINE_PCM_1) -PCM_CAPTURE_ADD(DMIC, 5, PIPELINE_PCM_2) -PCM_CAPTURE_ADD(DMIC16kHz, 6, PIPELINE_PCM_3) - -# -# BE configurations - overrides config in ACPI if present -# - -#SSP 5 (ID: 0) -DAI_CONFIG(SSP, 5, 0, SSP5-Codec, - SSP_CONFIG(I2S, SSP_CLOCK(mclk, 24576000, codec_mclk_in), - SSP_CLOCK(bclk, 3072000, codec_slave), - SSP_CLOCK(fsync, 48000, codec_slave), - SSP_TDM(2, 32, 3, 3), - SSP_CONFIG_DATA(SSP, 5, 24))) - -# DMIC (ID: 1) -DAI_CONFIG(DMIC, 0, 1, dmic01, - DMIC_CONFIG(1, 2400000, 4800000, 40, 60, 48000, - DMIC_WORD_LENGTH(s32le), 400, DMIC, 0, - PDM_CONFIG(DMIC, 0, STEREO_PDM0))) - -# DMIC16kHz (ID: 2) -DAI_CONFIG(DMIC, 1, 2, dmic16k, - DMIC_CONFIG(1, 2400000, 4800000, 40, 60, 16000, - DMIC_WORD_LENGTH(s32le), 400, DMIC, 1, - PDM_CONFIG(DMIC, 1, STEREO_PDM0))) - -DEBUG_END diff --git a/tools/topology/topology1/development/sof-apl-asrc-wm8804.m4 b/tools/topology/topology1/development/sof-apl-asrc-wm8804.m4 deleted file mode 100644 index 8ed5e009e88b..000000000000 --- a/tools/topology/topology1/development/sof-apl-asrc-wm8804.m4 +++ /dev/null @@ -1,86 +0,0 @@ -# -# Topology for Apollolake UP^2 with wm8804 codec for testing ASRC -# - -# Include topology builder -include(`utils.m4') -include(`dai.m4') -include(`pipeline.m4') -include(`ssp.m4') - -# Include TLV library -include(`common/tlv.m4') - -# Include Token library -include(`sof/tokens.m4') - -# Include Apollolake DSP configuration -include(`platform/intel/bxt.m4') - -DEBUG_START - -# -# Define the pipelines -# -# PCM0P ---> Volume ---> ASRC ---> SSP5 (wm8804) -# PCM0C <--- ASRC <--- SSP5 (wm8804) -# - -dnl PIPELINE_PCM_ADD(pipeline, -dnl pipe id, pcm, max channels, format, -dnl period, priority, core, -dnl pcm_min_rate, pcm_max_rate, pipeline_rate, -dnl time_domain, sched_comp) - -# Low Latency playback pipeline 1 on PCM 0 using max 2 channels of s32le. -# 1000us deadline with priority 0 on core 0 -PIPELINE_PCM_ADD(sof/pipe-asrc-volume-playback.m4, - 1, 0, 2, s32le, - 1000, 0, 0, - 8000, 48000, 48000) - -# Low Latency capture pipeline 2 on PCM 0 using max 2 channels of s32le. -# 1000us deadline with priority 0 on core 0 -PIPELINE_PCM_ADD(sof/pipe-asrc-capture.m4, - 2, 0, 2, s32le, - 1000, 0, 0, - 8000, 96000, 48000) - -# -# DAIs configuration -# - -dnl DAI_ADD(pipeline, -dnl pipe id, dai type, dai_index, dai_be, -dnl buffer, periods, format, -dnl deadline, priority, core, time_domain) - -# playback DAI is SSP5 using 2 periods -# Buffers use s24le format, 1000us deadline with priority 0 on core 0 -DAI_ADD(sof/pipe-dai-playback.m4, - 1, SSP, 5, SSP5-Codec, - PIPELINE_SOURCE_1, 2, s24le, - 1000, 0, 0, SCHEDULE_TIME_DOMAIN_TIMER) - -# capture DAI is SSP5 using 2 periods -# Buffers use s24le format, 1000us deadline with priority 0 on core 0 -DAI_ADD(sof/pipe-dai-capture.m4, - 2, SSP, 5, SSP5-Codec, - PIPELINE_SINK_2, 2, s24le, - 1000, 0, 0, SCHEDULE_TIME_DOMAIN_DMA) - -# PCM Low Latency, id 0 -PCM_DUPLEX_ADD(Port5, 0, PIPELINE_PCM_1, PIPELINE_PCM_2) - -# -# BE configurations - overrides config in ACPI if present -# - -DAI_CONFIG(SSP, 5, 0, SSP5-Codec, - SSP_CONFIG(I2S, SSP_CLOCK(mclk, 24576000, codec_mclk_in), - SSP_CLOCK(bclk, 3072000, codec_master), - SSP_CLOCK(fsync, 48000, codec_master), - SSP_TDM(2, 32, 3, 3), - SSP_CONFIG_DATA(SSP, 5, 24))) - -DEBUG_END diff --git a/tools/topology/topology1/development/sof-apl-dmic-a96k-b16k.m4 b/tools/topology/topology1/development/sof-apl-dmic-a96k-b16k.m4 deleted file mode 100644 index 9efc11bef416..000000000000 --- a/tools/topology/topology1/development/sof-apl-dmic-a96k-b16k.m4 +++ /dev/null @@ -1,104 +0,0 @@ -# -# Topology for Apollo Lake with direct attach digital microphones array -# - -# Capture configuration -# DAI0 2ch 32b mic1-2 -# DAI1 2ch 32b mic1-2 - -# Include topology builder -include(`utils.m4') -include(`dai.m4') -include(`pipeline.m4') - -# Include TLV library -include(`common/tlv.m4') - -# Include Token library -include(`sof/tokens.m4') - -# Include Apollolake DSP configuration -include(`platform/intel/bxt.m4') -include(`platform/intel/dmic.m4') - -DEBUG_START - -# -# Define the pipelines -# -# PCM6 <--- volume <--- DMIC6 (DMIC01) -# PCM7 <--- volume <--- DMIC7 (DMIC16k) -# - -dnl PIPELINE_PCM_DAI_ADD(pipeline, -dnl pipe id, pcm, max channels, format, -dnl period, priority, core, -dnl dai type, dai_index, dai format, -dnl dai periods, pcm_min_rate, pcm_max_rate, -dnl pipeline_rate, time_domain) - -# Passthrough capture pipeline 6 on PCM 6 using max channels 2. -# Set 1000us deadline with priority 0 on core 0 -PIPELINE_PCM_DAI_ADD(sof/pipe-volume-capture.m4, - 6, 6, 2, s32le, - 1000, 0, 0, DMIC, 0, s32le, 3, - 96000, 96000, 96000) - -# Passthrough capture pipeline 7 on PCM 7 using max channels 2. -# Set 1000us deadline with priority 0 on core 0 -PIPELINE_PCM_DAI_ADD(sof/pipe-volume-capture.m4, - 7, 7, 2, s32le, - 1000, 0, 0, DMIC, 1, s32le, 3, - 16000, 16000, 16000) - -# -# DAIs configuration -# - -dnl DAI_ADD(pipeline, -dnl pipe id, dai type, dai_index, dai_be, -dnl buffer, periods, format, -dnl deadline, priority, core, time_domain) - -# capture DAI is DMIC 0 using 3 periods -# Buffers use s32le format, 1000us deadline with priority 0 on core 0 -DAI_ADD(sof/pipe-dai-capture.m4, - 6, DMIC, 0, NoCodec-6, - PIPELINE_SINK_6, 3, s32le, - 1000, 0, 0, SCHEDULE_TIME_DOMAIN_TIMER) - -# capture DAI is DMIC 1 using 3 periods -# Buffers use s32le format, 1000us deadline with priority 0 on core 0 -DAI_ADD(sof/pipe-dai-capture.m4, - 7, DMIC, 1, NoCodec-7, - PIPELINE_SINK_7, 3, s32le, - 1000, 0, 0, SCHEDULE_TIME_DOMAIN_TIMER) - -dnl PCM_DUPLEX_ADD(name, pcm_id, playback, capture) -dnl PCM_CAPTURE_ADD(name, pipeline, capture) -PCM_CAPTURE_ADD(DMIC01, 6, PIPELINE_PCM_6) -PCM_CAPTURE_ADD(DMIC16k, 7, PIPELINE_PCM_7) - -# -# BE configurations - overrides config in ACPI if present -# - -dnl DAI_CONFIG(type, dai_index, link_id, name, ssp_config/dmic_config) - -DAI_CONFIG(DMIC, 0, 6, NoCodec-6, - dnl DMIC_CONFIG(driver_version, clk_min, clk_mac, duty_min, duty_max, - dnl sample_rate, fifo word length, unmute time, type, - dnl dai_index, pdm controller config) - DMIC_CONFIG(1, 2400000, 4800000, 40, 60, 96000, - DMIC_WORD_LENGTH(s32le), 400, DMIC, 0, - PDM_CONFIG(DMIC, 0, STEREO_PDM0))) - -DAI_CONFIG(DMIC, 1, 7, NoCodec-7, - dnl DMIC_CONFIG(driver_version, clk_min, clk_mac, duty_min, duty_max, - dnl sample_rate, fifo word length, unmute time, type, - dnl dai_index, pdm controller config) - DMIC_CONFIG(1, 2400000, 4800000, 40, 60, 16000, - DMIC_WORD_LENGTH(s32le), 400, DMIC, 1, - PDM_CONFIG(DMIC, 1, STEREO_PDM0))) - -DEBUG_END diff --git a/tools/topology/topology1/development/sof-apl-dmic-asymmetric.m4 b/tools/topology/topology1/development/sof-apl-dmic-asymmetric.m4 deleted file mode 100644 index af4f3e9056f6..000000000000 --- a/tools/topology/topology1/development/sof-apl-dmic-asymmetric.m4 +++ /dev/null @@ -1,103 +0,0 @@ -# -# Topology for Apollo Lake with direct attach digital microphones array -# - -ifdef(`DMICSETTING', , `apl-dmic-a2b4') -include(`platform/intel/'DMICSETTING`.m4') -# Capture configuration -`# DAI0 'ACHANNEL`ch 'AFORMAT` mic1-2' -`# DAI1 'BCHANNEL`ch 'BFORMAT` mic1-4' - -# Include topology builder -include(`utils.m4') -include(`dai.m4') -include(`pipeline.m4') - -# Include TLV library -include(`common/tlv.m4') - -# Include Token library -include(`sof/tokens.m4') - -# Include Apollolake DSP configuration -include(`platform/intel/bxt.m4') -include(`platform/intel/dmic.m4') - - -# -# Define the pipelines -# -# PCM6 <--- volume <--- DMIC6 (DMIC01) -# PCM7 <--- volume <--- DMIC7 (DMIC16k) -# - -dnl PIPELINE_PCM_ADD(pipeline, -dnl pipe id, pcm, max channels, format, -dnl period, priority, core, -dnl pcm_min_rate, pcm_max_rate, pipeline_rate, -dnl time_domain, sched_comp) - -`# Passthrough capture pipeline 6 on PCM 6 using max channels 'ACHANNEL -# Set 1000us deadline with priority 0 on core 0 -PIPELINE_PCM_ADD(sof/pipe-volume-capture.m4, - 6, 6, ACHANNEL, AFORMAT, - 1000, 0, 0, - ARATE, ARATE, ARATE) - -`# Passthrough capture pipeline 7 on PCM 7 using max channels 'BCHANNEL -# Set 1000us deadline with priority 0 on core 0 -PIPELINE_PCM_ADD(sof/pipe-volume-capture-16khz.m4, - 7, 7, BCHANNEL, BFORMAT, - 1000, 0, 0, - BRATE, BRATE, BRATE) - -# -# DAIs configuration -# - -dnl DAI_ADD(pipeline, -dnl pipe id, dai type, dai_index, dai_be, -dnl buffer, periods, format, -dnl deadline, priority, core, time_domain) - -# capture DAI is DMIC 0 using 2 periods -`# Buffers use 'AFORMAT `format, 1000us deadline with priority 0 on core 0' -DAI_ADD(sof/pipe-dai-capture.m4, - 6, DMIC, 0, NoCodec-6, - PIPELINE_SINK_6, 2, AFORMAT, - 1000, 0, 0, SCHEDULE_TIME_DOMAIN_TIMER) - -# capture DAI is DMIC 1 using 2 periods -`# Buffers use 'BFORMAT `format, 1000us deadline with priority 0 on core 0' -DAI_ADD(sof/pipe-dai-capture.m4, - 7, DMIC, 1, NoCodec-7, - PIPELINE_SINK_7, 2, BFORMAT, - 1000, 0, 0, SCHEDULE_TIME_DOMAIN_TIMER) - - -dnl PCM_DUPLEX_ADD(name, pcm_id, playback, capture) -dnl PCM_CAPTURE_ADD(name, pipeline, capture) -PCM_CAPTURE_ADD(DMIC, 6, PIPELINE_PCM_6) -PCM_CAPTURE_ADD(DMIC16kHz, 7, PIPELINE_PCM_7) - -# -# BE configurations - overrides config in ACPI if present -# - -dnl DAI_CONFIG(type, dai_index, link_id, name, ssp_config/dmic_config) - -DAI_CONFIG(DMIC, 0, 6, NoCodec-6, - dnl DMIC_CONFIG(driver_version, clk_min, clk_mac, duty_min, duty_max, - dnl sample_rate, fifo word length, unmute time, type, - dnl dai_index, pdm controller config) - DMIC_CONFIG(1, 2400000, 4800000, 40, 60, ARATE, - DMIC_WORD_LENGTH(AFORMAT), 400, DMIC, 0, - PDM_CONFIG(DMIC, 0, APDM))) - -DAI_CONFIG(DMIC, 1, 7, NoCodec-7, - dnl DMIC_CONFIG(driver_version, clk_min, clk_mac, duty_min, duty_max, - dnl sample_rate, fifo word length, unmute time, type, - dnl dai_index, pdm controller config) - DMIC_CONFIG(1, 2400000, 4800000, 40, 60, BRATE, - DMIC_WORD_LENGTH(BFORMAT), 400, DMIC, 1, - PDM_CONFIG(DMIC, 1, BPDM))) diff --git a/tools/topology/topology1/development/sof-apl-dmic.m4 b/tools/topology/topology1/development/sof-apl-dmic.m4 deleted file mode 100644 index 339c93d071ac..000000000000 --- a/tools/topology/topology1/development/sof-apl-dmic.m4 +++ /dev/null @@ -1,108 +0,0 @@ -# -# Topology for Apollo Lake with direct attach digital microphones array -# - -# Include topology builder -include(`utils.m4') -include(`dai.m4') -include(`pipeline.m4') - -# Include TLV library -include(`common/tlv.m4') - -# Include Token library -include(`sof/tokens.m4') - -# Include Apollolake DSP configuration -include(`platform/intel/bxt.m4') -include(`platform/intel/dmic.m4') - -define(DMIC_PDM_CONFIG, ifelse(CHANNELS, `4', ``FOUR_CH_PDM0_PDM1'', - `ifelse(CHANNELS, `2', ``STEREO_PDM0'', `')')) - -# -# Define the pipelines -# -# CPROC is for capture pipeline processing, i.e volume, eq, eq-iir, eq-fir etc -# In this file, volume and eq are used. If anything else is used, please update -# pipeline comments below for tracking purpose. -# -ifelse(CPROC, `volume', `# PCM6 <----- DMIC6 (DMIC01)', - `ifelse(CPROC, `eq', `# PCM6 <---- EQ IIR <----- DMIC6 (DMIC01)', `')') - -# The pipeline naming notation is pipe-PROCESSING-DIRECTION.m4 -define(PIPE_PROC_CAPTURE, `sof/pipe-`CPROC'-capture.m4') - -# PCM7 <----- DMIC7 (DMIC16k) -# - -dnl PIPELINE_PCM_ADD(pipeline, -dnl pipe id, pcm, max channels, format, -dnl period, priority, core, -dnl pcm_min_rate, pcm_max_rate, pipeline_rate, -dnl time_domain, sched_comp) - -# Passthrough capture pipeline 6 on PCM 6 using max channels defined by CHANNELS. -# Set 1000us deadline with priority 0 on core 0 -PIPELINE_PCM_ADD(PIPE_PROC_CAPTURE, - 6, 6, CHANNELS, s32le, - 1000, 0, 0, - 48000, 48000, 48000) - -# Passthrough capture pipeline 7 on PCM 7 using max channels defined by CHANNELS. -# Set 1000us deadline with priority 0 on core 0 -PIPELINE_PCM_ADD(sof/pipe-volume-capture.m4, - 7, 7, CHANNELS, s32le, - 1000, 0, 0, - 16000, 16000, 16000) - -# -# DAIs configuration -# - -dnl DAI_ADD(pipeline, -dnl pipe id, dai type, dai_index, dai_be, -dnl buffer, periods, format, -dnl deadline, priority, core, time_domain) - -# capture DAI is DMIC 0 using 2 periods -# Buffers use s32le format, 1000us deadline with priority 0 on core 0 -DAI_ADD(sof/pipe-dai-capture.m4, - 6, DMIC, 0, NoCodec-6, - PIPELINE_SINK_6, 2, s32le, - 1000, 0, 0, SCHEDULE_TIME_DOMAIN_TIMER) - -# capture DAI is DMIC 1 using 2 periods -# Buffers use s16le format, 1000us deadline with priority 0 on core 0 -DAI_ADD(sof/pipe-dai-capture.m4, - 7, DMIC, 1, NoCodec-7, - PIPELINE_SINK_7, 2, s16le, - 1000, 0, 0, SCHEDULE_TIME_DOMAIN_TIMER) - - -dnl PCM_DUPLEX_ADD(name, pcm_id, playback, capture) -dnl PCM_CAPTURE_ADD(name, pipeline, capture) -PCM_CAPTURE_ADD(DMIC, 6, PIPELINE_PCM_6) -PCM_CAPTURE_ADD(DMIC16kHz, 7, PIPELINE_PCM_7) - -# -# BE configurations - overrides config in ACPI if present -# - -dnl DAI_CONFIG(type, dai_index, link_id, name, ssp_config/dmic_config) - -DAI_CONFIG(DMIC, 0, 6, NoCodec-6, - dnl DMIC_CONFIG(driver_version, clk_min, clk_mac, duty_min, duty_max, - dnl sample_rate, fifo word length, unmute time, type, - dnl dai_index, pdm controller config) - DMIC_CONFIG(1, 2400000, 4800000, 40, 60, 48000, - DMIC_WORD_LENGTH(s32le), 400, DMIC, 0, - PDM_CONFIG(DMIC, 0, DMIC_PDM_CONFIG))) - -DAI_CONFIG(DMIC, 1, 7, NoCodec-7, - dnl DMIC_CONFIG(driver_version, clk_min, clk_mac, duty_min, duty_max, - dnl sample_rate, fifo word length, unmute time, type, - dnl dai_index, pdm controller config) - DMIC_CONFIG(1, 2400000, 4800000, 40, 60, 16000, - DMIC_WORD_LENGTH(s16le), 400, DMIC, 1, - PDM_CONFIG(DMIC, 1, DMIC_PDM_CONFIG))) diff --git a/tools/topology/topology1/development/sof-apl-nocodec-ci.m4 b/tools/topology/topology1/development/sof-apl-nocodec-ci.m4 deleted file mode 100644 index b8d063fea9d2..000000000000 --- a/tools/topology/topology1/development/sof-apl-nocodec-ci.m4 +++ /dev/null @@ -1,321 +0,0 @@ -# -# Topology for generic Apollolake board with no codec and digital mic array. -# -# APL Host GW DMAC support max 6 playback and max 6 capture channels so some -# pipelines/PCMs/DAIs are commented out to keep within HW bounds. If these -# are needed then they can be used provided other PCMs/pipelines/SSPs are -# commented out in their place. - -# Include topology builder -include(`utils.m4') -include(`dai.m4') -include(`ssp.m4') -include(`pipeline.m4') - -# Include TLV library -include(`common/tlv.m4') - -# Include Token library -include(`sof/tokens.m4') - -# Include Apollolake DSP configuration -include(`platform/intel/bxt.m4') -include(`platform/intel/dmic.m4') - -# -# Define the pipelines -# -# PCM0 <---> volume <----> SSP0 -# PCM1 <---> volume <----> SSP1 -# PCM2 <---> volume <----> SSP2 -# PCM3 <---> volume <----> SSP3 -# PCM4 <---> volume <----> SSP4 -# PCM5 <---> volume <----> SSP5 -# PCM6 <---- volume <----- DMIC6 (DMIC01) -# - -dnl PIPELINE_PCM_ADD(pipeline, -dnl pipe id, pcm, max channels, format, -dnl period, priority, core, -dnl pcm_min_rate, pcm_max_rate, pipeline_rate, -dnl time_domain, sched_comp) - -# Low Latency playback pipeline 1 on PCM 0 using max 2 channels of s16le. -# Set 1000us deadline with priority 0 on core 0 -PIPELINE_PCM_ADD(sof/pipe-low-latency-playback.m4, - 1, 0, 2, s32le, - 1000, 0, 0, - 48000, 48000, 48000) - -# Volume switch capture pipeline 2 on PCM 0 using max 2 channels of s16le. -# 1000us deadline with priority 0 on core 0 -PIPELINE_PCM_ADD(sof/pipe-volume-switch-capture.m4, - 2, 0, 2, s32le, - 1000, 0, 0, - 48000, 48000, 48000) - -# Low Latency playback pipeline 3 on PCM 1 using max 2 channels of s16le. -# 1000us deadline with priority 0 on core 0 -PIPELINE_PCM_ADD(sof/pipe-volume-playback.m4, - 3, 1, 2, s32le, - 1000, 0, 0, - 48000, 48000, 48000) - -# Volume switch capture pipeline 4 on PCM 1 using max 2 channels of s16le. -# 1000us deadline with priority 0 on core 0 -PIPELINE_PCM_ADD(sof/pipe-volume-switch-capture.m4, - 4, 1, 2, s32le, - 1000, 0, 0, - 48000, 48000, 48000) - -# Low Latency playback pipeline 5 on PCM 2 using max 2 channels of s16le. -# 1000us deadline with priority 0 on core 0 -#PIPELINE_PCM_ADD(sof/pipe-volume-playback.m4, -# 5, 2, 2, s32le, -# 1000, 0, 0, -# 48000, 48000, 48000) - -# Volume switch capture pipeline 6 on PCM 2 using max 2 channels of s16le. -# 1000us deadline with priority 0 on core 0 -#PIPELINE_PCM_ADD(sof/pipe-volume-switch-capture.m4, -# 6, 2, 2, s32le, -# 1000, 0, 0, -# 48000, 48000, 48000) - -# Low Latency playback pipeline 7 on PCM 3 using max 2 channels of s16le. -# 1000us deadline with priority 0 on core 0 -PIPELINE_PCM_ADD(sof/pipe-volume-playback.m4, - 7, 3, 2, s32le, - 1000, 0, 0, - 48000, 48000, 48000) - -# Volume switch capture pipeline 8 on PCM 3 using max 2 channels of s16le. -# 1000us deadline with priority 0 on core 0 -PIPELINE_PCM_ADD(sof/pipe-volume-switch-capture.m4, - 8, 3, 2, s32le, - 1000, 0, 0, - 48000, 48000, 48000) - -# Low Latency playback pipeline 9 on PCM 4 using max 2 channels of s16le. -# 1000us deadline with priority 0 on core 0 -#PIPELINE_PCM_ADD(sof/pipe-volume-playback.m4, -# 9, 4, 2, s32le, -# 1000, 0, 0, -# 48000, 48000, 48000) - -# Volume switch capture pipeline 10 on PCM 4 using max 2 channels of s16le. -# 1000us deadline with priority 0 on core 0 -#PIPELINE_PCM_ADD(sof/pipe-volume-switch-capture.m4, -# 10, 4, 2, s32le, -# 1000, 0, 0, -# 48000, 48000, 48000) - -# Low Latency playback pipeline 11 on PCM 5 using max 2 channels of s16le. -# 1000us deadline with priority 0 on core 0 -PIPELINE_PCM_ADD(sof/pipe-volume-playback.m4, - 11, 5, 2, s32le, - 1000, 0, 0, - 48000, 48000, 48000) - -# Volume switch capture pipeline 12 on PCM 5 using max 2 channels of s16le. -# 1000us deadline with priority 0 on core 0 -PIPELINE_PCM_ADD(sof/pipe-volume-switch-capture.m4, - 12, 5, 2, s32le, - 1000, 0, 0, - 48000, 48000, 48000) - -# Passthrough capture pipeline 13 on PCM 6 using max 2 channels. -# 1000us deadline with priority 0 on core 0 -PIPELINE_PCM_ADD(sof/pipe-passthrough-capture.m4, - 13, 6, 2, s32le, - 1000, 0, 0, - 48000, 48000, 48000) - -# -# DAIs configuration -# - -dnl DAI_ADD(pipeline, -dnl pipe id, dai type, dai_index, dai_be, -dnl buffer, periods, format, -dnl deadline, priority, core, time_domain) - -# playback DAI is SSP0 using 2 periods -# Buffers use s16le format, 1000us deadline with priority 0 on core 0 -DAI_ADD(sof/pipe-dai-playback.m4, - 1, SSP, 0, NoCodec-0, - PIPELINE_SOURCE_1, 2, s16le, - 1000, 0, 0, SCHEDULE_TIME_DOMAIN_TIMER) - -# Media playback pipeline 14 on PCM 7 using max 2 channels of s16le. -# Set 4000us deadline with priority 0 on core 0 -PIPELINE_PCM_ADD(sof/pipe-pcm-media.m4, - 14, 7, 2, s16le, - 4000, 0, 0, - 8000, 192000, 48000, - SCHEDULE_TIME_DOMAIN_TIMER, - PIPELINE_PLAYBACK_SCHED_COMP_1) - -# Connect pipelines together -SectionGraph."media-pipeline" { - index "0" - - lines [ - # media 0 - dapm(PIPELINE_MIXER_1, PIPELINE_SOURCE_14) - ] -} - -# capture DAI is SSP0 using 2 periods -# Buffers use s16le format, 1000us deadline with priority 0 on core 0 -DAI_ADD(sof/pipe-dai-capture.m4, - 2, SSP, 0, NoCodec-0, - PIPELINE_SINK_2, 2, s16le, - 1000, 0, 0, SCHEDULE_TIME_DOMAIN_TIMER) - -# playback DAI is SSP1 using 2 periods -# Buffers use s16le format, 1000us deadline with priority 0 on core 0 -DAI_ADD(sof/pipe-dai-playback.m4, - 3, SSP, 1, NoCodec-1, - PIPELINE_SOURCE_3, 2, s16le, - 1000, 0, 0, SCHEDULE_TIME_DOMAIN_TIMER) - -# capture DAI is SSP1 using 2 periods -# Buffers use s16le format, 1000us deadline with priority 0 on core 0 -DAI_ADD(sof/pipe-dai-capture.m4, - 4, SSP, 1, NoCodec-1, - PIPELINE_SINK_4, 2, s16le, - 1000, 0, 0, SCHEDULE_TIME_DOMAIN_TIMER) - -# playback DAI is SSP2 using 2 periods -# Buffers use s16le format, 1000us deadline with priority 0 on core 0 -#DAI_ADD(sof/pipe-dai-playback.m4, -# 5, SSP, 2, NoCodec-2, -# PIPELINE_SOURCE_5, 2, s16le, -# 1000, 0, 0, SCHEDULE_TIME_DOMAIN_TIMER) - -# capture DAI is SSP2 using 2 periods -# Buffers use s16le format, 1000us deadline with priority 0 on core 0 -#DAI_ADD(sof/pipe-dai-capture.m4, -# 6, SSP, 2, NoCodec-2, -# PIPELINE_SINK_6, 2, s16le, -# 1000, 0, 0, SCHEDULE_TIME_DOMAIN_TIMER) - -# playback DAI is SSP3 using 2 periods -# Buffers use s16le format, 1000us deadline with priority 0 on core 0 -DAI_ADD(sof/pipe-dai-playback.m4, - 7, SSP, 3, NoCodec-3, - PIPELINE_SOURCE_7, 2, s16le, - 1000, 0, 0, SCHEDULE_TIME_DOMAIN_TIMER) - -# capture DAI is SSP3 using 2 periods -# Buffers use s16le format, 1000us deadline with priority 0 on core 0 -DAI_ADD(sof/pipe-dai-capture.m4, - 8, SSP, 3, NoCodec-3, - PIPELINE_SINK_8, 2, s16le, - 1000, 0, 0, SCHEDULE_TIME_DOMAIN_TIMER) - -# playback DAI is SSP4 using 2 periods -# Buffers use s16le format, 1000us deadline with priority 0 on core 0 -#DAI_ADD(sof/pipe-dai-playback.m4, -# 9, SSP, 4, NoCodec-4, -# PIPELINE_SOURCE_9, 2, s16le, -# 1000, 0, 0, SCHEDULE_TIME_DOMAIN_TIMER) - -# capture DAI is SSP4 using 2 periods -# Buffers use s16le format, 1000us deadline with priority 0 on core 0 -#DAI_ADD(sof/pipe-dai-capture.m4, -# 10, SSP, 4, NoCodec-4, -# PIPELINE_SINK_10, 2, s16le, -# 1000, 0, 0, SCHEDULE_TIME_DOMAIN_TIMER) - -# playback DAI is SSP5 using 2 periods -# Buffers use s16le format, 1000us deadline with priority 0 on core 0 -DAI_ADD(sof/pipe-dai-playback.m4, - 11, SSP, 5, NoCodec-5, - PIPELINE_SOURCE_11, 2, s16le, - 1000, 0, 0, SCHEDULE_TIME_DOMAIN_TIMER) - -# capture DAI is SSP5 using 2 periods -# Buffers use s16le format, 1000us deadline with priority 0 on core 0 -DAI_ADD(sof/pipe-dai-capture.m4, - 12, SSP, 5, NoCodec-5, - PIPELINE_SINK_12, 2, s16le, - 1000, 0, 0, SCHEDULE_TIME_DOMAIN_TIMER) - -# capture DAI is DMIC 0 using 2 periods -# Buffers use s32le format, 1000us deadline with priority 0 on core 0 -DAI_ADD(sof/pipe-dai-capture.m4, - 13, DMIC, 0, NoCodec-6, - PIPELINE_SINK_13, 2, s32le, - 1000, 0, 0, SCHEDULE_TIME_DOMAIN_TIMER) - -dnl PCM_DUPLEX_ADD(name, pcm_id, playback, capture) -PCM_DUPLEX_ADD(Port0, 0, PIPELINE_PCM_1, PIPELINE_PCM_2) -PCM_DUPLEX_ADD(Port1, 1, PIPELINE_PCM_3, PIPELINE_PCM_4) -#PCM_DUPLEX_ADD(Port2, 2, PIPELINE_PCM_5, PIPELINE_PCM_6) -PCM_DUPLEX_ADD(Port3, 3, PIPELINE_PCM_7, PIPELINE_PCM_8) -#PCM_DUPLEX_ADD(Port4, 4, PIPELINE_PCM_9, PIPELINE_PCM_10) -PCM_DUPLEX_ADD(Port5, 5, PIPELINE_PCM_11, PIPELINE_PCM_12) -dnl PCM_CAPTURE_ADD(name, pipeline, capture) -PCM_CAPTURE_ADD(DMIC, 6, PIPELINE_PCM_13) - -# -# BE configurations - overrides config in ACPI if present -# - -dnl DAI_CONFIG(type, dai_index, link_id, name, ssp_config/dmic_config) -DAI_CONFIG(SSP, 0, 0, NoCodec-0, - dnl SSP_CONFIG(format, mclk, bclk, fsync, tdm, ssp_config_data) - SSP_CONFIG(I2S, SSP_CLOCK(mclk, 24576000, codec_mclk_in), - SSP_CLOCK(bclk, 1536000, codec_slave), - SSP_CLOCK(fsync, 48000, codec_slave), - SSP_TDM(2, 16, 3, 3), - dnl SSP_CONFIG_DATA(type, dai_index, valid bits, mclk_id, quirks) - SSP_CONFIG_DATA(SSP, 0, 16, 0, SSP_QUIRK_LBM))) - -DAI_CONFIG(SSP, 1, 1, NoCodec-1, - SSP_CONFIG(I2S, SSP_CLOCK(mclk, 24576000, codec_mclk_in), - SSP_CLOCK(bclk, 1536000, codec_slave), - SSP_CLOCK(fsync, 48000, codec_slave), - SSP_TDM(2, 16, 3, 3), - SSP_CONFIG_DATA(SSP, 1, 16, 0, SSP_QUIRK_LBM))) - -#DAI_CONFIG(SSP, 2, 2, NoCodec-2, -# SSP_CONFIG(I2S, SSP_CLOCK(mclk, 24576000, codec_mclk_in), -# SSP_CLOCK(bclk, 1536000, codec_slave), -# SSP_CLOCK(fsync, 48000, codec_slave), -# SSP_TDM(2, 16, 3, 3), -# SSP_CONFIG_DATA(SSP, 2, 16, 0, SSP_QUIRK_LBM))) - -DAI_CONFIG(SSP, 3, 3, NoCodec-3, - SSP_CONFIG(I2S, SSP_CLOCK(mclk, 24576000, codec_mclk_in), - SSP_CLOCK(bclk, 1536000, codec_slave), - SSP_CLOCK(fsync, 48000, codec_slave), - SSP_TDM(2, 16, 3, 3), - SSP_CONFIG_DATA(SSP, 3, 16, 0, SSP_QUIRK_LBM))) - -#DAI_CONFIG(SSP, 4, 4, NoCodec-4, -# SSP_CONFIG(I2S, SSP_CLOCK(mclk, 24576000, codec_mclk_in), -# SSP_CLOCK(bclk, 1536000, codec_slave), -# SSP_CLOCK(fsync, 48000, codec_slave), -# SSP_TDM(2, 16, 3, 3), -# SSP_CONFIG_DATA(SSP, 4, 16, 0, SSP_QUIRK_LBM))) - -DAI_CONFIG(SSP, 5, 5, NoCodec-5, - SSP_CONFIG(I2S, SSP_CLOCK(mclk, 24576000, codec_mclk_in), - SSP_CLOCK(bclk, 1536000, codec_slave), - SSP_CLOCK(fsync, 48000, codec_slave), - SSP_TDM(2, 16, 3, 3), - SSP_CONFIG_DATA(SSP, 5, 16, 0, SSP_QUIRK_LBM))) - -DAI_CONFIG(DMIC, 0, 6, NoCodec-6, - dnl DMIC_CONFIG(driver_version, clk_min, clk_mac, duty_min, duty_max, - dnl sample_rate, fifo word length, unmute time, type, - dnl dai_index, pdm controller config) - DMIC_CONFIG(1, 2400000, 4800000, 40, 60, 48000, - DMIC_WORD_LENGTH(s32le), 400, DMIC, 0, - dnl PDM_CONFIG(type, dai_index, num pdm active, pdm tuples list) - dnl STEREO_PDM0 is a pre-defined pdm config for stereo capture - PDM_CONFIG(DMIC, 0, STEREO_PDM0))) - diff --git a/tools/topology/topology1/development/sof-apl-nocodec-demux-eq-2ch4ch.m4 b/tools/topology/topology1/development/sof-apl-nocodec-demux-eq-2ch4ch.m4 deleted file mode 100644 index f3d796e9916c..000000000000 --- a/tools/topology/topology1/development/sof-apl-nocodec-demux-eq-2ch4ch.m4 +++ /dev/null @@ -1,113 +0,0 @@ -# -# Topology for generic Apollolake board with no codec and digital mic array. -# -# APL Host GW DMAC support max 6 playback and max 6 capture channels so some -# pipelines/PCMs/DAIs are commented out to keep within HW bounds. If these -# are needed then they can be used provided other PCMs/pipelines/SSPs are -# commented out in their place. - -# Include topology builder -include(`utils.m4') -include(`dai.m4') -include(`ssp.m4') -include(`pipeline.m4') -include(`muxdemux.m4') - -# Include TLV library -include(`common/tlv.m4') - -# Include Token library -include(`sof/tokens.m4') - -# Include Apollolake DSP configuration -include(`platform/intel/bxt.m4') -include(`platform/intel/dmic.m4') - -dnl Configure demux -dnl name, pipeline_id, routing_matrix_rows -dnl Diagonal 1's in routing matrix mean that every input channel is -dnl copied to corresponding output channels in all output streams. -dnl I.e. row index is the input channel, 1 means it is copied to -dnl corresponding output channel (column index), 0 means it is discarded. -dnl There's a separate matrix for all outputs. -define(matrix1, `ROUTE_MATRIX(1, - `BITS_TO_BYTE(1, 0, 0 ,0 ,0 ,0 ,0 ,0)', - `BITS_TO_BYTE(0, 1, 0 ,0 ,0 ,0 ,0 ,0)', - `BITS_TO_BYTE(1, 0, 0 ,0 ,0 ,0 ,0 ,0)', - `BITS_TO_BYTE(0, 1, 0 ,0 ,0 ,0 ,0 ,0)', - `BITS_TO_BYTE(0, 0, 0 ,0 ,0 ,0 ,0 ,0)', - `BITS_TO_BYTE(0, 0, 0 ,0 ,0 ,0 ,0 ,0)', - `BITS_TO_BYTE(0, 0, 0 ,0 ,0 ,0 ,0 ,0)', - `BITS_TO_BYTE(0, 0, 0 ,0 ,0 ,0 ,0 ,0)')') - -dnl name, num_streams, route_matrix list -MUXDEMUX_CONFIG(demux_priv_1, 1, LIST_NONEWLINE(`', `matrix1')) - -# -# Define the pipelines -# -# PCM0P ---> demux ---> eq_iir ---> SSP0 -# PCM0C <-------------------------- SSP0 - -dnl PIPELINE_PCM_ADD(pipeline, -dnl pipe id, pcm, max channels, format, -dnl period, priority, core, -dnl pcm_min_rate, pcm_max_rate, pipeline_rate, -dnl time_domain, sched_comp) - -# Low Latency playback pipeline 1 on PCM 0 using max 2 channels of s32le. -# Set 1000us deadline with priority 0 on core 0 -PIPELINE_PCM_ADD(sof/pipe-demux-eq-iir-playback.m4, - 1, 0, 2, s32le, - 1000, 0, 0, - 48000, 48000, 48000) - -# Volume switch capture pipeline 2 on PCM 0 using max 4 channels of s32le. -# 1000us deadline with priority 0 on core 0 -PIPELINE_PCM_ADD(sof/pipe-passthrough-capture.m4, - 2, 0, 4, s32le, - 1000, 0, 0, - 48000, 48000, 48000) - - -# -# DAIs configuration -# - -dnl DAI_ADD(pipeline, -dnl pipe id, dai type, dai_index, dai_be, -dnl buffer, periods, format, -dnl deadline, priority, core, time_domain) - -# playback DAI is SSP0 using 2 periods -# Buffers use s32le format, 1000us deadline with priority 0 on core 0 -DAI_ADD(sof/pipe-dai-playback.m4, - 1, SSP, 0, NoCodec-0, - PIPELINE_SOURCE_1, 4, s32le, - 1000, 0, 0, SCHEDULE_TIME_DOMAIN_TIMER) - - -# capture DAI is SSP0 using 2 periods -# Buffers use s32le format, 1000us deadline with priority 0 on core 0 -DAI_ADD(sof/pipe-dai-capture.m4, - 2, SSP, 0, NoCodec-0, - PIPELINE_SINK_2, 4, s32le, - 1000, 0, 0, SCHEDULE_TIME_DOMAIN_TIMER) - - -dnl PCM_DUPLEX_ADD(name, pcm_id, playback, capture) -PCM_DUPLEX_ADD(Port0, 0, PIPELINE_PCM_1, PIPELINE_PCM_2) - -# -# BE configurations - overrides config in ACPI if present -# - -dnl DAI_CONFIG(type, dai_index, link_id, name, ssp_config/dmic_config) -DAI_CONFIG(SSP, 0, 0, NoCodec-0, - dnl SSP_CONFIG(format, mclk, bclk, fsync, tdm, ssp_config_data) - SSP_CONFIG(I2S, SSP_CLOCK(mclk, 24576000, codec_mclk_in), - SSP_CLOCK(bclk, 6144000, codec_slave), - SSP_CLOCK(fsync, 48000, codec_slave), - SSP_TDM(4, 32, 15, 15), - dnl SSP_CONFIG_DATA(type, dai_index, valid bits, mclk_id, quirks) - SSP_CONFIG_DATA(SSP, 0, 32, 0, SSP_QUIRK_LBM))) diff --git a/tools/topology/topology1/development/sof-apl-nocodec-demux-eq-4ch4ch.m4 b/tools/topology/topology1/development/sof-apl-nocodec-demux-eq-4ch4ch.m4 deleted file mode 100644 index 9479b1a4bf47..000000000000 --- a/tools/topology/topology1/development/sof-apl-nocodec-demux-eq-4ch4ch.m4 +++ /dev/null @@ -1,114 +0,0 @@ -# -# Topology for generic Apollolake board with no codec and digital mic array. -# -# APL Host GW DMAC support max 6 playback and max 6 capture channels so some -# pipelines/PCMs/DAIs are commented out to keep within HW bounds. If these -# are needed then they can be used provided other PCMs/pipelines/SSPs are -# commented out in their place. - -# Include topology builder -include(`utils.m4') -include(`dai.m4') -include(`ssp.m4') -include(`pipeline.m4') -include(`muxdemux.m4') - -# Include TLV library -include(`common/tlv.m4') - -# Include Token library -include(`sof/tokens.m4') - -# Include Apollolake DSP configuration -include(`platform/intel/bxt.m4') -include(`platform/intel/dmic.m4') - -dnl Configure demux -dnl name, pipeline_id, routing_matrix_rows -dnl Diagonal 1's in routing matrix mean that every input channel is -dnl copied to corresponding output channels in all output streams. -dnl I.e. row index is the input channel, 1 means it is copied to -dnl corresponding output channel (column index), 0 means it is discarded. -dnl There's a separate matrix for all outputs. -define(matrix1, `ROUTE_MATRIX(1, - `BITS_TO_BYTE(1, 0, 0 ,0 ,0 ,0 ,0 ,0)', - `BITS_TO_BYTE(0, 1, 0 ,0 ,0 ,0 ,0 ,0)', - `BITS_TO_BYTE(1, 0, 0 ,0 ,0 ,0 ,0 ,0)', - `BITS_TO_BYTE(0, 1, 0 ,0 ,0 ,0 ,0 ,0)', - `BITS_TO_BYTE(0, 0, 0 ,0 ,0 ,0 ,0 ,0)', - `BITS_TO_BYTE(0, 0, 0 ,0 ,0 ,0 ,0 ,0)', - `BITS_TO_BYTE(0, 0, 0 ,0 ,0 ,0 ,0 ,0)', - `BITS_TO_BYTE(0, 0, 0 ,0 ,0 ,0 ,0 ,0)')') - -dnl name, num_streams, route_matrix list -MUXDEMUX_CONFIG(demux_priv_1, 1, LIST_NONEWLINE(`', `matrix1')) - -# -# Define the pipelines -# -# PCM0P ---> demux ---> eq_iir ---> SSP0 -# PCM0C <-------------------------- SSP0 - -dnl PIPELINE_PCM_ADD(pipeline, -dnl pipe id, pcm, max channels, format, -dnl period, priority, core, -dnl pcm_min_rate, pcm_max_rate, pipeline_rate, -dnl time_domain, sched_comp) - -# Low Latency playback pipeline 1 on PCM 0 using max 4 channels of s32le. -# Set 1000us deadline with priority 0 on core 0 -PIPELINE_PCM_ADD(sof/pipe-demux-eq-iir-playback.m4, - 1, 0, 4, s32le, - 1000, 0, 0, - 48000, 48000, 48000) - -# Volume switch capture pipeline 2 on PCM 0 using max 4 channels of s32le. -# 1000us deadline with priority 0 on core 0 -PIPELINE_PCM_ADD(sof/pipe-passthrough-capture.m4, - 2, 0, 4, s32le, - 1000, 0, 0, - 48000, 48000, 48000) - - -# -# DAIs configuration -# - -dnl DAI_ADD(pipeline, -dnl pipe id, dai type, dai_index, dai_be, -dnl buffer, periods, format, -dnl deadline, priority, core, time_domain) - -# playback DAI is SSP0 using 2 periods -# Buffers use s32le format, 1000us deadline with priority 0 on core 0 -DAI_ADD(sof/pipe-dai-playback.m4, - 1, SSP, 0, NoCodec-0, - PIPELINE_SOURCE_1, 4, s32le, - 1000, 0, 0, SCHEDULE_TIME_DOMAIN_TIMER) - - -# capture DAI is SSP0 using 2 periods -# Buffers use s32le format, 1000us deadline with priority 0 on core 0 -DAI_ADD(sof/pipe-dai-capture.m4, - 2, SSP, 0, NoCodec-0, - PIPELINE_SINK_2, 4, s32le, - 1000, 0, 0, SCHEDULE_TIME_DOMAIN_TIMER) - - -dnl PCM_DUPLEX_ADD(name, pcm_id, playback, capture) -PCM_DUPLEX_ADD(Port0, 0, PIPELINE_PCM_1, PIPELINE_PCM_2) - -# -# BE configurations - overrides config in ACPI if present -# - -dnl DAI_CONFIG(type, dai_index, link_id, name, ssp_config/dmic_config) -DAI_CONFIG(SSP, 0, 0, NoCodec-0, - dnl SSP_CONFIG(format, mclk, bclk, fsync, tdm, ssp_config_data) - SSP_CONFIG(I2S, SSP_CLOCK(mclk, 24576000, codec_mclk_in), - SSP_CLOCK(bclk, 6144000, codec_slave), - SSP_CLOCK(fsync, 48000, codec_slave), - SSP_TDM(4, 32, 15, 15), - dnl SSP_CONFIG_DATA(type, dai_index, valid bits, mclk_id, quirks) - SSP_CONFIG_DATA(SSP, 0, 32, 0, SSP_QUIRK_LBM))) - diff --git a/tools/topology/topology1/development/sof-apl-pcm512x-nohdmi.m4 b/tools/topology/topology1/development/sof-apl-pcm512x-nohdmi.m4 deleted file mode 100644 index 4e3814745ac6..000000000000 --- a/tools/topology/topology1/development/sof-apl-pcm512x-nohdmi.m4 +++ /dev/null @@ -1,82 +0,0 @@ -# -# Topology for generic Apollolake UP^2 with pcm512x codec and no HDMI. -# - -# Include topology builder -include(`utils.m4') -include(`dai.m4') -include(`pipeline.m4') -include(`ssp.m4') - -# Include TLV library -include(`common/tlv.m4') - -# Include Token library -include(`sof/tokens.m4') - -# Include Apollolake DSP configuration -include(`platform/intel/bxt.m4') - -DEBUG_START - -# -# Define the pipelines -# -# PPROC is for playback pipeline processing, i.e volume, eq-volume, eq-iir, eq-fir etc -# In this file, volume and eq-volume are used. If anything else is used, please update -# pipeline comments below for tracking purpose. -# -ifelse(PPROC, `volume', `# PCM0 ----> volume -----> SSP5 (pcm512x)', - `ifelse(PPROC, `eq-volume', - `# PCM0 ----> EQ IIR ----> EQ FIR ----> volume ----> SSP5 (pcm512x)', `')') -# -# The pipeline naming notation is pipe-PROCESSING-DIRECTION.m4 -define(PIPE_PROC_PLAYBACK, `sof/pipe-`PPROC'-playback.m4') - - -dnl PIPELINE_PCM_ADD(pipeline, -dnl pipe id, pcm, max channels, format, -dnl period, priority, core, -dnl pcm_min_rate, pcm_max_rate, pipeline_rate, -dnl time_domain, sched_comp) - -# Low Latency playback pipeline 1 on PCM 0 using max 2 channels of s32le. -# Set 1000us deadline with priority 0 on core 0 -PIPELINE_PCM_ADD(PIPE_PROC_PLAYBACK, - 1, 0, 2, s32le, - 1000, 0, 0, - 48000, 48000, 48000) - -# -# DAIs configuration -# - -dnl DAI_ADD(pipeline, -dnl pipe id, dai type, dai_index, dai_be, -dnl buffer, periods, format, -dnl deadline, priority, core, time_domain) - -# playback DAI is SSP5 using 2 periods -# Buffers use s24le format, 1000us deadline with priority 0 on core 0 -DAI_ADD(sof/pipe-dai-playback.m4, - 1, SSP, 5, SSP5-Codec, - PIPELINE_SOURCE_1, 2, s24le, - 1000, 0, 0, SCHEDULE_TIME_DOMAIN_TIMER) - -# PCM Low Latency, id 0 -dnl PCM_PLAYBACK_ADD(name, pcm_id, playback) -PCM_PLAYBACK_ADD(Port5, 0, PIPELINE_PCM_1) - -# -# BE configurations - overrides config in ACPI if present -# - -#SSP 5 (ID: 0) -DAI_CONFIG(SSP, 5, 0, SSP5-Codec, - SSP_CONFIG(I2S, SSP_CLOCK(mclk, 24576000, codec_mclk_in), - SSP_CLOCK(bclk, 3072000, codec_slave), - SSP_CLOCK(fsync, 48000, codec_slave), - SSP_TDM(2, 32, 3, 3), - SSP_CONFIG_DATA(SSP, 5, 24))) - -DEBUG_END diff --git a/tools/topology/topology1/development/sof-apl-src-50khz-pcm512x.m4 b/tools/topology/topology1/development/sof-apl-src-50khz-pcm512x.m4 deleted file mode 100644 index 4833bca55f30..000000000000 --- a/tools/topology/topology1/development/sof-apl-src-50khz-pcm512x.m4 +++ /dev/null @@ -1,74 +0,0 @@ -# -# Topology for Apollolake UP^2 with pcm512x codec with sample rate -# conversion (SRC component). -# - -# Include topology builder -include(`utils.m4') -include(`dai.m4') -include(`pipeline.m4') -include(`ssp.m4') - -# Include TLV library -include(`common/tlv.m4') - -# Include Token library -include(`sof/tokens.m4') - -# Include Apollolake DSP configuration -include(`platform/intel/bxt.m4') - -DEBUG_START - -# -# Define the pipelines -# -# PCM0 ----> src -----> SSP5 (pcm512x) -# - -dnl PIPELINE_PCM_ADD(pipeline, -dnl pipe id, pcm, max channels, format, -dnl period, priority, core, -dnl pcm_min_rate, pcm_max_rate, pipeline_rate, -dnl time_domain, sched_comp) - -# Playback pipeline 1 on PCM 0 using max 2 channels of s24le. -# Schedule 1000us deadline with priority 0 on core 0 -PIPELINE_PCM_ADD(sof/pipe-src-volume-playback.m4, - 1, 0, 2, s24le, - 1000, 0, 0, - 48000, 50000, 50000) - -# -# DAIs configuration -# - -dnl DAI_ADD(pipeline, -dnl pipe id, dai type, dai_index, dai_be, -dnl buffer, periods, format, -dnl deadline, priority, core, time_domain) - -# playback DAI is SSP5 using 2 periods -# Buffers use s24le format, with 48 frame per 1000us on core 0 with priority 0 -DAI_ADD(sof/pipe-dai-playback.m4, - 1, SSP, 5, SSP5-Codec, - PIPELINE_SOURCE_1, 2, s24le, - 1000, 0, 0, SCHEDULE_TIME_DOMAIN_TIMER) - -# PCM, id 0 -dnl PCM_PLAYBACK_ADD(name, pcm_id, playback) -PCM_PLAYBACK_ADD(Port5, 0, PIPELINE_PCM_1) - -# -# BE configurations - overrides config in ACPI if present -# - -#SSP 5 (ID: 0) -DAI_CONFIG(SSP, 5, 0, SSP5-Codec, - SSP_CONFIG(I2S, SSP_CLOCK(mclk, 19200000, codec_mclk_in), - SSP_CLOCK(bclk, 3200000, codec_slave), - SSP_CLOCK(fsync, 50000, codec_slave), - SSP_TDM(2, 32, 3, 3), - SSP_CONFIG_DATA(SSP, 5, 24))) - -DEBUG_END diff --git a/tools/topology/topology1/development/sof-apl-src-pcm512x.m4 b/tools/topology/topology1/development/sof-apl-src-pcm512x.m4 deleted file mode 100644 index 8f3ae16e7d8a..000000000000 --- a/tools/topology/topology1/development/sof-apl-src-pcm512x.m4 +++ /dev/null @@ -1,117 +0,0 @@ -# -# Topology for Apollolake UP^2 with pcm512x codec for testing SRC -# - -# Include topology builder -include(`utils.m4') -include(`dai.m4') -include(`pipeline.m4') -include(`ssp.m4') - -# Include TLV library -include(`common/tlv.m4') - -# Include Token library -include(`sof/tokens.m4') - -# Include Apollolake DSP configuration -include(`platform/intel/bxt.m4') -include(`platform/intel/dmic.m4') - -DEBUG_START - -# -# Define the pipelines -# -# PCM0 --> SRC --> Volume --> SSP5 (pcm512x) -# PCM5 <-- SRC <-- Volume <-- DMIC0 (DMIC) -# PCM6 <-- SRC <-- Volume <-- DMIC1 (DMIC16kHz) - -dnl PIPELINE_PCM_ADD(pipeline, -dnl pipe id, pcm, max channels, format, -dnl period, priority, core, -dnl pcm_min_rate, pcm_max_rate, pipeline_rate, -dnl time_domain, sched_comp) - -# Playback pipeline 1 on PCM 0 using max 2 channels of s32le. -# Set 1000us deadline with priority 0 on core 0 -PIPELINE_PCM_ADD(sof/pipe-src-volume-playback.m4, - 1, 0, 2, s32le, - 1000, 0, 0, - 8000, 192000, 48000) - -# DMIC capture pipeline 2 on PCM 5 using max 2 channels. -# 1000us deadline with priority 0 on core 0 -PIPELINE_PCM_ADD(sof/pipe-src-volume-capture.m4, - 2, 5, 2, s32le, - 1000, 0, 0, - 8000, 192000, 48000) - -# DMIC16kHz capture pipeline 2 on PCM 6 using max 2 channels. -# 1000us deadline with priority 0 on core 0 -PIPELINE_PCM_ADD(sof/pipe-src-volume-capture.m4, - 3, 6, 2, s32le, - 1000, 0, 0, - 8000, 192000, 16000) - -# -# DAIs configuration -# - -dnl DAI_ADD(pipeline, -dnl pipe id, dai type, dai_index, dai_be, -dnl buffer, periods, format, -dnl deadline, priority, core, time_domain) - -# playback DAI is SSP5 using 2 periods -# Buffers use s24le format, 1000us deadline with priority 0 on core 0 -DAI_ADD(sof/pipe-dai-playback.m4, - 1, SSP, 5, SSP5-Codec, - PIPELINE_SOURCE_1, 2, s24le, - 1000, 0, 0, SCHEDULE_TIME_DOMAIN_TIMER) - -# capture DAI is DMIC using 2 periods -# Buffers use s32le format, 1000us deadline with priority 0 on core 0 -DAI_ADD(sof/pipe-dai-capture.m4, - 2, DMIC, 0, dmic01, - PIPELINE_SINK_2, 2, s32le, - 1000, 0, 0, SCHEDULE_TIME_DOMAIN_TIMER) - -# capture DAI is DMIC16kHz using 2 periods -# Buffers use s16le format, 1000us deadline with priority 0 on core 0 -DAI_ADD(sof/pipe-dai-capture.m4, - 3, DMIC, 1, dmic16k, - PIPELINE_SINK_3, 2, s32le, - 1000, 0, 0, SCHEDULE_TIME_DOMAIN_TIMER) - -# PCM, id 0 -dnl PCM_PLAYBACK_ADD(name, pcm_id, playback) -PCM_PLAYBACK_ADD(Port5, 0, PIPELINE_PCM_1) -PCM_CAPTURE_ADD(DMIC, 5, PIPELINE_PCM_2) -PCM_CAPTURE_ADD(DMIC16kHz, 6, PIPELINE_PCM_3) - -# -# BE configurations - overrides config in ACPI if present -# - -#SSP 5 (ID: 0) -DAI_CONFIG(SSP, 5, 0, SSP5-Codec, - SSP_CONFIG(I2S, SSP_CLOCK(mclk, 24576000, codec_mclk_in), - SSP_CLOCK(bclk, 3072000, codec_slave), - SSP_CLOCK(fsync, 48000, codec_slave), - SSP_TDM(2, 32, 3, 3), - SSP_CONFIG_DATA(SSP, 5, 24))) - -# DMIC (ID: 1) -DAI_CONFIG(DMIC, 0, 1, dmic01, - DMIC_CONFIG(1, 2400000, 4800000, 40, 60, 48000, - DMIC_WORD_LENGTH(s32le), 400, DMIC, 0, - PDM_CONFIG(DMIC, 0, STEREO_PDM0))) - -# DMIC16kHz (ID: 2) -DAI_CONFIG(DMIC, 1, 2, dmic16k, - DMIC_CONFIG(1, 2400000, 4800000, 40, 60, 16000, - DMIC_WORD_LENGTH(s32le), 400, DMIC, 1, - PDM_CONFIG(DMIC, 1, STEREO_PDM0))) - -DEBUG_END diff --git a/tools/topology/topology1/platform/intel/apl-dmic-a2b2.m4 b/tools/topology/topology1/platform/intel/apl-dmic-a2b2.m4 deleted file mode 100644 index 6bf0a7ac6ba1..000000000000 --- a/tools/topology/topology1/platform/intel/apl-dmic-a2b2.m4 +++ /dev/null @@ -1,20 +0,0 @@ -# apl dmic settings for A2-B2 -undefine(`ACHANNEL') -undefine(`AFORMAT') -undefine(`ARATE') -undefine(`APDM') - -undefine(`BCHANNEL') -undefine(`BFORMAT') -undefine(`BRATE') -undefine(`BPDM') - -define(`ACHANNEL', `2') -define(`AFORMAT', `s32le') -define(`ARATE', `48000') -define(`APDM', `STEREO_PDM0') - -define(`BCHANNEL', `2') -define(`BFORMAT', `s32le') -define(`BRATE', `16000') -define(`BPDM', `STEREO_PDM1') diff --git a/tools/topology/topology1/platform/intel/apl-dmic-a2b4.m4 b/tools/topology/topology1/platform/intel/apl-dmic-a2b4.m4 deleted file mode 100644 index c336fd7cd5bb..000000000000 --- a/tools/topology/topology1/platform/intel/apl-dmic-a2b4.m4 +++ /dev/null @@ -1,20 +0,0 @@ -# apl dmic settings for A2-B4 -undefine(`ACHANNEL') -undefine(`AFORMAT') -undefine(`ARATE') -undefine(`APDM') - -undefine(`BCHANNEL') -undefine(`BFORMAT') -undefine(`BRATE') -undefine(`BPDM') - -define(`ACHANNEL', `2') -define(`AFORMAT', `s16le') -define(`ARATE', `48000') -define(`APDM', `STEREO_PDM0') - -define(`BCHANNEL', `4') -define(`BFORMAT', `s32le') -define(`BRATE', `16000') -define(`BPDM', `FOUR_CH_PDM0_PDM1') diff --git a/tools/topology/topology1/platform/intel/apl-dmic-a4b2.m4 b/tools/topology/topology1/platform/intel/apl-dmic-a4b2.m4 deleted file mode 100644 index e1fa0fd4974b..000000000000 --- a/tools/topology/topology1/platform/intel/apl-dmic-a4b2.m4 +++ /dev/null @@ -1,20 +0,0 @@ -# apl dmic settings for A4-B2 -undefine(`ACHANNEL') -undefine(`AFORMAT') -undefine(`ARATE') -undefine(`APDM') - -undefine(`BCHANNEL') -undefine(`BFORMAT') -undefine(`BRATE') -undefine(`BPDM') - -define(`ACHANNEL', `4') -define(`AFORMAT', `s16le') -define(`ARATE', `48000') -define(`APDM', `FOUR_CH_PDM0_PDM1') - -define(`BCHANNEL', `2') -define(`BFORMAT', `s16le') -define(`BRATE', `16000') -define(`BPDM', `STEREO_PDM0') diff --git a/tools/topology/topology1/platform/intel/glk-da7219.m4 b/tools/topology/topology1/platform/intel/glk-da7219.m4 deleted file mode 100644 index cab68544ee99..000000000000 --- a/tools/topology/topology1/platform/intel/glk-da7219.m4 +++ /dev/null @@ -1,17 +0,0 @@ -include(`platform/intel/bxt.m4') - -# SSP/DMIC machine specific settings on GLK platform -undefine(`SSP_INDEX') -define(`SSP_INDEX', 2) - -undefine(`SSP_NAME') -define(`SSP_NAME', `SSP2-Codec') - -undefine(`DMIC_PCM_NUM') -define(`DMIC_PCM_NUM', `99') - -undefine(`UNUSED_SSP_ROUTE1') -define(`UNUSED_SSP_ROUTE1', `ssp1') - -undefine(`UNUSED_SSP_ROUTE2') -define(`UNUSED_SSP_ROUTE2', `ssp2') diff --git a/tools/topology/topology1/sof-apl-da7219.m4 b/tools/topology/topology1/sof-apl-da7219.m4 deleted file mode 100644 index 9a50991d46b6..000000000000 --- a/tools/topology/topology1/sof-apl-da7219.m4 +++ /dev/null @@ -1,211 +0,0 @@ -# -# Topology for ApolloLake with Dialog7219. -# - -# Include topology builder -include(`utils.m4') -include(`dai.m4') -include(`pipeline.m4') -include(`ssp.m4') -include(`hda.m4') - -# Include TLV library -include(`common/tlv.m4') - -# Include Token library -include(`sof/tokens.m4') - -# Include bxt DSP configuration -include(`platform/intel/bxt.m4') -include(`platform/intel/dmic.m4') - -# -# Define the pipelines -# -# PCM0 ----> volume (pipe 1) -----> SSP5 (speaker - maxim98357a, BE link 0) -# PCM1 <---> volume (pipe 2,3) <----> SSP1 (headset - da7219, BE link 1) -# PCM99 <---- DMIC0 (dmic capture, BE link 2) -# PCM5 ----> volume (pipe 5) -----> iDisp1 (HDMI/DP playback, BE link 3) -# PCM6 ----> Volume (pipe 6) -----> iDisp2 (HDMI/DP playback, BE link 4) -# PCM7 ----> volume (pipe 7) -----> iDisp3 (HDMI/DP playback, BE link 5) -# - -dnl PIPELINE_PCM_ADD(pipeline, -dnl pipe id, pcm, max channels, format, -dnl period, priority, core, -dnl pcm_min_rate, pcm_max_rate, pipeline_rate, -dnl time_domain, sched_comp) - -# Low Latency playback pipeline 1 on PCM 0 using max 2 channels of s32le. -# 1000us deadline with priority 0 on core 0 -PIPELINE_PCM_ADD(sof/pipe-volume-playback.m4, - 1, 0, 2, s32le, - 1000, 0, 0, - 48000, 48000, 48000) - -# Low Latency playback pipeline 2 on PCM 1 using max 2 channels of s32le. -# 1000us deadline with priority 0 on core 0 -PIPELINE_PCM_ADD(sof/pipe-volume-playback.m4, - 2, 1, 2, s32le, - 1000, 0, 0, - 48000, 48000, 48000) - -# Low Latency capture pipeline 3 on PCM 1 using max 2 channels of s32le. -# 1000us deadline with priority 0 on core 0 -PIPELINE_PCM_ADD(sof/pipe-volume-capture.m4, - 3, 1, 2, s32le, - 1000, 0, 0, - 48000, 48000, 48000) - -# Low Latency capture pipeline 4 on PCM 99 using max 4 channels of s32le. -# 1000us deadline with priority 0 on core 0 -PIPELINE_PCM_ADD(sof/pipe-passthrough-capture.m4, - 4, 99, 2, s32le, - 1000, 0, 0, - 48000, 48000, 48000) - -# Low Latency playback pipeline 5 on PCM 5 using max 2 channels of s32le. -# 1000us deadline with priority 0 on core 0 -# PIPELINE_PCM_ADD(sof/pipe-passthrough-playback.m4, -PIPELINE_PCM_ADD(sof/pipe-volume-playback.m4, - 5, 5, 2, s32le, - 1000, 0, 0, - 48000, 48000, 48000) - -# Low Latency playback pipeline 6 on PCM 6 using max 2 channels of s32le. -# 1000us deadline with priority 0 on core 0 -# PIPELINE_PCM_ADD(sof/pipe-passthrough-playback.m4, -PIPELINE_PCM_ADD(sof/pipe-volume-playback.m4, - 6, 6, 2, s32le, - 1000, 0, 0, - 48000, 48000, 48000) - -# Low Latency playback pipeline 7 on PCM 7 using max 2 channels of s32le. -# 1000us deadline with priority 0 on core 0 -# PIPELINE_PCM_ADD(sof/pipe-passthrough-playback.m4, -PIPELINE_PCM_ADD(sof/pipe-volume-playback.m4, - 7, 7, 2, s32le, - 1000, 0, 0, - 48000, 48000, 48000) - -# -# DAIs configuration -# - -dnl DAI_ADD(pipeline, -dnl pipe id, dai type, dai_index, dai_be, -dnl buffer, periods, format, -dnl deadline, priority, core, time_domain) - -# playback DAI is SSP5 using 2 periods -# Buffers use s16le format, 1000us deadline with priority 0 on core 0 -DAI_ADD(sof/pipe-dai-playback.m4, - 1, SSP, 5, SSP5-Codec, - PIPELINE_SOURCE_1, 2, s16le, - 1000, 0, 0, SCHEDULE_TIME_DOMAIN_TIMER) - -# playback DAI is SSP1 using 2 periods -# Buffers use s16le format, 1000us deadline with priority 0 on core 0 -DAI_ADD(sof/pipe-dai-playback.m4, - 2, SSP, 1, SSP1-Codec, - PIPELINE_SOURCE_2, 2, s16le, - 1000, 0, 0, SCHEDULE_TIME_DOMAIN_TIMER) - -# capture DAI is SSP1 using 2 periods -# Buffers use s16le format, 1000us deadline with priority 0 on core 0 -DAI_ADD(sof/pipe-dai-capture.m4, - 3, SSP, 1, SSP1-Codec, - PIPELINE_SINK_3, 2, s16le, - 1000, 0, 0, SCHEDULE_TIME_DOMAIN_TIMER) - -# capture DAI is DMIC0 using 2 periods -# Buffers use s32le format, 1000us deadline with priority 0 on core 0 -DAI_ADD(sof/pipe-dai-capture.m4, - 4, DMIC, 0, dmic01, - PIPELINE_SINK_4, 2, s32le, - 1000, 0, 0, SCHEDULE_TIME_DOMAIN_TIMER) - -# playback DAI is iDisp1 using 2 periods -# Buffers use s32le format, 1000us deadline with priority 0 on core 0 -DAI_ADD(sof/pipe-dai-playback.m4, - 5, HDA, 3, iDisp1, - PIPELINE_SOURCE_5, 2, s32le, - 1000, 0, 0, SCHEDULE_TIME_DOMAIN_TIMER) - -# playback DAI is iDisp2 using 2 periods -# Buffers use s32le format, 1000us deadline with priority 0 on core 0 -DAI_ADD(sof/pipe-dai-playback.m4, - 6, HDA, 4, iDisp2, - PIPELINE_SOURCE_6, 2, s32le, - 1000, 0, 0, SCHEDULE_TIME_DOMAIN_TIMER) - -# playback DAI is iDisp3 using 2 periods -# Buffers use s32le format, 1000us deadline with priority 0 on core 0 -DAI_ADD(sof/pipe-dai-playback.m4, - 7, HDA, 5, iDisp3, - PIPELINE_SOURCE_7, 2, s32le, - 1000, 0, 0, SCHEDULE_TIME_DOMAIN_TIMER) - -PCM_PLAYBACK_ADD(Speakers, 0, PIPELINE_PCM_1) -PCM_DUPLEX_ADD(Headset, 1, PIPELINE_PCM_2, PIPELINE_PCM_3) -PCM_CAPTURE_ADD(DMIC, 99, PIPELINE_PCM_4) -PCM_PLAYBACK_ADD(HDMI1, 5, PIPELINE_PCM_5) -PCM_PLAYBACK_ADD(HDMI2, 6, PIPELINE_PCM_6) -PCM_PLAYBACK_ADD(HDMI3, 7, PIPELINE_PCM_7) - -# -# BE configurations - overrides config in ACPI if present -# - -#SSP 5 (ID: 0) with 19.2 MHz mclk with MCLK_ID 1 (unused), 1.536 MHz blck -DAI_CONFIG(SSP, 5, 0, SSP5-Codec, - SSP_CONFIG(I2S, SSP_CLOCK(mclk, 19200000, codec_mclk_in), - SSP_CLOCK(bclk, 1536000, codec_slave), - SSP_CLOCK(fsync, 48000, codec_slave), - SSP_TDM(2, 16, 3, 3), - SSP_CONFIG_DATA(SSP, 5, 16, 1))) - -#SSP 1 (ID: 1) with 19.2 MHz mclk with MCLK_ID 1, 1.92 MHz bclk -DAI_CONFIG(SSP, 1, 1, SSP1-Codec, - SSP_CONFIG(I2S, SSP_CLOCK(mclk, 19200000, codec_mclk_in), - SSP_CLOCK(bclk, 1920000, codec_slave), - SSP_CLOCK(fsync, 48000, codec_slave), - SSP_TDM(2, 20, 3, 3), - SSP_CONFIG_DATA(SSP, 1, 16, 1))) - -# dmic01 (id: 2) -DAI_CONFIG(DMIC, 0, 2, dmic01, - DMIC_CONFIG(1, 2400000, 4800000, 40, 60, 48000, - DMIC_WORD_LENGTH(s32le), 400, DMIC, 0, - # FIXME: what is the right configuration - # PDM_CONFIG(DMIC, 0, FOUR_CH_PDM0_PDM1))) - PDM_CONFIG(DMIC, 0, STEREO_PDM0))) - -# 3 HDMI/DP outputs (ID: 3,4,5) -DAI_CONFIG(HDA, 3, 3, iDisp1, - HDA_CONFIG(HDA_CONFIG_DATA(HDA, 3, 48000, 2))) -DAI_CONFIG(HDA, 4, 4, iDisp2, - HDA_CONFIG(HDA_CONFIG_DATA(HDA, 4, 48000, 2))) -DAI_CONFIG(HDA, 5, 5, iDisp3, - HDA_CONFIG(HDA_CONFIG_DATA(HDA, 5, 48000, 2))) - -## remove warnings with SST hard-coded routes - -VIRTUAL_WIDGET(ssp5 Tx, out_drv, 0) -VIRTUAL_WIDGET(ssp1 Rx, out_drv, 1) -VIRTUAL_WIDGET(ssp1 Tx, out_drv, 2) -VIRTUAL_WIDGET(iDisp3 Tx, out_drv, 15) -VIRTUAL_WIDGET(iDisp2 Tx, out_drv, 16) -VIRTUAL_WIDGET(iDisp1 Tx, out_drv, 17) -VIRTUAL_WIDGET(DMIC01 Rx, out_drv, 3) -VIRTUAL_WIDGET(DMic, out_drv, 4) -VIRTUAL_WIDGET(dmic01_hifi, out_drv, 5) -VIRTUAL_WIDGET(hif5-0 Output, out_drv, 6) -VIRTUAL_WIDGET(hif6-0 Output, out_drv, 7) -VIRTUAL_WIDGET(hif7-0 Output, out_drv, 8) -VIRTUAL_WIDGET(iDisp3_out, out_drv, 9) -VIRTUAL_WIDGET(iDisp2_out, out_drv, 10) -VIRTUAL_WIDGET(iDisp1_out, out_drv, 11) -VIRTUAL_WIDGET(codec0_out, output, 12) -VIRTUAL_WIDGET(codec1_out, output, 13) -VIRTUAL_WIDGET(codec0_in, input, 14) diff --git a/tools/topology/topology1/sof-apl-demux-pcm512x.m4 b/tools/topology/topology1/sof-apl-demux-pcm512x.m4 deleted file mode 100644 index 457137a4c01d..000000000000 --- a/tools/topology/topology1/sof-apl-demux-pcm512x.m4 +++ /dev/null @@ -1,200 +0,0 @@ -# -# Demux topology for generic Apollolake UP^2 with pcm512x codec and HDMI. -# - -# Include topology builder -include(`utils.m4') -include(`dai.m4') -include(`pipeline.m4') -include(`ssp.m4') -include(`muxdemux.m4') -include(`hda.m4') - -# Include TLV library -include(`common/tlv.m4') - -# Include Token library -include(`sof/tokens.m4') - -# Include Apollolake DSP configuration -include(`platform/intel/bxt.m4') - -DEBUG_START - -dnl Configure demux -dnl name, pipeline_id, routing_matrix_rows -dnl Diagonal 1's in routing matrix mean that every input channel is -dnl copied to corresponding output channels in all output streams. -dnl I.e. row index is the input channel, 1 means it is copied to -dnl corresponding output channel (column index), 0 means it is discarded. -dnl There's a separate matrix for all outputs. -define(matrix1, `ROUTE_MATRIX(1, - `BITS_TO_BYTE(1, 0, 0 ,0 ,0 ,0 ,0 ,0)', - `BITS_TO_BYTE(0, 1, 0 ,0 ,0 ,0 ,0 ,0)', - `BITS_TO_BYTE(0, 0, 1 ,0 ,0 ,0 ,0 ,0)', - `BITS_TO_BYTE(0, 0, 0 ,1 ,0 ,0 ,0 ,0)', - `BITS_TO_BYTE(0, 0, 0 ,0 ,1 ,0 ,0 ,0)', - `BITS_TO_BYTE(0, 0, 0 ,0 ,0 ,1 ,0 ,0)', - `BITS_TO_BYTE(0, 0, 0 ,0 ,0 ,0 ,1 ,0)', - `BITS_TO_BYTE(0, 0, 0 ,0 ,0 ,0 ,0 ,1)')') - -define(matrix2, `ROUTE_MATRIX(5, - `BITS_TO_BYTE(1, 0, 0 ,0 ,0 ,0 ,0 ,0)', - `BITS_TO_BYTE(0, 1, 0 ,0 ,0 ,0 ,0 ,0)', - `BITS_TO_BYTE(0, 0, 1 ,0 ,0 ,0 ,0 ,0)', - `BITS_TO_BYTE(0, 0, 0 ,1 ,0 ,0 ,0 ,0)', - `BITS_TO_BYTE(0, 0, 0 ,0 ,1 ,0 ,0 ,0)', - `BITS_TO_BYTE(0, 0, 0 ,0 ,0 ,1 ,0 ,0)', - `BITS_TO_BYTE(0, 0, 0 ,0 ,0 ,0 ,1 ,0)', - `BITS_TO_BYTE(0, 0, 0 ,0 ,0 ,0 ,0 ,1)')') - -dnl name, num_streams, route_matrix list -MUXDEMUX_CONFIG(demux_priv_1, 2, LIST_NONEWLINE(`', `matrix1,', `matrix2')) - -# -# Define the pipelines -# -# PCM0 ----> demux -----> SSP5 (pcm512x) -# PCM1 ----> volume -----> iDisp1 -# PCM2 ----> volume -----> iDisp2 -# PCM3 ----> volume -----> iDisp3 -# PCM4 <---- demux -# - - - -dnl PIPELINE_PCM_ADD(pipeline, -dnl pipe id, pcm, max channels, format, -dnl period, priority, core, -dnl pcm_min_rate, pcm_max_rate, pipeline_rate, -dnl time_domain, sched_comp) - -# Demux pipeline 1 on PCM 0 using max 2 channels of s32le. -# Set 1000us deadline with priority 0 on core 0 -PIPELINE_PCM_ADD(sof/pipe-volume-demux-playback.m4, - 1, 0, 2, s32le, - 1000, 0, 0, - 48000, 48000, 48000) - -# Low Latency playback pipeline 2 on PCM 1 using max 2 channels of s32le. -# Set 1000us deadline with priority 0 on core 0 -PIPELINE_PCM_ADD(sof/pipe-volume-playback.m4, - 2, 1, 2, s32le, - 1000, 0, 0, - 48000, 48000, 48000) - -# Low Latency playback pipeline 3 on PCM 2 using max 2 channels of s32le. -# Set 1000us deadline with priority 0 on core 0 -PIPELINE_PCM_ADD(sof/pipe-volume-playback.m4, - 3, 2, 2, s32le, - 1000, 0, 0, - 48000, 48000, 48000) - -# Low Latency playback pipeline 4 on PCM 3 using max 2 channels of s32le. -# Set 1000us deadline with priority 0 on core 0 -PIPELINE_PCM_ADD(sof/pipe-volume-playback.m4, - 4, 3, 2, s32le, - 1000, 0, 0, - 48000, 48000, 48000) - -# -# DAIs configuration -# - -dnl DAI_ADD(pipeline, -dnl pipe id, dai type, dai_index, dai_be, -dnl buffer, periods, format, -dnl deadline, priority, core, time_domain) - -# playback DAI is SSP5 using 2 periods -# Buffers use s24le format, 1000us deadline with priority 0 on core 0 -DAI_ADD(sof/pipe-dai-playback.m4, - 1, SSP, 5, SSP5-Codec, - PIPELINE_SOURCE_1, 2, s24le, - 1000, 0, 0, SCHEDULE_TIME_DOMAIN_TIMER) - -# The echo refenrence pipeline has no connections in it, -# it is used for the capture DAI widget to dock. -DAI_ADD(sof/pipe-echo-ref-dai-capture.m4, - 29, SSP, 5, SSP5-Codec, - PIPELINE_SINK_29, 3, s24le, - 1000, 0, 0, SCHEDULE_TIME_DOMAIN_TIMER) - -# Capture pipeline 5 from demux on PCM 5 using max 2 channels of s32le. -PIPELINE_PCM_ADD(sof/pipe-passthrough-capture-sched.m4, - 5, 4, 2, s32le, - 1000, 1, 0, - 48000, 48000, 48000, - SCHEDULE_TIME_DOMAIN_TIMER, - PIPELINE_PLAYBACK_SCHED_COMP_1) - -# Connect demux to capture -SectionGraph."PIPE_CAP" { - index "0" - - lines [ - # mux to capture - dapm(PIPELINE_SINK_5, PIPELINE_DEMUX_1) - ] -} - -# Connect virtual capture to dai -SectionGraph."PIPE_CAP_VIRT" { - index "5" - - lines [ - # mux to capture - dapm(ECHO REF 5, SSP5.IN) - ] -} - -# playback DAI is iDisp1 using 2 periods -# Buffers use s32le format, 1000us deadline with priority 0 on core 0 -DAI_ADD(sof/pipe-dai-playback.m4, - 2, HDA, 0, iDisp1, - PIPELINE_SOURCE_2, 2, s32le, - 1000, 0, 0, SCHEDULE_TIME_DOMAIN_TIMER) - -# playback DAI is iDisp2 using 2 periods -# Buffers use s32le format, 1000us deadline with priority 0 on core 0 -DAI_ADD(sof/pipe-dai-playback.m4, - 3, HDA, 1, iDisp2, - PIPELINE_SOURCE_3, 2, s32le, - 1000, 0, 0, SCHEDULE_TIME_DOMAIN_TIMER) - -# playback DAI is iDisp3 using 2 periods -# Buffers use s32le format, 1000us deadline with priority 0 on core 0 -DAI_ADD(sof/pipe-dai-playback.m4, - 4, HDA, 2, iDisp3, - PIPELINE_SOURCE_4, 2, s32le, - 1000, 0, 0, SCHEDULE_TIME_DOMAIN_TIMER) - -# PCM Low Latency, id 0 -dnl PCM_PLAYBACK_ADD(name, pcm_id, playback) -PCM_PLAYBACK_ADD(Port5, 0, PIPELINE_PCM_1) -PCM_PLAYBACK_ADD(HDMI1, 1, PIPELINE_PCM_2) -PCM_PLAYBACK_ADD(HDMI2, 2, PIPELINE_PCM_3) -PCM_PLAYBACK_ADD(HDMI3, 3, PIPELINE_PCM_4) -PCM_CAPTURE_ADD(EchoRef, 4, PIPELINE_PCM_5) - -# -# BE configurations - overrides config in ACPI if present -# - -#SSP 5 (ID: 0) -DAI_CONFIG(SSP, 5, 0, SSP5-Codec, - SSP_CONFIG(I2S, SSP_CLOCK(mclk, 24576000, codec_mclk_in), - SSP_CLOCK(bclk, 3072000, codec_slave), - SSP_CLOCK(fsync, 48000, codec_slave), - SSP_TDM(2, 32, 3, 3), - SSP_CONFIG_DATA(SSP, 5, 24))) - -# 3 HDMI/DP outputs (ID: 3,4,5) -DAI_CONFIG(HDA, 0, 3, iDisp1, - HDA_CONFIG(HDA_CONFIG_DATA(HDA, 0, 48000, 2))) -DAI_CONFIG(HDA, 1, 4, iDisp2, - HDA_CONFIG(HDA_CONFIG_DATA(HDA, 1, 48000, 2))) -DAI_CONFIG(HDA, 2, 5, iDisp3, - HDA_CONFIG(HDA_CONFIG_DATA(HDA, 2, 48000, 2))) - -DEBUG_END diff --git a/tools/topology/topology1/sof-apl-keyword-detect.m4 b/tools/topology/topology1/sof-apl-keyword-detect.m4 deleted file mode 100644 index 70472737d6e9..000000000000 --- a/tools/topology/topology1/sof-apl-keyword-detect.m4 +++ /dev/null @@ -1,99 +0,0 @@ -# -# Topology for ApolloLake with direct attach digital microphones array for -# keyword detection and triggering use case. -# - -# Include topology builder -include(`utils.m4') -include(`dai.m4') -include(`pipeline.m4') - -# Include TLV library -include(`common/tlv.m4') - -# Include Token library -include(`sof/tokens.m4') - -# Include Apollolake DSP configuration -include(`platform/intel/bxt.m4') -include(`platform/intel/dmic.m4') - -define(KWD_PIPE_SCH_DEADLINE_US, 20000) - -define(DMIC_16k_PCM_NAME, `DMIC16k') - -# -# Define the pipelines -# -# PCM 0 <-------+- KPBM 0 <-- B0 <-- DMIC6 (DMIC01) -# | -# Keyword <-----+ - -dnl PIPELINE_PCM_ADD(pipeline, -dnl pipe id, pcm, max channels, format, -dnl period, priority, core, -dnl pcm_min_rate, pcm_max_rate, pipeline_rate, -dnl time_domain, sched_comp) - -# Passthrough capture pipeline 1 on PCM 0 using max 2 channels. -# Schedule 1000us deadline with priority 0 on core 0 -PIPELINE_PCM_ADD(sof/pipe-kfbm-capture.m4, - 1, 0, 2, s16le, - KWD_PIPE_SCH_DEADLINE_US, 0, 0, - 16000, 16000, 16000) - -# -# DAIs configuration -# - -dnl DAI_ADD(pipeline, -dnl pipe id, dai type, dai_index, dai_be, -dnl buffer, periods, format, -dnl deadline, priority, core, time_domain) - - -# capture DAI is DMIC 0 using 2 periods -# Buffers use s16le format, with 320 frame per 1000us on core 0 with priority 0 -DAI_ADD(sof/pipe-dai-capture.m4, - 1, DMIC, 1, NoCodec-6, - PIPELINE_SINK_1, 2, s16le, - KWD_PIPE_SCH_DEADLINE_US, - 0, 0, SCHEDULE_TIME_DOMAIN_TIMER) - -# keyword detector pipe -dnl PIPELINE_ADD(pipeline, -dnl pipe id, max channels, format, -dnl period, priority, core, -dnl sched_comp, time_domain, -dnl pcm_min_rate, pcm_max_rate, pipeline_rate) -PIPELINE_PCM_ADD(sof/pipe-detect.m4, - 2, 0, 2, s16le, - KWD_PIPE_SCH_DEADLINE_US, 1, 0, - 16000, 16000, 16000, - PIPELINE_SCHED_COMP_1, - SCHEDULE_TIME_DOMAIN_TIMER) - -# Connect pipelines together -SectionGraph."pipe-sof-apl-keyword-detect" { - index "0" - - lines [ - # keyword detect - dapm(PIPELINE_SINK_2, PIPELINE_SOURCE_1) - dapm(PIPELINE_PCM_1, PIPELINE_DETECT_2) - ] -} - -# -# BE configurations - overrides config in ACPI if present -# - -dnl DAI_CONFIG(type, dai_index, link_id, name, ssp_config/dmic_config) -DAI_CONFIG(DMIC, 1, 6, NoCodec-6, - dnl DMIC_CONFIG(driver_version, clk_min, clk_mac, duty_min, duty_max, - dnl sample_rate, fifo word length, unmute time, type, - dnl dai_index, pdm controller config) - DMIC_CONFIG(1, 500000, 4800000, 40, 60, 16000, - DMIC_WORD_LENGTH(s16le), 400, DMIC, 1, - PDM_CONFIG(DMIC, 1, STEREO_PDM0))) - diff --git a/tools/topology/topology1/sof-apl-pcm512x.m4 b/tools/topology/topology1/sof-apl-pcm512x.m4 deleted file mode 100644 index de10231f3bb0..000000000000 --- a/tools/topology/topology1/sof-apl-pcm512x.m4 +++ /dev/null @@ -1,206 +0,0 @@ -# -# Topology for generic Apollolake UP^2 with pcm512x codec and HDMI. -# - -# if XPROC is not defined, define with default pipe -ifdef(`DMICPROC', , `define(DMICPROC, eq-iir-volume)') -ifdef(`DMIC16KPROC', , `define(DMIC16KPROC, eq-iir-volume)') - -# if CHANNELS is not defined, define with default 2ch. Note that -# it can be overrode with DMIC_DAI_CHANNELS, DMIC_PCM_CHANNELS -# in intel-generic-dmic.m4. Same macros exist for DMIC16K too. -ifdef(`CHANNELS', , `define(CHANNELS, 2)') - -# Include topology builder -include(`utils.m4') -include(`dai.m4') -include(`pipeline.m4') -include(`ssp.m4') -include(`hda.m4') - -# Include TLV library -include(`common/tlv.m4') - -# Include Token library -include(`sof/tokens.m4') - -# Include Apollolake DSP configuration -include(`platform/intel/bxt.m4') - -define(`SSP_SCHEDULE_TIME_DOMAIN', - ifdef(`CODEC_MASTER', SCHEDULE_TIME_DOMAIN_DMA, SCHEDULE_TIME_DOMAIN_TIMER)) - -DEBUG_START - -# -# Define the pipelines -# -# PCM0 <---> volume <----> SSP5 (pcm512x) -# PCM5 ----> volume -----> iDisp1 -# PCM6 ----> volume -----> iDisp2 -# PCM7 ----> volume -----> iDisp3 -# PCM4 ----> volume -----> Media Playback 4 -# PCM1 <------------------ DMIC0 (DMIC) -# PCM2 <------------------ DMIC1 (DMIC16kHz) -# - -dnl PIPELINE_PCM_ADD(pipeline, -dnl pipe id, pcm, max channels, format, -dnl period, priority, core, -dnl pcm_min_rate, pcm_max_rate, pipeline_rate, -dnl time_domain, sched_comp) - -# Low Latency playback pipeline 1 on PCM 0 using max 2 channels of s32le. -# Set 1000us deadline with priority 0 on core 0 -PIPELINE_PCM_ADD(sof/pipe-low-latency-playback.m4, - 1, 0, 2, s32le, - 1000, 0, 0, - FSYNC, FSYNC, FSYNC) - -# Low Latency capture pipeline 2 on PCM 0 using max 2 channels of s32le. -# 1000us deadline with priority 0 on core 0 -PIPELINE_PCM_ADD(sof/pipe-volume-capture.m4, - 6, 0, 2, s32le, - 1000, 0, 0, - FSYNC, FSYNC, FSYNC) - -# Low Latency playback pipeline 2 on PCM 5 using max 2 channels of s32le. -# 1000us deadline with priority 0 on core 0 -PIPELINE_PCM_ADD(sof/pipe-volume-playback.m4, - 2, 5, 2, s32le, - 1000, 0, 0, - 48000, 48000, 48000) - -# Low Latency playback pipeline 3 on PCM 6 using max 2 channels of s32le. -# 1000us deadline with priority 0 on core 0 -PIPELINE_PCM_ADD(sof/pipe-volume-playback.m4, - 3, 6, 2, s32le, - 1000, 0, 0, - 48000, 48000, 48000) - -# Low Latency playback pipeline 4 on PCM 7 using max 2 channels of s32le. -# 1000us deadline with priority 0 on core 0 -PIPELINE_PCM_ADD(sof/pipe-volume-playback.m4, - 4, 7, 2, s32le, - 1000, 0, 0, - 48000, 48000, 48000) - -# platform/intel/intel-generic-dmic.m4 uses DAI link IDs for PCM IDs so we have -# to use PCM1 and PCM2 for DMICs. - -ifelse(CHANNELS, `0', , -` -define(DMIC_PCM_48k_ID, `1') -define(DMIC_PCM_16k_ID, `2') -define(DMIC_DAI_LINK_48k_ID, `1') -define(DMIC_DAI_LINK_16k_ID, `2') -define(DMIC_PIPELINE_48k_ID, `7') -define(DMIC_PIPELINE_16k_ID, `8') -include(`platform/intel/intel-generic-dmic.m4') -' -) - -# -# DAIs configuration -# - -dnl DAI_ADD(pipeline, -dnl pipe id, dai type, dai_index, dai_be, -dnl buffer, periods, format, -dnl deadline, priority, core, time_domain) - -# playback DAI is SSP5 using 2 periods -# Buffers use s24le format, 1000us deadline with priority 0 on core 0 -DAI_ADD(sof/pipe-dai-playback.m4, - 1, SSP, 5, SSP5-Codec, - PIPELINE_SOURCE_1, 2, s24le, - 1000, 0, 0, SSP_SCHEDULE_TIME_DOMAIN) - -# capture DAI is SSP5 using 2 periods -# Buffers use s16le format, 1000us deadline with priority 0 on core 0 -DAI_ADD(sof/pipe-dai-capture.m4, - 6, SSP, 5, SSP5-Codec, - PIPELINE_SINK_6, 2, s24le, - 1000, 0, 0, SSP_SCHEDULE_TIME_DOMAIN) - -# Media playback pipeline 5 on PCM 4 using max 2 channels of s32le. -# Set 1000us deadline with priority 0 on core 0 -PIPELINE_PCM_ADD(sof/pipe-pcm-media.m4, - 5, 4, 2, s32le, - 1000, 0, 0, - 8000, 96000, FSYNC, - SSP_SCHEDULE_TIME_DOMAIN, - PIPELINE_PLAYBACK_SCHED_COMP_1) - -# Connect pipelines together -SectionGraph."media-pipeline" { - index "0" - - lines [ - dapm(PIPELINE_MIXER_1, PIPELINE_SOURCE_5) - ] -} - -# playback DAI is iDisp1 using 2 periods -# Buffers use s32le format, 1000us deadline with priority 0 on core 0 -DAI_ADD(sof/pipe-dai-playback.m4, - 2, HDA, 0, iDisp1, - PIPELINE_SOURCE_2, 2, s32le, - 1000, 0, 0, SCHEDULE_TIME_DOMAIN_TIMER) - -# playback DAI is iDisp2 using 2 periods -# Buffers use s32le format, 1000us deadline with priority 0 on core 0 -DAI_ADD(sof/pipe-dai-playback.m4, - 3, HDA, 1, iDisp2, - PIPELINE_SOURCE_3, 2, s32le, - 1000, 0, 0, SCHEDULE_TIME_DOMAIN_TIMER) - -# playback DAI is iDisp3 using 2 periods -# Buffers use s32le format, 1000us deadline with priority 0 on core 0 -DAI_ADD(sof/pipe-dai-playback.m4, - 4, HDA, 2, iDisp3, - PIPELINE_SOURCE_4, 2, s32le, - 1000, 0, 0, SCHEDULE_TIME_DOMAIN_TIMER) - -# PCM Low Latency, id 0 -dnl PCM_PLAYBACK_ADD(name, pcm_id, playback) -PCM_DUPLEX_ADD(Port5, 0, PIPELINE_PCM_1, PIPELINE_PCM_6) -PCM_PLAYBACK_ADD(HDMI1, 5, PIPELINE_PCM_2) -PCM_PLAYBACK_ADD(HDMI2, 6, PIPELINE_PCM_3) -PCM_PLAYBACK_ADD(HDMI3, 7, PIPELINE_PCM_4) - -# -# BE configurations - overrides config in ACPI if present -# - -dnl DAI_CONFIG(type, dai_index, link_id, name, ssp_config/dmic_config) -#SSP 5 (ID: 0) -ifdef(`CODEC_MASTER', -` -DAI_CONFIG(SSP, 5, 0, SSP5-Codec, - SSP_CONFIG(I2S, SSP_CLOCK(mclk, 24576000, codec_mclk_in), - SSP_CLOCK(bclk, eval(FSYNC * 64), codec_master), - SSP_CLOCK(fsync, FSYNC, codec_master), - SSP_TDM(2, 32, 3, 3), - SSP_CONFIG_DATA(SSP, 5, 24))) -' -, -` -DAI_CONFIG(SSP, 5, 0, SSP5-Codec, - SSP_CONFIG(I2S, SSP_CLOCK(mclk, 24576000, codec_mclk_in), - SSP_CLOCK(bclk, 3072000, codec_slave), - SSP_CLOCK(fsync, 48000, codec_slave), - SSP_TDM(2, 32, 3, 3), - SSP_CONFIG_DATA(SSP, 5, 24))) -' -) - -# 3 HDMI/DP outputs (ID: 3,4,5) -DAI_CONFIG(HDA, 0, 3, iDisp1, - HDA_CONFIG(HDA_CONFIG_DATA(HDA, 0, 48000, 2))) -DAI_CONFIG(HDA, 1, 4, iDisp2, - HDA_CONFIG(HDA_CONFIG_DATA(HDA, 1, 48000, 2))) -DAI_CONFIG(HDA, 2, 5, iDisp3, - HDA_CONFIG(HDA_CONFIG_DATA(HDA, 2, 48000, 2))) - -DEBUG_END diff --git a/tools/topology/topology1/sof-apl-rt298.m4 b/tools/topology/topology1/sof-apl-rt298.m4 deleted file mode 100644 index 4e1a596b8d90..000000000000 --- a/tools/topology/topology1/sof-apl-rt298.m4 +++ /dev/null @@ -1,124 +0,0 @@ -# -# Topology for generic Apollolake UP^2 with pcm512x codec. -# - -# Include topology builder -include(`utils.m4') -include(`dai.m4') -include(`pipeline.m4') -include(`ssp.m4') -include(`hda.m4') - -# Include TLV library -include(`common/tlv.m4') - -# Include Token library -include(`sof/tokens.m4') - -# Include Apollolake DSP configuration -include(`platform/intel/bxt.m4') - -# -# Define the pipelines -# -# PCM0 ----> volume -----> SSP5 (rt298) -# PCM5 ----> volume (pipe 5) -----> iDisp1 (HDMI/DP playback, BE link 3) -# PCM6 ----> volume (pipe 6) -----> iDisp2 (HDMI/DP playback, BE link 4) -# PCM7 ----> volume (pipe 7) -----> iDisp3 (HDMI/DP playback, BE link 5) -# - -dnl PIPELINE_PCM_ADD(pipeline, -dnl pipe id, pcm, max channels, format, -dnl period, priority, core, -dnl pcm_min_rate, pcm_max_rate, pipeline_rate, -dnl time_domain, sched_comp) - -# Low Latency playback pipeline 1 on PCM 0 using max 2 channels of s32le. -# 1000us deadline with priority 0 on core 0 -PIPELINE_PCM_ADD(sof/pipe-volume-playback.m4, - 1, 0, 2, s32le, - 1000, 0, 0, - 48000, 48000, 48000) - -# Low Latency playback pipeline 5 on PCM 5 using max 2 channels of s16le. -# 1000us deadline with priority 0 on core 0 -PIPELINE_PCM_ADD(sof/pipe-volume-playback.m4, - 5, 5, 2, s16le, - 1000, 0, 0, - 48000, 48000, 48000) - -# Low Latency playback pipeline 6 on PCM 6 using max 2 channels of s16le. -# 1000us deadline with priority 0 on core 0 -PIPELINE_PCM_ADD(sof/pipe-volume-playback.m4, - 6, 6, 2, s16le, - 1000, 0, 0, - 48000, 48000, 48000) - -# Low Latency playback pipeline 7 on PCM 7 using max 2 channels of s16le. -# 1000us deadline with priority 0 on core 0 -PIPELINE_PCM_ADD(sof/pipe-volume-playback.m4, - 7, 7, 2, s16le, - 1000, 0, 0, - 48000, 48000, 48000) -# -# DAIs configuration -# - -dnl DAI_ADD(pipeline, -dnl pipe id, dai type, dai_index, dai_be, -dnl buffer, periods, format, -dnl deadline, priority, core, time_domain) - -# playback DAI is SSP5 using 2 periods -# Buffers use s24le format, 1000us deadline with priority 0 on core 0 -DAI_ADD(sof/pipe-dai-playback.m4, - 1, SSP, 5, SSP5-Codec, - PIPELINE_SOURCE_1, 2, s24le, - 1000, 0, 0, SCHEDULE_TIME_DOMAIN_TIMER) - -# playback DAI is iDisp1 using 2 periods -# Buffers use s16le format, 1000us deadline with priority 0 on core 0 -DAI_ADD(sof/pipe-dai-playback.m4, - 5, HDA, 3, iDisp1, - PIPELINE_SOURCE_5, 2, s32le, - 1000, 0, 0, SCHEDULE_TIME_DOMAIN_TIMER) - -# playback DAI is iDisp2 using 2 periods -# Buffers use s16le format, 1000us deadline with priority 0 on core 0 -DAI_ADD(sof/pipe-dai-playback.m4, - 6, HDA, 4, iDisp2, - PIPELINE_SOURCE_6, 2, s32le, - 1000, 0, 0, SCHEDULE_TIME_DOMAIN_TIMER) - -# playback DAI is iDisp3 using 2 periods -# Buffers use s16le format, 1000us deadline with priority 0 on core 0 -DAI_ADD(sof/pipe-dai-playback.m4, - 7, HDA, 5, iDisp3, - PIPELINE_SOURCE_7, 2, s32le, - 1000, 0, 0, SCHEDULE_TIME_DOMAIN_TIMER) - -# PCM Low Latency, id 0 -PCM_PLAYBACK_ADD(Port5, 0, PIPELINE_PCM_1) -PCM_PLAYBACK_ADD(HDMI1, 5, PIPELINE_PCM_5) -PCM_PLAYBACK_ADD(HDMI2, 6, PIPELINE_PCM_6) -PCM_PLAYBACK_ADD(HDMI3, 7, PIPELINE_PCM_7) - -# -# BE configurations - overrides config in ACPI if present -# -# -# 3 HDMI/DP outputs (ID: 3,4,5) -DAI_CONFIG(SSP, 5, 0, SSP5-Codec, - SSP_CONFIG(I2S, SSP_CLOCK(mclk, 24576000, codec_mclk_in), - SSP_CLOCK(bclk, 3072000, codec_slave), - SSP_CLOCK(fsync, 48000, codec_slave), - SSP_TDM(2, 32, 3, 3), - SSP_CONFIG_DATA(SSP, 5, 24))) - -DAI_CONFIG(HDA, 3, 3, iDisp1, - HDA_CONFIG(HDA_CONFIG_DATA(HDA, 3, 48000, 2))) -DAI_CONFIG(HDA, 4, 4, iDisp2, - HDA_CONFIG(HDA_CONFIG_DATA(HDA, 4, 48000, 2))) -DAI_CONFIG(HDA, 5, 5, iDisp3, - HDA_CONFIG(HDA_CONFIG_DATA(HDA, 5, 48000, 2))) - diff --git a/tools/topology/topology1/sof-apl-tdf8532.m4 b/tools/topology/topology1/sof-apl-tdf8532.m4 deleted file mode 100644 index 99447c67efc0..000000000000 --- a/tools/topology/topology1/sof-apl-tdf8532.m4 +++ /dev/null @@ -1,262 +0,0 @@ -# -# Topology for generic Apollolake board with TDF8532 -# - -# Include topology builder -include(`utils.m4') -include(`dai.m4') -include(`pipeline.m4') -include(`ssp.m4') - -# Include TLV library -include(`common/tlv.m4') - -# Include Token library -include(`sof/tokens.m4') - -# Include Apollolake DSP configuration -include(`platform/intel/bxt.m4') - -# -# Define the pipelines -# -# PCM0 -----> Volume -----> SSP4 -# PCM1 <----> Volume <----> SSP2(Dirana Pb/Cp) -# PCM2 <----> Volume <----> SSP0(BT HFP out/in) -# PCM3 <----- Volume <----- SSP1(HDMI in) -# PCM4 <----> Volume <----> SSP3(Modem out/in) -# PCM5 <----> Volume <----> SSP5(TestPin out/in) -# - -dnl PIPELINE_PCM_ADD(pipeline, -dnl pipe id, pcm, max channels, format, -dnl period, priority, core, -dnl pcm_min_rate, pcm_max_rate, pipeline_rate, -dnl time_domain, sched_comp) - -# Low Latency playback pipeline 1 on PCM 0 using max 4 channels of s32le. -# 1000us deadline with priority 0 on core 0 -PIPELINE_PCM_ADD(sof/pipe-volume-playback.m4, - 1, 0, 4, s32le, - 1000, 0, 0, - 48000, 48000, 48000) - -# Low Latency playback pipeline 2 on PCM 1 using max 8 channels of s32le. -# 1000us deadline with priority 0 on core 0 -PIPELINE_PCM_ADD(sof/pipe-volume-playback.m4, - 2, 1, 8, s32le, - 1000, 0, 0, - 48000, 48000, 48000) - -# Low Latency capture pipeline 3 on PCM 1 using max 8 channels of s32le. -# 1000us deadline with priority 0 on core 0 -PIPELINE_PCM_ADD(sof/pipe-volume-capture.m4, - 3, 1, 8, s32le, - 1000, 0, 0, - 48000, 48000, 48000) - -# Low Latency playback pipeline 4 on PCM 2 using max 2 channels of s16le. -# 1000us deadline with priority 0 on core 0 -PIPELINE_PCM_ADD(sof/pipe-volume-playback.m4, - 4, 2, 2, s16le, - 1000, 0, 0, - 48000, 48000, 48000) - -# Low Latency capture pipeline 5 on PCM 2 using max 2 channels of s16le. -# 1000us deadline with priority 0 on core 0 -PIPELINE_PCM_ADD(sof/pipe-volume-capture.m4, - 5, 2, 2, s16le, - 1000, 0, 0, - 48000, 48000, 48000) - -# Low Latency capture pipeline 6 on PCM 3 using max 2 channels of s16le. -# 1000us deadline with priority 0 on core 0 -PIPELINE_PCM_ADD(sof/pipe-volume-capture.m4, - 6, 3, 2, s16le, - 1000, 0, 0, - 48000, 48000, 48000) - -# Low Latency playback pipeline 7 on PCM 4 using max 2 channels of s16le. -# 1000us deadline with priority 0 on core 0 -PIPELINE_PCM_ADD(sof/pipe-volume-playback.m4, - 7, 4, 2, s16le, - 1000, 0, 0, - 48000, 48000, 48000) - -# Low Latency capture pipeline 8 on PCM 4 using max 2 channels of s16le. -# 1000us deadline with priority 0 on core 0 -PIPELINE_PCM_ADD(sof/pipe-volume-capture.m4, - 8, 4, 2, s16le, - 1000, 0, 0, - 48000, 48000, 48000) - -# Low Latency playback pipeline 9 on PCM 5 using max 2 channels of s16le. -# 1000us deadline with priority 0 on core 0 -PIPELINE_PCM_ADD(sof/pipe-volume-playback.m4, - 9, 5, 2, s16le, - 1000, 0, 0, - 48000, 48000, 48000) - -# Low Latency capture pipeline 10 on PCM 5 using max 2 channels of s16le. -# 1000us deadline with priority 0 on core 0 -PIPELINE_PCM_ADD(sof/pipe-volume-capture.m4, - 10, 5, 2, s16le, - 1000, 0, 0, - 48000, 48000, 48000) - - -# -# DAIs configuration -# - -dnl DAI_ADD(pipeline, -dnl pipe id, dai type, dai_index, dai_be, -dnl buffer, periods, format, -dnl deadline, priority, core, time_domain) - -# playback DAI is SSP0 using 2 periods -# Buffers use s16le format, 1000us deadline with priority 0 on core 0 -DAI_ADD(sof/pipe-dai-playback.m4, - 4, SSP, 0, SSP0-Codec, - PIPELINE_SOURCE_4, 2, s16le, - 1000, 0, 0, SCHEDULE_TIME_DOMAIN_TIMER) - -# capture DAI is SSP0 using 2 periods -# Buffers use s16le format, 1000us deadline with priority 0 on core 0 -DAI_ADD(sof/pipe-dai-capture.m4, - 5, SSP, 0, SSP0-Codec, - PIPELINE_SINK_5, 2, s16le, - 1000, 0, 0, SCHEDULE_TIME_DOMAIN_TIMER) - -# capture DAI is SSP1 using 2 periods -# Buffers use s16le format, 1000us deadline with priority 0 on core 0 -DAI_ADD(sof/pipe-dai-capture.m4, - 6, SSP, 1, SSP1-Codec, - PIPELINE_SINK_6, 2, s16le, - 1000, 0, 0, SCHEDULE_TIME_DOMAIN_TIMER) - -# playback DAI is SSP2 using 2 periods -# Buffers use s32le format, 1000us deadline with priority 0 on core 0 -DAI_ADD(sof/pipe-dai-playback.m4, - 2, SSP, 2, SSP2-Codec, - PIPELINE_SOURCE_2, 2, s32le, - 1000, 0, 0, SCHEDULE_TIME_DOMAIN_TIMER) - -# capture DAI is SSP2 using 2 periods -# Buffers use s32le format, 1000us deadline with priority 0 on core 0 -DAI_ADD(sof/pipe-dai-capture.m4, - 3, SSP, 2, SSP2-Codec, - PIPELINE_SINK_3, 2, s32le, - 1000, 0, 0, SCHEDULE_TIME_DOMAIN_TIMER) - -# playback DAI is SSP3 using 2 periods -# Buffers use s16le format, 1000us deadline with priority 0 on core 0 -DAI_ADD(sof/pipe-dai-playback.m4, - 7, SSP, 3, SSP3-Codec, - PIPELINE_SOURCE_7, 2, s16le, - 1000, 0, 0, SCHEDULE_TIME_DOMAIN_TIMER) - -# capture DAI is SSP3 using 2 periods -# Buffers use s16le format, 1000us deadline with priority 0 on core 0 -DAI_ADD(sof/pipe-dai-capture.m4, - 8, SSP, 3, SSP3-Codec, - PIPELINE_SINK_8, 2, s16le, - 1000, 0, 0, SCHEDULE_TIME_DOMAIN_TIMER) - -# playback DAI is SSP4 using 2 periods -# Buffers use s32le format, 1000us deadline with priority 0 on core 0 -DAI_ADD(sof/pipe-dai-playback.m4, - 1, SSP, 4, SSP4-Codec, - PIPELINE_SOURCE_1, 2, s32le, - 1000, 0, 0, SCHEDULE_TIME_DOMAIN_TIMER) - -# playback DAI is SSP5 using 2 periods -# Buffers use s16le format, 1000us deadline with priority 0 on core 0 -DAI_ADD(sof/pipe-dai-playback.m4, - 9, SSP, 5, SSP5-Codec, - PIPELINE_SOURCE_9, 2, s16le, - 1000, 0, 0, SCHEDULE_TIME_DOMAIN_TIMER) - -# capture DAI is SSP5 using 2 periods -# Buffers use s16le format, 1000us deadline with priority 0 on core 0 -DAI_ADD(sof/pipe-dai-capture.m4, - 10, SSP, 5, SSP5-Codec, - PIPELINE_SINK_10, 2, s16le, - 1000, 0, 0, SCHEDULE_TIME_DOMAIN_TIMER) - -# PCM Low Latency, id 0 -PCM_DUPLEX_ADD(Port0, 2, PIPELINE_PCM_4, PIPELINE_PCM_5) -PCM_CAPTURE_ADD(Port1, 3, PIPELINE_PCM_6) -PCM_DUPLEX_ADD(Port2, 1, PIPELINE_PCM_2, PIPELINE_PCM_3) -PCM_DUPLEX_ADD(Port3, 4, PIPELINE_PCM_7, PIPELINE_PCM_8) -PCM_PLAYBACK_ADD(Port4, 0, PIPELINE_PCM_1) -PCM_DUPLEX_ADD(Port5, 5, PIPELINE_PCM_9, PIPELINE_PCM_10) - -# -# BE configurations - overrides config in ACPI if present -# -DAI_CONFIG(SSP, 0, 0, SSP0-Codec, - SSP_CONFIG(I2S, SSP_CLOCK(mclk, 24576000, codec_mclk_in), - SSP_CLOCK(bclk, 1536000, codec_slave), - SSP_CLOCK(fsync, 48000, codec_slave), - SSP_TDM(2, 16, 3, 3), - SSP_CONFIG_DATA(SSP, 0, 16))) - -DAI_CONFIG(SSP, 1, 1, SSP1-Codec, - SSP_CONFIG(I2S, SSP_CLOCK(mclk, 24576000, codec_mclk_in), - SSP_CLOCK(bclk, 1536000, codec_slave), - SSP_CLOCK(fsync, 48000, codec_slave), - SSP_TDM(2, 16, 3, 3), - SSP_CONFIG_DATA(SSP, 1, 16))) - -DAI_CONFIG(SSP, 2, 2, SSP2-Codec, - SSP_CONFIG(DSP_B, SSP_CLOCK(mclk, 24576000, codec_mclk_in), - SSP_CLOCK(bclk, 12288000, codec_slave), - SSP_CLOCK(fsync, 48000, codec_slave), - SSP_TDM(8, 32, 255, 255), - SSP_CONFIG_DATA(SSP, 2, 32))) - -DAI_CONFIG(SSP, 3, 3, SSP3-Codec, - SSP_CONFIG(I2S, SSP_CLOCK(mclk, 24576000, codec_mclk_in), - SSP_CLOCK(bclk, 1536000, codec_slave), - SSP_CLOCK(fsync, 48000, codec_slave), - SSP_TDM(2, 16, 3, 3), - SSP_CONFIG_DATA(SSP, 3, 16))) - -DAI_CONFIG(SSP, 4, 4, SSP4-Codec, - SSP_CONFIG(DSP_B, SSP_CLOCK(mclk, 24576000, codec_mclk_in), - SSP_CLOCK(bclk, 12288000, codec_slave), - SSP_CLOCK(fsync, 48000, codec_slave), - SSP_TDM(8, 32, 15, 15), - SSP_CONFIG_DATA(SSP, 4, 32))) - -DAI_CONFIG(SSP, 5, 5, SSP5-Codec, - SSP_CONFIG(I2S, SSP_CLOCK(mclk, 24576000, codec_mclk_in), - SSP_CLOCK(bclk, 1536000, codec_slave), - SSP_CLOCK(fsync, 48000, codec_slave), - SSP_TDM(2, 16, 3, 3), - SSP_CONFIG_DATA(SSP, 5, 16))) - - -VIRTUAL_DAPM_ROUTE_IN(BtHfp_ssp0_in, SSP, 0, IN, 0) -VIRTUAL_DAPM_ROUTE_OUT(BtHfp_ssp0_out, SSP, 0, OUT, 1) -VIRTUAL_DAPM_ROUTE_IN(hdmi_ssp1_in, SSP, 1, IN, 2) -VIRTUAL_DAPM_ROUTE_IN(dirana_in, SSP, 2, IN, 3) -VIRTUAL_DAPM_ROUTE_IN(dirana_aux_in, SSP, 2, IN, 4) -VIRTUAL_DAPM_ROUTE_IN(dirana_tuner_in, SSP, 2, IN, 5) -VIRTUAL_DAPM_ROUTE_OUT(dirana_out, SSP, 2, OUT, 6) -VIRTUAL_DAPM_ROUTE_IN(Modem_ssp3_in, SSP, 3, IN, 7) -VIRTUAL_DAPM_ROUTE_OUT(Modem_ssp3_out, SSP, 3, OUT, 8) -VIRTUAL_DAPM_ROUTE_OUT(codec0_out, SSP, 4, OUT, 9) -VIRTUAL_DAPM_ROUTE_IN(TestPin_ssp5_in, SSP, 5, IN, 10) -VIRTUAL_DAPM_ROUTE_OUT(TestPin_ssp5_out, SSP, 5, OUT, 11) -VIRTUAL_WIDGET(ssp0 Tx, out_drv, 12) -VIRTUAL_WIDGET(ssp0 Rx, out_drv, 13) -VIRTUAL_WIDGET(ssp1 Rx, out_drv, 14) -VIRTUAL_WIDGET(ssp2 Tx, out_drv, 15) -VIRTUAL_WIDGET(ssp2 Rx, out_drv, 16) -VIRTUAL_WIDGET(ssp3 Tx, out_drv, 17) -VIRTUAL_WIDGET(ssp3 Rx, out_drv, 18) -VIRTUAL_WIDGET(ssp4 Tx, out_drv, 19) -VIRTUAL_WIDGET(ssp5 Tx, out_drv, 20) -VIRTUAL_WIDGET(ssp5 Rx, out_drv, 21) diff --git a/tools/topology/topology1/sof-apl-wm8804.m4 b/tools/topology/topology1/sof-apl-wm8804.m4 deleted file mode 100644 index 5ae7cf6b6454..000000000000 --- a/tools/topology/topology1/sof-apl-wm8804.m4 +++ /dev/null @@ -1,81 +0,0 @@ -# -# Topology for generic Apollolake UP^2 with wm8804 codec. -# - -# Include topology builder -include(`utils.m4') -include(`dai.m4') -include(`pipeline.m4') -include(`ssp.m4') - -# Include TLV library -include(`common/tlv.m4') - -# Include Token library -include(`sof/tokens.m4') - -# Include Apollolake DSP configuration -include(`platform/intel/bxt.m4') - -# -# Define the pipelines -# -# PCM0 <----> volume <-----> SSP5 (wm8804) -# - -dnl PIPELINE_PCM_ADD(pipeline, -dnl pipe id, pcm, max channels, format, -dnl period, priority, core, -dnl pcm_min_rate, pcm_max_rate, pipeline_rate, -dnl time_domain, sched_comp) - -# Low Latency playback pipeline 1 on PCM 0 using max 2 channels of s32le. -# 1000us deadline with priority 0 on core 0 -PIPELINE_PCM_ADD(sof/pipe-volume-playback.m4, - 1, 0, 2, s32le, - 1000, 0, 0, - 48000, 48000, 48000) - -# Low Latency capture pipeline 2 on PCM 0 using max 2 channels of s32le. -# 1000us deadline with priority 0 on core 0 -PIPELINE_PCM_ADD(sof/pipe-low-latency-capture.m4, - 2, 0, 2, s32le, - 1000, 0, 0, - 48000, 48000, 48000) - -# -# DAIs configuration -# - -dnl DAI_ADD(pipeline, -dnl pipe id, dai type, dai_index, dai_be, -dnl buffer, periods, format, -dnl deadline, priority, core, time_domain) - -# playback DAI is SSP5 using 2 periods -# Buffers use s24le format, 1000us deadline with priority 0 on core 0 -DAI_ADD(sof/pipe-dai-playback.m4, - 1, SSP, 5, SSP5-Codec, - PIPELINE_SOURCE_1, 2, s24le, - 1000, 0, 0, SCHEDULE_TIME_DOMAIN_DMA) - -# capture DAI is SSP5 using 2 periods -# Buffers use s24le format, 1000us deadline with priority 0 on core 0 -DAI_ADD(sof/pipe-dai-capture.m4, - 2, SSP, 5, SSP5-Codec, - PIPELINE_SINK_2, 2, s24le, - 1000, 0, 0, SCHEDULE_TIME_DOMAIN_DMA) - -# PCM Low Latency, id 0 -PCM_DUPLEX_ADD(Port5, 0, PIPELINE_PCM_1, PIPELINE_PCM_2) - -# -# BE configurations - overrides config in ACPI if present -# - -DAI_CONFIG(SSP, 5, 0, SSP5-Codec, - SSP_CONFIG(I2S, SSP_CLOCK(mclk, 24576000, codec_mclk_in), - SSP_CLOCK(bclk, 3072000, codec_master), - SSP_CLOCK(fsync, 48000, codec_master), - SSP_TDM(2, 32, 3, 3), - SSP_CONFIG_DATA(SSP, 5, 24))) diff --git a/tools/topology/topology1/sof-cavs-nocodec.m4 b/tools/topology/topology1/sof-cavs-nocodec.m4 index 1efa0dddf109..88c9c7bbeaf5 100644 --- a/tools/topology/topology1/sof-cavs-nocodec.m4 +++ b/tools/topology/topology1/sof-cavs-nocodec.m4 @@ -17,8 +17,6 @@ include(`sof/tokens.m4') # Include DSP configuration include(`platform/intel/'PLATFORM`.m4') -# bxt has 2 cores but currently only one is enabled in the build -ifelse(PLATFORM, `bxt', `define(NCORES, 1)') ifelse(PLATFORM, `cnl', `define(NCORES, 4)') ifelse(PLATFORM, `cml', `define(NCORES, 4)') ifelse(PLATFORM, `icl', `define(NCORES, 4)') @@ -76,17 +74,9 @@ define(SSP2_CORE_ID, `0') include(`platform/intel/intel-generic-dmic.m4') -ifelse(PLATFORM, `bxt', -` -define(SSP0_IDX, `0') -define(SSP1_IDX, `1') -define(SSP2_IDX, `5') -', -` define(SSP0_IDX, `0') define(SSP1_IDX, `1') define(SSP2_IDX, `2') -') define(PIPE_BITS, `s32le') define(DAI_BITS, `s24le') @@ -163,13 +153,12 @@ PIPELINE_PCM_ADD(sof/pipe-host-volume-playback.m4, # Deep buffer playback pipeline 11 on PCM 3 using max 2 channels of PIPE_BITS. # Set 1000us deadline on core SSP0_CORE_ID with priority 0. # TODO: Modify pipeline deadline to account for deep buffering -ifelse(PLATFORM, `bxt', `', -`PIPELINE_PCM_ADD(sof/pipe-host-volume-playback.m4, +PIPELINE_PCM_ADD(sof/pipe-host-volume-playback.m4, 11, 3, 2, PIPE_BITS, 1000, 0, SSP0_CORE_ID, 48000, 48000, 48000, SCHEDULE_TIME_DOMAIN_TIMER, - PIPELINE_PLAYBACK_SCHED_COMP_1)') + PIPELINE_PLAYBACK_SCHED_COMP_1) # capture DAI is SSP0 using 2 periods # Buffers use DAI_BITS format, 1000us deadline with priority 0 on core SSP0_IDX @@ -217,17 +206,6 @@ PIPELINE_PCM_ADD(sof/pipe-host-volume-playback.m4, SCHEDULE_TIME_DOMAIN_TIMER, PIPELINE_PLAYBACK_SCHED_COMP_5) -# Deep buffer playback pipeline 11 on PCM 3 using max 2 channels of PIPE_BITS. -# Set 1000us deadline on core SSP2_CORE_ID with priority 0. -# TODO: Modify pipeline deadline to account for deep buffering -ifelse(PLATFORM, `bxt', -`PIPELINE_PCM_ADD(sof/pipe-host-volume-playback.m4, - 11, 3, 2, PIPE_BITS, - 1000, 0, SSP2_CORE_ID, - 48000, 48000, 48000, - SCHEDULE_TIME_DOMAIN_TIMER, - PIPELINE_PLAYBACK_SCHED_COMP_5)') - # capture DAI is SSP2 using 2 periods # Buffers use DAI_BITS format, 1000us deadline with priority 0 on core SSP2_CORE_ID DAI_ADD(sof/pipe-dai-capture.m4, @@ -243,10 +221,6 @@ SectionGraph."mixer-host" { dapm(PIPELINE_MIXER_1, PIPELINE_SOURCE_7) dapm(PIPELINE_MIXER_3, PIPELINE_SOURCE_8) dapm(PIPELINE_MIXER_5, PIPELINE_SOURCE_9) - ifelse(PLATFORM, `bxt', - `dapm(PIPELINE_MIXER_5, PIPELINE_SOURCE_11)', - `dapm(PIPELINE_MIXER_1, PIPELINE_SOURCE_11)') - ] } @@ -258,15 +232,11 @@ ifdef(`DISABLE_SSP1',, PCM_DUPLEX_ADD(`Port'SSP1_IDX, 1, PIPELINE_PCM_8, PIPELINE_PCM_4) ) PCM_DUPLEX_ADD(`Port'SSP2_IDX, 2, PIPELINE_PCM_9, PIPELINE_PCM_6) -ifelse(PLATFORM,`bxt', -`PCM_PLAYBACK_ADD(`Port'SSP2_IDX` Deep Buffer', 3, PIPELINE_PCM_11)', -`PCM_PLAYBACK_ADD(`Port'SSP0_IDX` Deep Buffer', 3, PIPELINE_PCM_11)') # # BE configurations - overrides config in ACPI if present # -ifelse(PLATFORM, `bxt', `define(ROOT_CLK, 19_2)') ifelse(PLATFORM, `cnl', `define(ROOT_CLK, 24)') ifelse(PLATFORM, `cml', `define(ROOT_CLK, 24)') ifelse(PLATFORM, `icl', `define(ROOT_CLK, 38_4)') diff --git a/tools/topology/topology1/sof-glk-da7219.m4 b/tools/topology/topology1/sof-glk-da7219.m4 deleted file mode 100644 index c92982355101..000000000000 --- a/tools/topology/topology1/sof-glk-da7219.m4 +++ /dev/null @@ -1,240 +0,0 @@ -# -# Topology for GeminiLake with Dialog Semiconductor DA7219 or -# Cirrus Logic CS42L42 -# - -# Include topology builder -include(`utils.m4') -include(`dai.m4') -include(`pipeline.m4') -include(`ssp.m4') -include(`hda.m4') - -# Include TLV library -include(`common/tlv.m4') - -# Include Token library -include(`sof/tokens.m4') - -# Include bxt DSP configuration -include(`platform/intel/bxt.m4') -include(`platform/intel/dmic.m4') - -# -# Define the pipelines -# -# PCM0 ----> volume (pipe 1) -----> SSP1 (speaker - maxim98357a, BE link 0) -`# PCM1 <---> volume (pipe 2,3) <----> SSP2 (headset - 'HEADPHONE`, BE link 1)' -`# PCM99 <---- 'DMICPROC` <---- DMIC0 (dmic capture, BE link 2)' -# PCM5 ----> volume (pipe 5) -----> iDisp1 (HDMI/DP playback, BE link 3) -# PCM6 ----> Volume (pipe 6) -----> iDisp2 (HDMI/DP playback, BE link 4) -# PCM7 ----> volume (pipe 7) -----> iDisp3 (HDMI/DP playback, BE link 5) -# - -dnl PIPELINE_PCM_ADD(pipeline, -dnl pipe id, pcm, max channels, format, -dnl period, priority, core, -dnl pcm_min_rate, pcm_max_rate, pipeline_rate, -dnl time_domain, sched_comp) - -# Low Latency playback pipeline 1 on PCM 0 using max 2 channels of s32le. -# 1000us deadline with priority 0 on core 0 -PIPELINE_PCM_ADD(sof/pipe-volume-playback.m4, - 1, 0, 2, s32le, - 1000, 0, 0, - 48000, 48000, 48000) - -# Low Latency playback pipeline 2 on PCM 1 using max 2 channels of s32le. -# 1000us deadline with priority 0 on core 0 -PIPELINE_PCM_ADD(sof/pipe-volume-playback.m4, - 2, 1, 2, s32le, - 1000, 0, 0, - 48000, 48000, 48000) - -# Low Latency capture pipeline 3 on PCM 1 using max 2 channels of s32le. -# 1000us deadline with priority 0 on core 0 -PIPELINE_PCM_ADD(sof/pipe-volume-capture.m4, - 3, 1, 2, s32le, - 1000, 0, 0, - 48000, 48000, 48000) - -# if DMICPROC is not defined, default pipepline is volume -ifdef(`DMICPROC', , `define(DMICPROC, volume)') -define(DEF_PIPE_DMIC_CAPTURE, sof/pipe-DMICPROC-capture.m4) - -# Low Latency capture pipeline 4 on PCM 99 using max 4 channels of s32le. -# 1000us deadline with priority 0 on core 0 -PIPELINE_PCM_ADD(DEF_PIPE_DMIC_CAPTURE, - 4, 99, 4, s32le, - 1000, 0, 0, - 48000, 48000, 48000) - -# Low Latency playback pipeline 5 on PCM 5 using max 2 channels of s32le. -# 1000us deadline with priority 0 on core 0 -# PIPELINE_PCM_ADD(sof/pipe-passthrough-playback.m4, -PIPELINE_PCM_ADD(sof/pipe-volume-playback.m4, - 5, 5, 2, s32le, - 1000, 0, 0, - 48000, 48000, 48000) - -# Low Latency playback pipeline 6 on PCM 6 using max 2 channels of s32le. -# 1000us deadline with priority 0 on core 0 -# PIPELINE_PCM_ADD(sof/pipe-passthrough-playback.m4, -PIPELINE_PCM_ADD(sof/pipe-volume-playback.m4, - 6, 6, 2, s32le, - 1000, 0, 0, - 48000, 48000, 48000) - -# Low Latency playback pipeline 7 on PCM 7 using max 2 channels of s32le. -# 1000us deadline with priority 0 on core 0 -# PIPELINE_PCM_ADD(sof/pipe-passthrough-playback.m4, -PIPELINE_PCM_ADD(sof/pipe-volume-playback.m4, - 7, 7, 2, s32le, - 1000, 0, 0, - 48000, 48000, 48000) - -# -# DAIs configuration -# - -dnl DAI_ADD(pipeline, -dnl pipe id, dai type, dai_index, dai_be, -dnl buffer, periods, format, -dnl deadline, priority, core, time_domain) - -# playback DAI is SSP1 using 2 periods -# Buffers use s16le format, 1000us deadline with priority 0 on core 0 -DAI_ADD(sof/pipe-dai-playback.m4, - 1, SSP, 1, SSP1-Codec, - PIPELINE_SOURCE_1, 2, s16le, - 1000, 0, 0, SCHEDULE_TIME_DOMAIN_TIMER) - -ifelse(HEADPHONE, `da7219', ` -# playback DAI is SSP2 using 2 periods -# Buffers use s16le format, 1000us deadline with priority 0 on core 0 -DAI_ADD(sof/pipe-dai-playback.m4, - 2, SSP, 2, SSP2-Codec, - PIPELINE_SOURCE_2, 2, s16le, - 1000, 0, 0, SCHEDULE_TIME_DOMAIN_TIMER) - -# capture DAI is SSP2 using 2 periods -# Buffers use s16le format, 1000us deadline with priority 0 on core 0 -DAI_ADD(sof/pipe-dai-capture.m4, - 3, SSP, 2, SSP2-Codec, - PIPELINE_SINK_3, 2, s16le, - 1000, 0, 0, SCHEDULE_TIME_DOMAIN_TIMER) -', HEADPHONE, `cs42l42', ` -# playback DAI is SSP2 using 2 periods -# Buffers use s24le format, 1000us deadline with priority 0 on core 0 -DAI_ADD(sof/pipe-dai-playback.m4, - 2, SSP, 2, SSP2-Codec, - PIPELINE_SOURCE_2, 2, s24le, - 1000, 0, 0, SCHEDULE_TIME_DOMAIN_TIMER) - -# capture DAI is SSP2 using 2 periods -# Buffers use s24le format, 1000us deadline with priority 0 on core 0 -DAI_ADD(sof/pipe-dai-capture.m4, - 3, SSP, 2, SSP2-Codec, - PIPELINE_SINK_3, 2, s24le, - 1000, 0, 0, SCHEDULE_TIME_DOMAIN_TIMER) -', ) - -# capture DAI is DMIC0 using 2 periods -# Buffers use s32le format, 1000us deadline with priority 0 on core 0 -DAI_ADD(sof/pipe-dai-capture.m4, - 4, DMIC, 0, dmic01, - PIPELINE_SINK_4, 2, s32le, - 1000, 0, 0, SCHEDULE_TIME_DOMAIN_TIMER) - -# playback DAI is iDisp1 using 2 periods -# Buffers use s32le format, 1000us deadline with priority 0 on core 0 -DAI_ADD(sof/pipe-dai-playback.m4, - 5, HDA, 3, iDisp1, - PIPELINE_SOURCE_5, 2, s32le, - 1000, 0, 0, SCHEDULE_TIME_DOMAIN_TIMER) - -# playback DAI is iDisp2 using 2 periods -# Buffers use s32le format, 1000us deadline with priority 0 on core 0 -DAI_ADD(sof/pipe-dai-playback.m4, - 6, HDA, 4, iDisp2, - PIPELINE_SOURCE_6, 2, s32le, - 1000, 0, 0, SCHEDULE_TIME_DOMAIN_TIMER) - -# playback DAI is iDisp3 using 2 periods -# Buffers use s32le format, 1000us deadline with priority 0 on core 0 -DAI_ADD(sof/pipe-dai-playback.m4, - 7, HDA, 5, iDisp3, - PIPELINE_SOURCE_7, 2, s32le, - 1000, 0, 0, SCHEDULE_TIME_DOMAIN_TIMER) - -PCM_PLAYBACK_ADD(Speakers, 0, PIPELINE_PCM_1) -PCM_DUPLEX_ADD(Headset, 1, PIPELINE_PCM_2, PIPELINE_PCM_3) -PCM_CAPTURE_ADD(DMIC, 99, PIPELINE_PCM_4) -PCM_PLAYBACK_ADD(HDMI1, 5, PIPELINE_PCM_5) -PCM_PLAYBACK_ADD(HDMI2, 6, PIPELINE_PCM_6) -PCM_PLAYBACK_ADD(HDMI3, 7, PIPELINE_PCM_7) - -# -# BE configurations - overrides config in ACPI if present -# - -#SSP 1 (ID: 0) with 19.2 MHz mclk with MCLK_ID 1 (unused), 1.536 MHz blck -DAI_CONFIG(SSP, 1, 0, SSP1-Codec, - SSP_CONFIG(I2S, SSP_CLOCK(mclk, 19200000, codec_mclk_in), - SSP_CLOCK(bclk, 1536000, codec_slave), - SSP_CLOCK(fsync, 48000, codec_slave), - SSP_TDM(2, 16, 3, 3), - SSP_CONFIG_DATA(SSP, 1, 16, 1))) - -ifelse(HEADPHONE, `da7219', ` -#SSP 2 (ID: 1) with 19.2 MHz mclk with MCLK_ID 1, 1.92 MHz bclk -DAI_CONFIG(SSP, 2, 1, SSP2-Codec, - SSP_CONFIG(I2S, SSP_CLOCK(mclk, 19200000, codec_mclk_in), - SSP_CLOCK(bclk, 1920000, codec_slave), - SSP_CLOCK(fsync, 48000, codec_slave), - SSP_TDM(2, 20, 3, 3), - SSP_CONFIG_DATA(SSP, 2, 16, 1))) -', HEADPHONE, `cs42l42', ` -#SSP 2 (ID: 1) with 19.2 MHz mclk with MCLK_ID 1 (unused), 2.4 MHz bclk, no quirk, 10 ms BCLK delay -DAI_CONFIG(SSP, 2, 1, SSP2-Codec, - SSP_CONFIG(I2S, SSP_CLOCK(mclk, 19200000, codec_mclk_in), - SSP_CLOCK(bclk, 2400000, codec_slave), - SSP_CLOCK(fsync, 48000, codec_slave), - SSP_TDM(2, 25, 3, 3), - SSP_CONFIG_DATA(SSP, 2, 24, 1, 0, 0, SSP_CC_BCLK_ES))) -', ) - -# dmic01 (id: 2) -DAI_CONFIG(DMIC, 0, 2, dmic01, - DMIC_CONFIG(1, 2400000, 4800000, 40, 60, 48000, - DMIC_WORD_LENGTH(s32le), 400, DMIC, 0, - PDM_CONFIG(DMIC, 0, FOUR_CH_PDM0_PDM1))) - -# 3 HDMI/DP outputs (ID: 3,4,5) -DAI_CONFIG(HDA, 3, 3, iDisp1, - HDA_CONFIG(HDA_CONFIG_DATA(HDA, 3, 48000, 2))) -DAI_CONFIG(HDA, 4, 4, iDisp2, - HDA_CONFIG(HDA_CONFIG_DATA(HDA, 4, 48000, 2))) -DAI_CONFIG(HDA, 5, 5, iDisp3, - HDA_CONFIG(HDA_CONFIG_DATA(HDA, 5, 48000, 2))) - -## remove warnings with SST hard-coded routes - -VIRTUAL_WIDGET(ssp1 Tx, out_drv, 0) -VIRTUAL_WIDGET(ssp2 Rx, out_drv, 1) -VIRTUAL_WIDGET(ssp2 Tx, out_drv, 2) -VIRTUAL_WIDGET(iDisp3 Tx, out_drv, 15) -VIRTUAL_WIDGET(iDisp2 Tx, out_drv, 16) -VIRTUAL_WIDGET(iDisp1 Tx, out_drv, 17) -VIRTUAL_WIDGET(DMIC01 Rx, out_drv, 3) -VIRTUAL_WIDGET(DMic, out_drv, 4) -VIRTUAL_WIDGET(dmic01_hifi, out_drv, 5) -VIRTUAL_WIDGET(hif5-0 Output, out_drv, 6) -VIRTUAL_WIDGET(hif6-0 Output, out_drv, 7) -VIRTUAL_WIDGET(hif7-0 Output, out_drv, 8) -VIRTUAL_WIDGET(iDisp3_out, out_drv, 9) -VIRTUAL_WIDGET(iDisp2_out, out_drv, 10) -VIRTUAL_WIDGET(iDisp1_out, out_drv, 11) -VIRTUAL_WIDGET(codec0_out, output, 12) -VIRTUAL_WIDGET(codec1_out, output, 13) -VIRTUAL_WIDGET(codec0_in, input, 14) diff --git a/tools/topology/topology1/sof-glk-rt5682.m4 b/tools/topology/topology1/sof-glk-rt5682.m4 deleted file mode 100644 index a732c6f0a515..000000000000 --- a/tools/topology/topology1/sof-glk-rt5682.m4 +++ /dev/null @@ -1,214 +0,0 @@ -# -# Topology for Geminilake with rt5682 headset on SSP2, max98357a spk on SSP1 -# -# Modified from: -# Geminilake topology for codecs da7219 headset on SSP2, max98357a spk on SSP1 -# - -# Include topology builder -include(`utils.m4') -include(`dai.m4') -include(`pipeline.m4') -include(`ssp.m4') -include(`hda.m4') - -# Include TLV library -include(`common/tlv.m4') - -# Include Token library -include(`sof/tokens.m4') - -# Include bxt DSP configuration -include(`platform/intel/bxt.m4') -include(`platform/intel/dmic.m4') - -# -# Define the pipelines -# -# PCM0 ----> volume (pipe 1) -----> SSP1 (speaker - maxim98357a, BE link 0) -# PCM1 <---> volume (pipe 2,3) <----> SSP2 (headset - rt5682, BE link 1) -# PCM99 <---- DMIC0 (dmic capture, BE link 2) -# PCM5 ----> volume (pipe 5) -----> iDisp1 (HDMI/DP playback, BE link 3) -# PCM6 ----> Volume (pipe 6) -----> iDisp2 (HDMI/DP playback, BE link 4) -# PCM7 ----> volume (pipe 7) -----> iDisp3 (HDMI/DP playback, BE link 5) -# - -dnl PIPELINE_PCM_ADD(pipeline, -dnl pipe id, pcm, max channels, format, -dnl period, priority, core, -dnl pcm_min_rate, pcm_max_rate, pipeline_rate, -dnl time_domain, sched_comp) - -# Low Latency playback pipeline 1 on PCM 0 using max 2 channels of s32le. -# 1000us deadline with priority 0 on core 0 -PIPELINE_PCM_ADD(sof/pipe-volume-playback.m4, - 1, 0, 2, s32le, - 1000, 0, 0, - 48000, 48000, 48000) - -# Low Latency playback pipeline 2 on PCM 1 using max 2 channels of s32le. -# 1000us deadline with priority 0 on core 0 -PIPELINE_PCM_ADD(sof/pipe-volume-playback.m4, - 2, 1, 2, s32le, - 1000, 0, 0, - 48000, 48000, 48000) - -# Low Latency capture pipeline 3 on PCM 1 using max 2 channels of s32le. -# 1000us deadline with priority 0 on core 0 -PIPELINE_PCM_ADD(sof/pipe-volume-capture.m4, - 3, 1, 2, s32le, - 1000, 0, 0, - 48000, 48000, 48000) - -# Low Latency capture pipeline 4 on PCM 99 using max 4 channels of s16le. -# 1000us deadline with priority 0 on core 0 -#PIPELINE_PCM_ADD(sof/pipe-volume-capture.m4, -PIPELINE_PCM_ADD(sof/pipe-passthrough-capture.m4, - 4, 99, 4, s16le, - 1000, 0, 0, - 48000, 48000, 48000) - -# Low Latency playback pipeline 5 on PCM 5 using max 2 channels of s16le. -# 1000us deadline with priority 0 on core 0 -# PIPELINE_PCM_ADD(sof/pipe-passthrough-playback.m4, -PIPELINE_PCM_ADD(sof/pipe-volume-playback.m4, - 5, 5, 2, s16le, - 1000, 0, 0, - 48000, 48000, 48000) - -# Low Latency playback pipeline 6 on PCM 6 using max 2 channels of s16le. -# 1000us deadline with priority 0 on core 0 -# PIPELINE_PCM_ADD(sof/pipe-passthrough-playback.m4, -PIPELINE_PCM_ADD(sof/pipe-volume-playback.m4, - 6, 6, 2, s16le, - 1000, 0, 0, - 48000, 48000, 48000) - -# Low Latency playback pipeline 7 on PCM 7 using max 2 channels of s16le. -# 1000us deadline with priority 0 on core 0 -# PIPELINE_PCM_ADD(sof/pipe-passthrough-playback.m4, -PIPELINE_PCM_ADD(sof/pipe-volume-playback.m4, - 7, 7, 2, s16le, - 1000, 0, 0, - 48000, 48000, 48000) - -# -# DAIs configuration -# - -dnl DAI_ADD(pipeline, -dnl pipe id, dai type, dai_index, dai_be, -dnl buffer, periods, format, -dnl deadline, priority, core, time_domain) - -# playback DAI is SSP1 using 2 periods -# Buffers use s16le format, 1000us deadline with priority 0 on core 0 -DAI_ADD(sof/pipe-dai-playback.m4, - 1, SSP, 1, SSP1-Codec, - PIPELINE_SOURCE_1, 2, s16le, - 1000, 0, 0, SCHEDULE_TIME_DOMAIN_TIMER) - -# playback DAI is SSP1 using 2 periods -# Buffers use s16le format, 1000us deadline with priority 0 on core 0 -DAI_ADD(sof/pipe-dai-playback.m4, - 2, SSP, 2, SSP2-Codec, - PIPELINE_SOURCE_2, 2, s16le, - 1000, 0, 0, SCHEDULE_TIME_DOMAIN_TIMER) - -# capture DAI is SSP1 using 2 periods -# Buffers use s16le format, 1000us deadline with priority 0 on core 0 -DAI_ADD(sof/pipe-dai-capture.m4, - 3, SSP, 2, SSP2-Codec, - PIPELINE_SINK_3, 2, s16le, - 1000, 0, 0, SCHEDULE_TIME_DOMAIN_TIMER) - -# capture DAI is DMIC0 using 2 periods -# Buffers use s16le format, 1000us deadline with priority 0 on core 0 -DAI_ADD(sof/pipe-dai-capture.m4, - 4, DMIC, 0, dmic01, - PIPELINE_SINK_4, 2, s16le, - 1000, 0, 0, SCHEDULE_TIME_DOMAIN_TIMER) - -# playback DAI is iDisp1 using 2 periods -# Buffers use s16le format, 1000us deadline with priority 0 on core 0 -DAI_ADD(sof/pipe-dai-playback.m4, - 5, HDA, 3, iDisp1, - PIPELINE_SOURCE_5, 2, s16le, - 1000, 0, 0, SCHEDULE_TIME_DOMAIN_TIMER) - -# playback DAI is iDisp2 using 2 periods -# Buffers use s16le format, 1000us deadline with priority 0 on core 0 -DAI_ADD(sof/pipe-dai-playback.m4, - 6, HDA, 4, iDisp2, - PIPELINE_SOURCE_6, 2, s16le, - 1000, 0, 0, SCHEDULE_TIME_DOMAIN_TIMER) - -# playback DAI is iDisp3 using 2 periods -# Buffers use s16le format, 1000us deadline with priority 0 on core 0 -DAI_ADD(sof/pipe-dai-playback.m4, - 7, HDA, 5, iDisp3, - PIPELINE_SOURCE_7, 2, s16le, - 1000, 0, 0, SCHEDULE_TIME_DOMAIN_TIMER) - -PCM_PLAYBACK_ADD(Speakers, 0, PIPELINE_PCM_1) -PCM_DUPLEX_ADD(Headset, 1, PIPELINE_PCM_2, PIPELINE_PCM_3) -PCM_CAPTURE_ADD(DMIC, 99, PIPELINE_PCM_4) -PCM_PLAYBACK_ADD(HDMI1, 5, PIPELINE_PCM_5) -PCM_PLAYBACK_ADD(HDMI2, 6, PIPELINE_PCM_6) -PCM_PLAYBACK_ADD(HDMI3, 7, PIPELINE_PCM_7) - -# -# BE configurations - overrides config in ACPI if present -# - -#SSP 1 (ID: 0) with 19.2 MHz mclk with MCLK_ID 1 (unused), 1.536 MHz blck -DAI_CONFIG(SSP, 1, 0, SSP1-Codec, - SSP_CONFIG(I2S, SSP_CLOCK(mclk, 19200000, codec_mclk_in), - SSP_CLOCK(bclk, 1536000, codec_slave), - SSP_CLOCK(fsync, 48000, codec_slave), - SSP_TDM(2, 16, 3, 3), - SSP_CONFIG_DATA(SSP, 1, 16, 1))) - -#SSP 2 (ID: 1) with 19.2 MHz mclk with MCLK_ID 1, 2.4 MHz bclk -DAI_CONFIG(SSP, 2, 1, SSP2-Codec, - SSP_CONFIG(I2S, SSP_CLOCK(mclk, 19200000, codec_mclk_in), - SSP_CLOCK(bclk, 2400000, codec_slave), - SSP_CLOCK(fsync, 48000, codec_slave), - SSP_TDM(2, 20, 3, 3), - SSP_CONFIG_DATA(SSP, 2, 16, 1))) - -# dmic01 (id: 2) -DAI_CONFIG(DMIC, 0, 2, dmic01, - DMIC_CONFIG(1, 2400000, 4800000, 40, 60, 48000, - DMIC_WORD_LENGTH(s16le), 400, DMIC, 0, - PDM_CONFIG(DMIC, 0, FOUR_CH_PDM0_PDM1))) - -# 3 HDMI/DP outputs (ID: 3,4,5) -DAI_CONFIG(HDA, 3, 3, iDisp1, - HDA_CONFIG(HDA_CONFIG_DATA(HDA, 3, 48000, 2))) -DAI_CONFIG(HDA, 4, 4, iDisp2, - HDA_CONFIG(HDA_CONFIG_DATA(HDA, 4, 48000, 2))) -DAI_CONFIG(HDA, 5, 5, iDisp3, - HDA_CONFIG(HDA_CONFIG_DATA(HDA, 5, 48000, 2))) - -## remove warnings with SST hard-coded routes - -VIRTUAL_WIDGET(ssp1 Tx, out_drv, 0) -VIRTUAL_WIDGET(ssp2 Rx, out_drv, 1) -VIRTUAL_WIDGET(ssp2 Tx, out_drv, 2) -VIRTUAL_WIDGET(iDisp3 Tx, out_drv, 16) -VIRTUAL_WIDGET(iDisp2 Tx, out_drv, 17) -VIRTUAL_WIDGET(iDisp1 Tx, out_drv, 18) -VIRTUAL_WIDGET(DMIC01 Rx, out_drv, 3) -VIRTUAL_WIDGET(DMIC AIF, input, 15) -VIRTUAL_WIDGET(DMic, out_drv, 4) -VIRTUAL_WIDGET(dmic01_hifi, out_drv, 5) -VIRTUAL_WIDGET(hif5-0 Output, out_drv, 6) -VIRTUAL_WIDGET(hif6-0 Output, out_drv, 7) -VIRTUAL_WIDGET(hif7-0 Output, out_drv, 8) -VIRTUAL_WIDGET(iDisp3_out, out_drv, 9) -VIRTUAL_WIDGET(iDisp2_out, out_drv, 10) -VIRTUAL_WIDGET(iDisp1_out, out_drv, 11) -VIRTUAL_WIDGET(codec0_out, output, 12) -VIRTUAL_WIDGET(codec1_out, output, 13) -VIRTUAL_WIDGET(codec0_in, input, 14) diff --git a/zephyr/CMakeLists.txt b/zephyr/CMakeLists.txt index 20af32be6a40..a6d991096628 100644 --- a/zephyr/CMakeLists.txt +++ b/zephyr/CMakeLists.txt @@ -112,79 +112,6 @@ zephyr_include_directories( # SOC level sources # Files that are commented may not be needed. -# Intel APL, KBL, SKL CAVS 1.5 platforms -if (CONFIG_SOC_SERIES_INTEL_CAVS_V15) - - # Driver sources - zephyr_library_sources( - ${SOF_DRIVERS_PATH}/intel/cavs/ipc.c - ) - - zephyr_library_sources_ifdef(CONFIG_INTEL_HDA - ${SOF_DRIVERS_PATH}/intel/hda/hda-dma.c - ) - - if (NOT CONFIG_ZEPHYR_NATIVE_DRIVERS) - zephyr_library_sources( - ${SOF_DRIVERS_PATH}/intel/cavs/timestamp.c - ) - - zephyr_library_sources_ifdef(CONFIG_INTEL_HDA - ${SOF_DRIVERS_PATH}/intel/hda/hda.c - ) - - zephyr_library_sources_ifdef(CONFIG_INTEL_MN - ${SOF_DRIVERS_PATH}/intel/ssp/mn.c - ) - - zephyr_library_sources_ifdef(CONFIG_INTEL_SSP - ${SOF_DRIVERS_PATH}/intel/ssp/ssp.c - ) - - zephyr_library_sources_ifdef(CONFIG_INTEL_ALH - ${SOF_DRIVERS_PATH}/intel/alh.c - ) - - zephyr_library_sources_ifdef(CONFIG_INTEL_DMIC - ${SOF_DRIVERS_PATH}/intel/dmic/dmic.c - ) - - zephyr_library_sources_ifdef(CONFIG_INTEL_DMIC_TPLG_PARAMS - ${SOF_DRIVERS_PATH}/intel/dmic/dmic_computed.c - ) - - zephyr_library_sources_ifdef(CONFIG_INTEL_DMIC_NHLT - ${SOF_DRIVERS_PATH}/intel/dmic/dmic_nhlt.c - ) - - zephyr_library_sources( - ${SOF_PLATFORM_PATH}/intel/cavs/lib/dai.c - ) - endif() - - # Platform sources - zephyr_library_sources( - ${SOF_PLATFORM_PATH}/intel/cavs/platform.c - ${SOF_PLATFORM_PATH}/intel/cavs/lib/mem_window.c - ${SOF_PLATFORM_PATH}/intel/cavs/lib/pm_runtime.c - ${SOF_PLATFORM_PATH}/intel/cavs/lib/pm_memory.c - ${SOF_PLATFORM_PATH}/intel/cavs/lib/clk.c - ${SOF_PLATFORM_PATH}/intel/cavs/lib/dma.c - ${SOF_PLATFORM_PATH}/apollolake/lib/power_down.S - ${SOF_PLATFORM_PATH}/apollolake/lib/clk.c - ) - - # SOF core infrastructure - runs on top of Zephyr - zephyr_library_sources( - ${SOF_SRC_PATH}/schedule/zephyr_ll.c - ) - - set_source_files_properties(${SOF_PLATFORM_PATH}/apollolake/lib/power_down.S PROPERTIES COMPILE_FLAGS -DASSEMBLY) - - set(PLATFORM "apollolake") - zephyr_include_directories(${SOF_PLATFORM_PATH}/intel/cavs/include) -endif() - # Intel CNL and CAVS 1.8 platfroms if (CONFIG_SOC_SERIES_INTEL_CAVS_V18)