diff --git a/app/boards/intel_adsp_ace30_ptl.conf b/app/boards/intel_adsp_ace30_ptl.conf new file mode 100644 index 000000000000..57d85f75ef44 --- /dev/null +++ b/app/boards/intel_adsp_ace30_ptl.conf @@ -0,0 +1,76 @@ +CONFIG_PANTHERLAKE=y +CONFIG_IPC_MAJOR_4=y +CONFIG_IPC4_BASE_FW_INTEL=y + +CONFIG_COMP_SRC=y +CONFIG_MM_DRV=y +CONFIG_COMP_SRC_IPC4_FULL_MATRIX=y + +# power settings +CONFIG_PM=y +CONFIG_PM_DEVICE=y +CONFIG_PM_DEVICE_RUNTIME=y +CONFIG_PM_DEVICE_POWER_DOMAIN=y +CONFIG_PM_POLICY_CUSTOM=y +CONFIG_ADSP_IMR_CONTEXT_SAVE=y + +CONFIG_POWER_DOMAIN=y +CONFIG_POWER_DOMAIN_INTEL_ADSP=y + +# enable Zephyr drivers +CONFIG_ZEPHYR_NATIVE_DRIVERS=y +CONFIG_DAI=y +CONFIG_DAI_INIT_PRIORITY=70 +CONFIG_DAI_INTEL_DMIC=y +CONFIG_DAI_DMIC_HW_IOCLK=38400000 +CONFIG_DAI_INTEL_DMIC_NHLT=y +CONFIG_DAI_DMIC_HAS_OWNERSHIP=n +CONFIG_DAI_DMIC_HAS_MULTIPLE_LINE_SYNC=y +CONFIG_DAI_INTEL_SSP=y +CONFIG_ZEPHYR_DP_SCHEDULER=y +CONFIG_DMA=y +CONFIG_DMA_INTEL_ADSP_GPDMA=n +CONFIG_DMA_DW_LLI_POOL_SIZE=50 +CONFIG_INTEL_MODULES=y +CONFIG_LIBRARY_MANAGER=y +CONFIG_INTEL_ADSP_TIMER=y + +CONFIG_HEAP_MEM_POOL_SIZE=8192 +CONFIG_L3_HEAP=y +CONFIG_RIMAGE_SIGNING_SCHEMA="ptl" + +CONFIG_FORMAT_CONVERT_HIFI3=n +CONFIG_PCM_CONVERTER_FORMAT_S16_C16_AND_S16_C32=y +CONFIG_PCM_CONVERTER_FORMAT_S16_C32_AND_S32_C32=y +CONFIG_PCM_CONVERTER_FORMAT_S16_C32_AND_S24_C32=y +CONFIG_PCM_CONVERTER_FORMAT_S24_C24_AND_S24_C32=y +CONFIG_PCM_CONVERTER_FORMAT_S24_C32_AND_S24_C24=y +CONFIG_PCM_CONVERTER_FORMAT_S16_C32_AND_S16_C32=y +CONFIG_LOG=y +CONFIG_LOG_MODE_DEFERRED=y +CONFIG_LOG_FUNC_NAME_PREFIX_ERR=y +CONFIG_LOG_FUNC_NAME_PREFIX_WRN=y +CONFIG_LOG_FUNC_NAME_PREFIX_INF=y +CONFIG_LOG_FUNC_NAME_PREFIX_DBG=y +CONFIG_COMP_VOLUME_WINDOWS_FADE=y +CONFIG_COMP_UP_DOWN_MIXER=y +CONFIG_COMP_CHAIN_DMA=y +CONFIG_SYS_CLOCK_TICKS_PER_SEC=12000 + +CONFIG_MM_DRV_INTEL_ADSP_TLB_REMAP_UNUSED_RAM=y + +CONFIG_LOG_BACKEND_ADSP_MTRACE=y +CONFIG_SOF_LOG_LEVEL_INF=y + +CONFIG_SOF_LOG_LEVEL_OFF=y +CONFIG_ZEPHYR_LOG=y +CONFIG_INTEL_ADSP_IPC=y + +CONFIG_CLOCK_CONTROL_ADSP=y +CONFIG_CLOCK_CONTROL=y + +CONFIG_COMP_KPB=y +CONFIG_COMP_ARIA=y + +# Temporary disabled options +CONFIG_TRACE=n diff --git a/app/boards/intel_adsp_ace30_ptl_sim.conf b/app/boards/intel_adsp_ace30_ptl_sim.conf new file mode 100644 index 000000000000..be8d2b52c59e --- /dev/null +++ b/app/boards/intel_adsp_ace30_ptl_sim.conf @@ -0,0 +1,66 @@ +CONFIG_PANTHERLAKE=y +CONFIG_IPC_MAJOR_4=y +CONFIG_IPC4_BASE_FW_INTEL=y + +# turn off SOF drivers +CONFIG_COMP_SRC=y + +CONFIG_COMP_SRC_IPC4_FULL_MATRIX=y + +# power settings +CONFIG_PM=n +CONFIG_PM_POLICY_CUSTOM=y + +# enable Zephyr drivers +CONFIG_ZEPHYR_NATIVE_DRIVERS=y +CONFIG_DAI=y +CONFIG_DAI_INIT_PRIORITY=70 +CONFIG_DAI_INTEL_DMIC=y +CONFIG_DAI_DMIC_HW_IOCLK=19200000 +CONFIG_DAI_INTEL_DMIC_NHLT=y +CONFIG_DAI_DMIC_HAS_OWNERSHIP=y +CONFIG_DAI_DMIC_HAS_MULTIPLE_LINE_SYNC=y +CONFIG_DAI_INTEL_SSP=n +CONFIG_DMA=y +CONFIG_DMA_INTEL_ADSP_GPDMA=n +CONFIG_DMA_DW_LLI_POOL_SIZE=50 +CONFIG_INTEL_MODULES=n +CONFIG_LIBRARY_MANAGER=n +CONFIG_INTEL_ADSP_TIMER=y + +CONFIG_HEAP_MEM_POOL_SIZE=8192 +CONFIG_RIMAGE_SIGNING_SCHEMA="ptl" + +CONFIG_FORMAT_CONVERT_HIFI3=n +CONFIG_PCM_CONVERTER_FORMAT_S16_C16_AND_S16_C32=y +CONFIG_PCM_CONVERTER_FORMAT_S16_C32_AND_S32_C32=y +CONFIG_PCM_CONVERTER_FORMAT_S16_C32_AND_S24_C32=y +CONFIG_PCM_CONVERTER_FORMAT_S24_C24_AND_S24_C32=y +CONFIG_PCM_CONVERTER_FORMAT_S24_C32_AND_S24_C24=y +CONFIG_PCM_CONVERTER_FORMAT_S16_C32_AND_S16_C32=y +CONFIG_LOG=n +CONFIG_LOG_MODE_DEFERRED=n +CONFIG_LOG_FUNC_NAME_PREFIX_INF=n +CONFIG_COMP_VOLUME_WINDOWS_FADE=y +CONFIG_COMP_UP_DOWN_MIXER=y +CONFIG_SYS_CLOCK_TICKS_PER_SEC=12000 +CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=19200000 + +CONFIG_LOG_BACKEND_ADSP_MTRACE=n +CONFIG_SOF_LOG_LEVEL_INF=n +CONFIG_SOF_LOG_LEVEL_OFF=y +CONFIG_ZEPHYR_LOG=n + +CONFIG_INTEL_ADSP_IPC=y + + +# Temporary disabled options +CONFIG_TRACE=n +CONFIG_PM_DEVICE=y +CONFIG_PM_DEVICE_RUNTIME=n +CONFIG_PM_DEVICE_POWER_DOMAIN=n +CONFIG_COMP_KPB=n + +CONFIG_CLOCK_CONTROL_ADSP=y +CONFIG_CLOCK_CONTROL=y +CONFIG_USERSPACE=y diff --git a/app/overlays/ptl/fpga_overlay.conf b/app/overlays/ptl/fpga_overlay.conf new file mode 100644 index 000000000000..1d09ecb6bd99 --- /dev/null +++ b/app/overlays/ptl/fpga_overlay.conf @@ -0,0 +1,3 @@ +CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=19200000 +CONFIG_DAI_DMIC_HW_IOCLK=19200000 + diff --git a/app/sample.yaml b/app/sample.yaml index 5a4611b71449..4dfa47824681 100644 --- a/app/sample.yaml +++ b/app/sample.yaml @@ -14,6 +14,8 @@ tests: - intel_adsp/cavs25 - intel_adsp/ace15_mtpm - intel_adsp/ace20_lnl + - intel_adsp/ace30_ptl + - intel_adsp/ace30_ptl_sim - imx8qm_mek/mimx8qm6/adsp - imx8qxp_mek/mimx8qx6/adsp - imx8mp_evk/mimx8ml8/adsp @@ -23,6 +25,8 @@ tests: - intel_adsp/cavs25 # TGL - intel_adsp/ace15_mtpm # MTL - intel_adsp/ace20_lnl + - intel_adsp/ace30_ptl + - intel_adsp/ace30_ptl_sim - imx8qm_mek/mimx8qm6/adsp - imx8qxp_mek/mimx8qx6/adsp - imx8mp_evk/mimx8ml8/adsp diff --git a/scripts/xtensa-build-zephyr.py b/scripts/xtensa-build-zephyr.py index c3419a9519fa..648393ed70ff 100755 --- a/scripts/xtensa-build-zephyr.py +++ b/scripts/xtensa-build-zephyr.py @@ -120,6 +120,18 @@ class PlatformConfig: "ace10_LX7HiFi4_2022_10", ipc4 = True ), + "ptl" : PlatformConfig( + "intel", "intel_adsp/ace30_ptl", + f"RI-2022.10{xtensa_tools_version_postfix}", + "ace30_LX7HiFi4_PIF", + ipc4 = True + ), + "ptl-sim" : PlatformConfig( + "intel", "intel_adsp/ace30_ptl_sim", + f"RI-2022.10{xtensa_tools_version_postfix}", + "ace30_LX7HiFi4_PIF", + ipc4 = True + ), # NXP platforms "imx8" : PlatformConfig( diff --git a/src/audio/asrc/asrc.toml b/src/audio/asrc/asrc.toml index 9e744452de20..0bf6ace59bd9 100644 --- a/src/audio/asrc/asrc.toml +++ b/src/audio/asrc/asrc.toml @@ -29,7 +29,7 @@ 13, 0, 0, 0, 20480, 31871000, 384, 192, 0, 31871, 0, 14, 0, 0, 0, 20480, 34216000, 384, 256, 0, 34216, 0, 15, 0, 0, 0, 20480, 83448000, 1536, 1440, 0, 83448, 0] -#elif CONFIG_LUNARLAKE +#elif defined(CONFIG_LUNARLAKE) || defined(CONFIG_PANTHERLAKE) mod_cfg = [0, 0, 0, 0, 20480, 4065600, 24, 22, 0, 0, 0, 1, 0, 0, 0, 20480, 5616000, 8, 25, 0, 0, 0, 2, 0, 0, 0, 20480, 7319200, 24, 27, 0, 0, 0, diff --git a/src/audio/copier/copier.toml b/src/audio/copier/copier.toml index 12977121f342..e7cd23f5154b 100644 --- a/src/audio/copier/copier.toml +++ b/src/audio/copier/copier.toml @@ -60,7 +60,7 @@ 40, 0, 0, 0, 280, 6246000, 32, 32, 0, 6246, 0, 41, 0, 0, 0, 280, 5272000, 192, 384, 0, 5272, 0, 42, 0, 0, 0, 280, 5350000, 384, 192, 0, 5350, 0] -#elif CONFIG_LUNARLAKE +#elif defined(CONFIG_LUNARLAKE) || defined(CONFIG_PANTHERLAKE) mod_cfg = [ 0, 0, 0, 0, 280, 640100, 45, 60, 0, 0, 0, 1, 0, 0, 0, 280, 1106300, 192, 192, 0, 0, 0, 2, 0, 0, 0, 280, 1573000, 45, 45, 0, 0, 0, diff --git a/src/audio/eq_iir/eq_iir.toml b/src/audio/eq_iir/eq_iir.toml index 441469af85a3..ad369d38edce 100644 --- a/src/audio/eq_iir/eq_iir.toml +++ b/src/audio/eq_iir/eq_iir.toml @@ -23,7 +23,7 @@ mod_cfg = [0, 0, 0, 0, 4096, 1000000, 128, 128, 0, 1000, 0, 0, 0, 0, 0, 4096, 20663000, 768, 768, 0, 20663, 0, 0, 0, 0, 0, 4096, 11357000, 384, 384, 0, 11357, 0] -#elif CONFIG_LUNARLAKE +#elif defined(CONFIG_LUNARLAKE) || defined(CONFIG_PANTHERLAKE) mod_cfg = [0, 0, 0, 0, 4096, 1000000, 128, 128, 0, 0, 0] #endif diff --git a/src/audio/mixin_mixout/mixin_mixout.toml b/src/audio/mixin_mixout/mixin_mixout.toml index e342706fa773..22a6d3e471e6 100644 --- a/src/audio/mixin_mixout/mixin_mixout.toml +++ b/src/audio/mixin_mixout/mixin_mixout.toml @@ -26,7 +26,7 @@ 3, 0, 0, 0, 296, 2928000, 512, 512, 0, 2928, 0, 4, 0, 0, 0, 296, 2572000, 128, 128, 0, 2572, 0, 5, 0, 0, 0, 296, 3760000, 1536, 1536, 0, 3760, 0] -#elif CONFIG_LUNARLAKE +#elif defined(CONFIG_LUNARLAKE) || defined(CONFIG_PANTHERLAKE) mod_cfg = [ 0, 0, 0, 0, 296, 644000, 45, 60, 0, 0, 0, 1, 0, 0, 0, 296, 669900, 48, 64, 0, 0, 0, 2, 0, 0, 0, 296, 934000, 96, 128, 0, 0, 0, @@ -70,7 +70,7 @@ 3, 0, 0, 0, 520, 7631000, 512, 512, 0, 7631, 0, 4, 0, 0, 0, 520, 1953000, 128, 128, 0, 1953, 0, 5, 0, 0, 0, 520, 2301000, 1536, 1536, 0, 2301, 0] -#elif CONFIG_LUNARLAKE +#elif defined(CONFIG_LUNARLAKE) || defined(CONFIG_PANTHERLAKE) mod_cfg = [0, 0, 0, 0, 520, 649600, 48, 64, 0, 0, 0, 1, 0, 0, 0, 520, 966300, 96, 128, 0, 0, 0, 2, 0, 0, 0, 520, 2101000, 48, 64, 0, 0, 0, diff --git a/src/audio/selector/selector.toml b/src/audio/selector/selector.toml index 45ce65a83213..e93327242579 100644 --- a/src/audio/selector/selector.toml +++ b/src/audio/selector/selector.toml @@ -18,7 +18,7 @@ mod_cfg = [0, 0, 0, 0, 960, 488500, 16, 16, 0, 0, 0, 1, 0, 0, 0, 960, 964500, 16, 16, 0, 0, 0, 2, 0, 0, 0, 960, 2003000, 16, 16, 0, 0, 0] -#elif CONFIG_LUNARLAKE +#elif defined(CONFIG_LUNARLAKE) || defined(CONFIG_PANTHERLAKE) mod_cfg = [0, 0, 0, 0, 216, 706000, 12, 16, 0, 0, 0, 1, 0, 0, 0, 216, 1271000, 8, 8, 0, 0, 0, 2, 0, 0, 0, 216, 1839000, 89, 118, 0, 0, 0, diff --git a/src/audio/src/src.toml b/src/audio/src/src.toml index 1568491051de..9cd67f28d9ce 100644 --- a/src/audio/src/src.toml +++ b/src/audio/src/src.toml @@ -41,7 +41,7 @@ 24, 0, 0, 0, 12832, 27696000, 180, 256, 0, 27696, 0, 25, 0, 0, 0, 12832, 18368000, 256, 512, 0, 18368, 0, 26, 0, 0, 0, 12832, 15204000, 128, 256, 0, 15204, 0] -#elif CONFIG_LUNARLAKE +#elif defined(CONFIG_LUNARLAKE) || defined(CONFIG_PANTHERLAKE) mod_cfg = [0, 0, 0, 0, 12832, 1365500, 0, 0, 0, 1365, 0, 1, 0, 0, 0, 12832, 2302300, 0, 0, 0, 2302, 0, 2, 0, 0, 0, 12832, 3218200, 0, 0, 0, 3218, 0, diff --git a/src/audio/up_down_mixer/up_down_mixer.toml b/src/audio/up_down_mixer/up_down_mixer.toml index 117d6a115069..34a1bf586188 100644 --- a/src/audio/up_down_mixer/up_down_mixer.toml +++ b/src/audio/up_down_mixer/up_down_mixer.toml @@ -45,7 +45,7 @@ 28, 0, 0, 0, 216, 5080000, 1536, 1152, 0, 5080, 0, 29, 0, 0, 0, 216, 3552000, 384, 1536, 0, 3552, 0, 30, 0, 0, 0, 216, 3728000, 768, 1152, 0, 3728, 0] -#elif CONFIG_LUNARLAKE +#elif defined(CONFIG_LUNARLAKE) || defined(CONFIG_PANTHERLAKE) mod_cfg = [0, 0, 0, 0, 216, 706000, 12, 16, 0, 0, 0, 1, 0, 0, 0, 216, 1271000, 8, 8, 0, 0, 0, 2, 0, 0, 0, 216, 1839000, 89, 118, 0, 0, 0, diff --git a/src/audio/volume/gain.toml b/src/audio/volume/gain.toml index 64894fa9ce7f..1bd8defc4e2b 100644 --- a/src/audio/volume/gain.toml +++ b/src/audio/volume/gain.toml @@ -20,7 +20,7 @@ 3, 0, 0, 0, 416, 8192000, 512, 512, 0, 8192, 0, 4, 0, 0, 0, 416, 10091000, 128, 128, 0, 10091, 0, 5, 0, 0, 0, 416, 5908000, 768, 768, 0, 5908, 0] -#elif CONFIG_LUNARLAKE +#elif defined(CONFIG_LUNARLAKE) || defined(CONFIG_PANTHERLAKE) mod_cfg = [0, 0, 0, 0, 416, 914000, 48, 64, 0, 0, 0, 1, 0, 0, 0, 416, 1321600, 192, 256, 0, 0, 0, 2, 0, 0, 0, 416, 1786000, 192, 256, 0, 0, 0, diff --git a/src/audio/volume/peakvol.toml b/src/audio/volume/peakvol.toml index 7eb9fe739e8e..c7a3bea647f3 100644 --- a/src/audio/volume/peakvol.toml +++ b/src/audio/volume/peakvol.toml @@ -20,7 +20,7 @@ 3, 0, 0, 0, 480, 12567000, 720, 720, 0, 12567, 0, 4, 0, 0, 0, 480, 7360000, 768, 768, 0, 7360, 0, 5, 0, 0, 0, 480, 12236000, 1536, 1536, 0, 12236, 0] -#elif CONFIG_LUNARLAKE +#elif defined(CONFIG_LUNARLAKE) || defined(CONFIG_PANTHERLAKE) mod_cfg = [0, 0, 0, 0, 480, 1114000, 48, 64, 0, 0, 0, 1, 0, 0, 0, 480, 3321600, 192, 256, 0, 0, 0, 2, 0, 0, 0, 480, 3786000, 192, 256, 0, 0, 0, diff --git a/src/ipc/ipc4/dai.c b/src/ipc/ipc4/dai.c index 10db13e687a0..8a0cdb7fcd58 100644 --- a/src/ipc/ipc4/dai.c +++ b/src/ipc/ipc4/dai.c @@ -36,7 +36,7 @@ void dai_set_link_hda_config(uint16_t *link_config, struct ipc_config_dai *common_config, const void *spec_config) { -#if defined(CONFIG_ACE_VERSION_2_0) +#if ACE_VERSION > ACE_VERSION_1_5 const struct ipc4_audio_format *out_fmt = common_config->out_fmt; union hdalink_cfg link_cfg; @@ -78,13 +78,13 @@ int dai_config_dma_channel(struct dai_data *dd, struct comp_dev *dev, const void COMPILER_FALLTHROUGH; case SOF_DAI_INTEL_DMIC: channel = 0; -#if defined(CONFIG_ACE_VERSION_2_0) +#if ACE_VERSION > ACE_VERSION_1_5 if (dai->host_dma_config[0]->pre_allocated_by_host) channel = dai->host_dma_config[0]->dma_channel_id; #endif break; case SOF_DAI_INTEL_HDA: -#if defined(CONFIG_ACE_VERSION_2_0) +#if ACE_VERSION > ACE_VERSION_1_5 if (copier_cfg->gtw_cfg.node_id.f.dma_type == ipc4_alh_link_output_class || copier_cfg->gtw_cfg.node_id.f.dma_type == ipc4_alh_link_input_class) { struct processing_module *mod = comp_mod(dev); @@ -106,7 +106,7 @@ int dai_config_dma_channel(struct dai_data *dd, struct comp_dev *dev, const void } break; } -#endif /* defined(CONFIG_ACE_VERSION_2_0) */ +#endif /* ACE_VERSION > ACE_VERSION_1_5 */ channel = copier_cfg->gtw_cfg.node_id.f.v_index; break; case SOF_DAI_INTEL_ALH: diff --git a/src/ipc/ipc4/helper.c b/src/ipc/ipc4/helper.c index 08f6298c88f1..aa6505218854 100644 --- a/src/ipc/ipc4/helper.c +++ b/src/ipc/ipc4/helper.c @@ -1076,7 +1076,7 @@ int ipc4_add_comp_dev(struct comp_dev *dev) int ipc4_find_dma_config(struct ipc_config_dai *dai, uint8_t *data_buffer, uint32_t size) { -#if defined(CONFIG_ACE_VERSION_2_0) +#if ACE_VERSION > ACE_VERSION_1_5 uint32_t *dma_config_id = GET_IPC_DMA_CONFIG_ID(data_buffer, size); if (*dma_config_id != GTW_DMA_CONFIG_ID) diff --git a/src/platform/Kconfig b/src/platform/Kconfig index 5e675315d2a3..760a1790d3f2 100644 --- a/src/platform/Kconfig +++ b/src/platform/Kconfig @@ -16,7 +16,6 @@ config TIGERLAKE help Select if your target platform is Tigerlake-compatible - config METEORLAKE bool "Build for Meteorlake" select ACE @@ -31,6 +30,13 @@ config LUNARLAKE help Select if your target platform is Lunarlake-compatible +config PANTHERLAKE + bool "Build for Pantherlake" + select ACE + select ACE_VERSION_3_0 + help + Select if your target platform is Pantherlake-compatible + config LIBRARY bool "Build Library" help @@ -249,6 +255,7 @@ endchoice config MAX_CORE_COUNT int default 5 if LUNARLAKE + default 5 if PANTHERLAKE default 4 if TIGERLAKE default 3 if METEORLAKE default 1 @@ -338,6 +345,12 @@ config ACE_VERSION_2_0 help Select for ACE version 2.0 +config ACE_VERSION_3_0 + depends on ACE + bool + help + Select for ACE version 3.0 + config HP_MEMORY_BANKS int "HP memory banks count" depends on CAVS diff --git a/src/platform/intel/ace/include/ace/version.h b/src/platform/intel/ace/include/ace/version.h index adf262c31bbc..1a1aa52381d7 100644 --- a/src/platform/intel/ace/include/ace/version.h +++ b/src/platform/intel/ace/include/ace/version.h @@ -8,6 +8,19 @@ #ifndef __ACE_VERSION_H__ #define __ACE_VERSION_H__ -#define HW_CFG_VERSION 0 +#define ACE_VERSION_1_5 0x10500 /* MTL */ +#define ACE_VERSION_2_0 0x20000 /* LNL */ +#define ACE_VERSION_3_0 0x30000 /* PTL */ + +/* ACE version defined by CONFIG_ACE_VER_*/ +#if defined(CONFIG_ACE_VERSION_1_5) +#define ACE_VERSION ACE_VERSION_1_5 +#elif defined(CONFIG_ACE_VERSION_2_0) +#define ACE_VERSION ACE_VERSION_2_0 +#elif defined(CONFIG_ACE_VERSION_3_0) +#define ACE_VERSION ACE_VERSION_3_0 +#endif + +#define HW_CFG_VERSION ACE_VERSION #endif /* __ACE_VERSION_H__ */ diff --git a/src/platform/pantherlake/include/platform/lib/clk.h b/src/platform/pantherlake/include/platform/lib/clk.h new file mode 100644 index 000000000000..245a515b9dd5 --- /dev/null +++ b/src/platform/pantherlake/include/platform/lib/clk.h @@ -0,0 +1,41 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * + * Copyright(c) 2022-2024 Intel Corporation. + * + * Author: Liam Girdwood + * Keyon Jie + * Rander Wang + */ + +#ifdef __SOF_LIB_CLK_H__ + +#ifndef __PLATFORM_LIB_CLK_H__ +#define __PLATFORM_LIB_CLK_H__ + +#include + +#define CLK_MAX_CPU_HZ CONFIG_XTENSA_CCOUNT_HZ + +#define CPU_WOVCRO_FREQ_IDX 0 + +#define CPU_LPRO_FREQ_IDX 1 + +#define CPU_HPRO_FREQ_IDX 2 + +#define CPU_LOWEST_FREQ_IDX CPU_WOVCRO_FREQ_IDX + +#define CPU_DEFAULT_IDX CPU_HPRO_FREQ_IDX + +#define SSP_DEFAULT_IDX 1 + +#define NUM_CPU_FREQ 3 + +#define NUM_SSP_FREQ 3 + +#endif /* __PLATFORM_LIB_CLK_H__ */ + +#else + +#error "This file shouldn't be included from outside of sof/lib/clk.h" + +#endif /* __SOF_LIB_CLK_H__ */ diff --git a/src/platform/pantherlake/include/platform/lib/cpu.h b/src/platform/pantherlake/include/platform/lib/cpu.h new file mode 100644 index 000000000000..19590911ea99 --- /dev/null +++ b/src/platform/pantherlake/include/platform/lib/cpu.h @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * + * Copyright(c) 2022-2024 Intel Corporation. + */ + +/** + * \file + * \brief DSP core parameters. + */ + +#ifdef __SOF_LIB_CPU_H__ + +#ifndef __PLATFORM_LIB_CPU_H__ +#define __PLATFORM_LIB_CPU_H__ + +#include + +#endif /* __PLATFORM_LIB_CPU_H__ */ + +#else + +#error "This file shouldn't be included from outside of sof/lib/cpu.h" + +#endif /* __SOF_LIB_CPU_H__ */ diff --git a/src/platform/pantherlake/include/platform/lib/dai.h b/src/platform/pantherlake/include/platform/lib/dai.h new file mode 100644 index 000000000000..cce32b808cf7 --- /dev/null +++ b/src/platform/pantherlake/include/platform/lib/dai.h @@ -0,0 +1,46 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * + * Copyright(c) 2022-2024 Intel Corporation. + * + * Author: Marcin Maka + */ + +#ifdef __SOF_LIB_DAI_H__ + +#ifndef __PLATFORM_LIB_DAI_H__ +#define __PLATFORM_LIB_DAI_H__ + +/* SSP */ + +/* + * Number of base and extended SSP ports must be defined separately + * since some HW registers are in two groups, one for base and one + * for extended. + */ + +/** \brief Number of 'base' SSP ports available */ +#define DAI_NUM_SSP_BASE 6 + +/* HD/A */ + +/** \brief Number of HD/A Link Outputs */ +#define DAI_NUM_HDA_OUT 9 + +/** \brief Number of HD/A Link Inputs */ +#define DAI_NUM_HDA_IN 11 + +/* ALH */ + +/** \brief Number of ALH bi-directional links */ +#define DAI_NUM_ALH_BI_DIR_LINKS 0 + +/** \brief Number of contiguous ALH bi-dir links */ +#define DAI_NUM_ALH_BI_DIR_LINKS_GROUP 0 + +#endif /* __PLATFORM_LIB_DAI_H__ */ + +#else + +#error "This file shouldn't be included from outside of sof/lib/dai.h" + +#endif /* __SOF_LIB_DAI_H__ */ diff --git a/src/platform/pantherlake/include/platform/lib/dma.h b/src/platform/pantherlake/include/platform/lib/dma.h new file mode 100644 index 000000000000..48a37b2b635a --- /dev/null +++ b/src/platform/pantherlake/include/platform/lib/dma.h @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * + * Copyright(c) 2022-2024 Intel Corporation. + */ + +#ifdef __SOF_LIB_DMA_H__ + +#ifndef __PLATFORM_LIB_DMA_H__ +#define __PLATFORM_LIB_DMA_H__ + +/* max number of supported DMA channels */ +#define PLATFORM_MAX_DMA_CHAN 9 + +/* number of supported DMACs */ +#define PLATFORM_NUM_DMACS 6 + +#endif /* __PLATFORM_LIB_DMA_H__ */ + +#else + +#error "This file shouldn't be included from outside of sof/lib/dma.h" + +#endif /* __SOF_LIB_DMA_H__ */ diff --git a/src/platform/pantherlake/include/platform/lib/mailbox.h b/src/platform/pantherlake/include/platform/lib/mailbox.h new file mode 100644 index 000000000000..7d253fd9327e --- /dev/null +++ b/src/platform/pantherlake/include/platform/lib/mailbox.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * + * Copyright(c) 2022-2024 Intel Corporation. + */ + +#ifdef __SOF_LIB_MAILBOX_H__ + +#ifndef __PLATFORM_LIB_MAILBOX_H__ +#define __PLATFORM_LIB_MAILBOX_H__ + +#include + +#endif /* __PLATFORM_LIB_MAILBOX_H__ */ + +#else + +#error "This file shouldn't be included from outside of sof/lib/mailbox.h" + +#endif /* __SOF_LIB_MAILBOX_H__ */ diff --git a/src/platform/pantherlake/include/platform/lib/memory.h b/src/platform/pantherlake/include/platform/lib/memory.h new file mode 100644 index 000000000000..6232b77af907 --- /dev/null +++ b/src/platform/pantherlake/include/platform/lib/memory.h @@ -0,0 +1,67 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * + * Copyright(c) 2022-2024 Intel Corporation. + * + * Author: Marcin Rajwa + */ + +#ifdef __SOF_LIB_MEMORY_H__ + +#ifndef __PLATFORM_LIB_MEMORY_H__ +#define __PLATFORM_LIB_MEMORY_H__ + +/* prioritize definitions in Zephyr SoC layer */ +#ifdef __ZEPHYR__ +#include +#endif + +#include +#include +#include + +/* HP SRAM windows */ +#define WIN_BASE(n) DT_REG_ADDR(DT_PHANDLE(MEM_WINDOW_NODE(n), memory)) + +/* window 0 */ +#define SRAM_SW_REG_BASE ((uint32_t)(WIN_BASE(0) + WIN0_OFFSET)) +#define SRAM_SW_REG_SIZE 0x1000 + +#define SRAM_OUTBOX_BASE (SRAM_SW_REG_BASE + SRAM_SW_REG_SIZE) +#define SRAM_OUTBOX_SIZE 0x1000 + +/* window 1 */ +#define SRAM_INBOX_BASE ((uint32_t)(WIN_BASE(1) + WIN1_OFFSET)) +#define SRAM_INBOX_SIZE ((uint32_t)WIN_SIZE(1)) + +/* window 2 */ +#define SRAM_DEBUG_BASE ((uint32_t)(WIN_BASE(2) + WIN2_OFFSET)) +#define SRAM_DEBUG_SIZE 0x800 + +#define SRAM_EXCEPT_BASE (SRAM_DEBUG_BASE + SRAM_DEBUG_SIZE) +#define SRAM_EXCEPT_SIZE 0x800 + +#define SRAM_STREAM_BASE (SRAM_EXCEPT_BASE + SRAM_EXCEPT_SIZE) +#define SRAM_STREAM_SIZE 0x1000 + +/* Stack configuration */ +#define SOF_STACK_SIZE 0x1000 + +#define PLATFORM_HEAP_SYSTEM CONFIG_CORE_COUNT /* one per core */ +#define PLATFORM_HEAP_SYSTEM_RUNTIME CONFIG_CORE_COUNT /* one per core */ +#define PLATFORM_HEAP_RUNTIME 1 +#define PLATFORM_HEAP_RUNTIME_SHARED 1 +#define PLATFORM_HEAP_SYSTEM_SHARED 1 +#define PLATFORM_HEAP_BUFFER 2 + +/** + * size of HPSRAM system heap + */ +#define HEAPMEM_SIZE 0xD0000 + +#endif /* __PLATFORM_LIB_MEMORY_H__ */ + +#else + +#error "This file shouldn't be included from outside of sof/lib/memory.h" + +#endif /* __SOF_LIB_MEMORY_H__ */ diff --git a/src/platform/pantherlake/include/platform/lib/pm_runtime.h b/src/platform/pantherlake/include/platform/lib/pm_runtime.h new file mode 100644 index 000000000000..edb1ebdeee49 --- /dev/null +++ b/src/platform/pantherlake/include/platform/lib/pm_runtime.h @@ -0,0 +1,72 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * + * Copyright(c) 2022-2024 Intel Corporation. + * + * Author: Tomasz Lauda + */ + +/** + * \file platform/pantherlake/include/platform/lib/pm_runtime.h + * \brief Runtime power management header file for Tigerlake + * \author Tomasz Lauda + */ + +#ifdef __SOF_LIB_PM_RUNTIME_H__ + +#ifndef __PLATFORM_LIB_PM_RUNTIME_H__ +#define __PLATFORM_LIB_PM_RUNTIME_H__ + +#include +#include + +/** + * \brief extra pwr flag to power up a core with a specific reason + * it can be powered down only with the same reason (flag) + */ +#define PWRD_MASK MASK(31, 30) +#define PWRD_BY_HPRO BIT(31) /**< requested by HPRO */ +#define PWRD_BY_TPLG BIT(30) /**< typical power up */ + +struct pm_runtime_data; + +/** + * \brief Initializes platform specific runtime power management. + * \param[in,out] prd Runtime power management data. + */ +void platform_pm_runtime_init(struct pm_runtime_data *prd); + +/** + * \brief Retrieves platform specific power management resource. + * + * \param[in] context Type of power management context. + * \param[in] index of the device. + * \param[in] flags, set of RPM_... + */ +void platform_pm_runtime_get(uint32_t context, uint32_t index, uint32_t flags); + +/** + * \brief Releases platform specific power management resource. + * + * \param[in] context Type of power management context. + * \param[in] index of the device. + * \param[in] flags, set of RPM_... + */ +void platform_pm_runtime_put(uint32_t context, uint32_t index, uint32_t flags); + +void platform_pm_runtime_prepare_d0ix_en(uint32_t index); + +void platform_pm_runtime_enable(uint32_t context, uint32_t index); + +void platform_pm_runtime_disable(uint32_t context, uint32_t index); + +bool platform_pm_runtime_is_active(uint32_t context, uint32_t index); + +void platform_pm_runtime_power_off(void); + +#endif /* __PLATFORM_LIB_PM_RUNTIME_H__ */ + +#else + +#error "This file shouldn't be included from outside of sof/lib/pm_runtime.h" + +#endif /* __SOF_LIB_PM_RUNTIME_H__ */ diff --git a/src/platform/pantherlake/include/platform/lib/shim.h b/src/platform/pantherlake/include/platform/lib/shim.h new file mode 100644 index 000000000000..175b8af24980 --- /dev/null +++ b/src/platform/pantherlake/include/platform/lib/shim.h @@ -0,0 +1,58 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * + * Copyright(c) 2022-2024 Intel Corporation. + * + * Author: Liam Girdwood + * Keyon Jie + * Rander Wang + */ + +#ifdef __SOF_LIB_SHIM_H__ + +#ifndef __PLATFORM_LIB_SHIM_H__ +#define __PLATFORM_LIB_SHIM_H__ + +#include +#include + +/** \brief Request HP RING Oscillator Clock */ +#define SHIM_CLKCTL_RHROSCC BIT(31) + +/** \brief Request WOVCRO Clock */ +#define SHIM_CLKCTL_WOV_CRO_REQUEST BIT(4) + +/** \brief Request LP RING Oscillator Clock */ +#define SHIM_CLKCTL_RLROSCC BIT(29) + +/** \brief Oscillator Clock Select*/ +#define SHIM_CLKCTL_OCS_HP_RING BIT(2) +#define SHIM_CLKCTL_OCS_LP_RING 0 +#define SHIM_CLKCTL_WOVCROSC BIT(3) + +/** \brief LP Memory Clock Select */ +#define SHIM_CLKCTL_LMCS_DIV4 BIT(1) + +/** \brief HP Memory Clock Select */ +#define SHIM_CLKCTL_HMCS_DIV2 0 + +/** \brief HP RING Oscillator Clock Status */ +#define SHIM_CLKSTS_HROSCCS BIT(31) + +/** \brief WOVCRO Clock Status */ +#define SHIM_CLKSTS_WOV_CRO BIT(4) + +/** \brief LP RING Oscillator Clock Status */ +#define SHIM_CLKSTS_LROSCCS BIT(29) + +#define L2HSBPM(x) (0x17A800 + 0x0008 * (x)) +#define SHIM_HSPGCTL(x) (L2HSBPM(x) + 0x0000) + +#define LSPGCTL 0x71D80 + +#endif /* __PLATFORM_LIB_SHIM_H__ */ + +#else + +#error "This file shouldn't be included from outside of sof/lib/shim.h" + +#endif /* __SOF_LIB_SHIM_H__ */ diff --git a/src/platform/pantherlake/include/platform/platform.h b/src/platform/pantherlake/include/platform/platform.h new file mode 100644 index 000000000000..352061fb4bf3 --- /dev/null +++ b/src/platform/pantherlake/include/platform/platform.h @@ -0,0 +1,46 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * + * Copyright(c) 2022-2024 Intel Corporation. + * + * Author: Liam Girdwood + * Keyon Jie + * Rander Wang + * Xiuli Pan + */ + +#ifdef __SOF_PLATFORM_H__ + +#ifndef __PLATFORM_PLATFORM_H__ +#define __PLATFORM_PLATFORM_H__ + +#include + +/*! \def PLATFORM_DEFAULT_CLOCK + * \brief clock source for audio pipeline + * + * There are two types of clock: cpu clock which is a internal clock in + * xtensa core, and ssp clock which is provided by external HW IP. + * The choice depends on HW features on different platform + */ +#define PLATFORM_DEFAULT_CLOCK CLK_SSP + +/* Host page size */ +#define HOST_PAGE_SIZE 4096 + +/* Platform stream capabilities */ +#define PLATFORM_MAX_CHANNELS 8 +#define PLATFORM_MAX_STREAMS 16 + +/* local buffer size of DMA tracing */ +#define DMA_TRACE_LOCAL_SIZE (HOST_PAGE_SIZE * 2) + +/* DSP default delay in cycles */ +#define PLATFORM_DEFAULT_DELAY 12 + +#endif /* __PLATFORM_PLATFORM_H__ */ + +#else + +#error "This file shouldn't be included from outside of sof/platform.h" + +#endif /* __SOF_PLATFORM_H__ */ diff --git a/src/platform/pantherlake/include/platform/trace/trace.h b/src/platform/pantherlake/include/platform/trace/trace.h new file mode 100644 index 000000000000..2e1e6022854f --- /dev/null +++ b/src/platform/pantherlake/include/platform/trace/trace.h @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * + * Copyright(c) 2022-2024 Intel Corporation. + */ + +#ifdef __SOF_TRACE_TRACE_H__ + +#ifndef __PLATFORM_TRACE_TRACE_H__ +#define __PLATFORM_TRACE_TRACE_H__ + +#include +#include +#include +#include + +/* Platform defined trace code */ +static inline void platform_trace_point(uint32_t x) +{ } + +#endif /* __PLATFORM_TRACE_TRACE_H__ */ + +#else + +#error "This file shouldn't be included from outside of sof/trace/trace.h" + +#endif /* __SOF_TRACE_TRACE_H__ */ diff --git a/src/platform/pantherlake/lib/clk.c b/src/platform/pantherlake/lib/clk.c new file mode 100644 index 000000000000..34fd9e7f653f --- /dev/null +++ b/src/platform/pantherlake/lib/clk.c @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: BSD-3-Clause +// +// Copyright(c) 2022-2024 Intel Corporation. +// +// Author: Tomasz Lauda +// Janusz Jankowski + +#include +#include + +static const struct freq_table platform_cpu_freq[] = { + { 38400000, 38400 }, + { 120000000, 120000 }, + { CLK_MAX_CPU_HZ, 400000 }, +}; + +STATIC_ASSERT(ARRAY_SIZE(platform_cpu_freq) == NUM_CPU_FREQ, invalid_number_of_cpu_frequencies); + +const struct freq_table *cpu_freq = platform_cpu_freq; diff --git a/src/samples/audio/smart_amp_test.toml b/src/samples/audio/smart_amp_test.toml index 6862391af9c2..39f2a76c47a8 100644 --- a/src/samples/audio/smart_amp_test.toml +++ b/src/samples/audio/smart_amp_test.toml @@ -23,7 +23,7 @@ REM # mod_cfg [PAR_0 PAR_1 PAR_2 PAR_3 IS_BYTES CPS IBS OBS MOD_FLAGS CPC OBLS] #ifdef CONFIG_METEORLAKE mod_cfg = [0, 0, 0, 0, 296, 5000000, 384, 384, 0, 5000, 0] -#elif CONFIG_LUNARLAKE +#elif defined(CONFIG_LUNARLAKE) || defined(CONFIG_PANTHERLAKE) mod_cfg = [0, 0, 0, 0, 4096, 1000000, 128, 128, 0, 0, 0] #endif diff --git a/tools/rimage/config/platform-ptl.toml b/tools/rimage/config/platform-ptl.toml new file mode 100644 index 000000000000..e32b9a1776f9 --- /dev/null +++ b/tools/rimage/config/platform-ptl.toml @@ -0,0 +1,56 @@ +version = [3, 0] + +[adsp] +name = "ptl" +image_size = "0x2C0000" # (22) bank * 128KB +alias_mask = "0xE0000000" + +[[adsp.mem_zone]] +type = "ROM" +base = "0x1FF80000" +size = "0x400" +[[adsp.mem_zone]] +type = "IMR" +base = "0xA104A000" +size = "0x2000" +[[adsp.mem_zone]] +type = "SRAM" +base = "0xa00f0000" +size = "0x100000" + +[[adsp.mem_alias]] +type = "uncached" +base = "0x40000000" +[[adsp.mem_alias]] +type = "cached" +base = "0xA0000000" + +[cse] +partition_name = "ADSP" +[[cse.entry]] +name = "ADSP.man" +offset = "0x5c" +length = "0x4b8" +[[cse.entry]] +name = "ADSP.met" +offset = "0x4c0" +length = "0x70" +[[cse.entry]] +name = "ADSP" +offset = "0x540" +length = "0x0" # calculated by rimage + +[css] + +[signed_pkg] +name = "ADSP" +[[signed_pkg.module]] +name = "ADSP.met" + +[adsp_file] +[[adsp_file.comp]] +base_offset = "0x2000" + +[fw_desc.header] +name = "ADSPFW" +load_offset = "0x40000" diff --git a/tools/rimage/config/ptl.toml.h b/tools/rimage/config/ptl.toml.h new file mode 100644 index 000000000000..377bf22dd66e --- /dev/null +++ b/tools/rimage/config/ptl.toml.h @@ -0,0 +1,124 @@ +#include "platform-ptl.toml" + +[[module.entry]] +name = "BRNGUP" +uuid = "2B79E4F3-4675-F649-89DF-3BC194A91AEB" +affinity_mask = "0x1" +instance_count = "1" +domain_types = "0" +load_type = "0" +module_type = "0" +auto_start = "0" + +index = __COUNTER__ + +[[module.entry]] +name = "BASEFW" +uuid = "0E398C32-5ADE-BA4B-93B1-C50432280EE4" +affinity_mask = "3" +instance_count = "1" +domain_types = "0" +load_type = "0" +module_type = "0" +auto_start = "0" + +index = __COUNTER__ + +#ifdef CONFIG_COMP_MIXIN_MIXOUT +#include