From 8319b673678e7c5c0de403f4a60249a4ddee0729 Mon Sep 17 00:00:00 2001 From: Kai Vehmanen Date: Tue, 4 Jun 2024 19:57:54 +0300 Subject: [PATCH] app: boards: ace20_lnl: set DMA_INTEL_ADSP_HDA_TIMING_L1_EXIT=y Set CONFIG_DMA_INTEL_ADSP_HDA_TIMING_L1_EXIT in board overlay as the Zephyr platform default is not correct in the current version of Zephyr. Link: https://github.com/thesofproject/sof/issues/9191 Signed-off-by: Kai Vehmanen --- app/boards/intel_adsp_ace20_lnl.conf | 3 +++ 1 file changed, 3 insertions(+) diff --git a/app/boards/intel_adsp_ace20_lnl.conf b/app/boards/intel_adsp_ace20_lnl.conf index 81bb35b47fca..3f10aaf28f97 100644 --- a/app/boards/intel_adsp_ace20_lnl.conf +++ b/app/boards/intel_adsp_ace20_lnl.conf @@ -77,6 +77,9 @@ CONFIG_PROBE_DMA_MAX=2 CONFIG_MEMORY_WIN_2_SIZE=12288 +# must be set for LNL/ACE20 +# (can be removed once platform default changed in Zephyr upstream) +CONFIG_DMA_INTEL_ADSP_HDA_TIMING_L1_EXIT=y # Temporary disabled options CONFIG_TRACE=n