From 43a260f2f27db1cba8d940b056af31e266e5938b Mon Sep 17 00:00:00 2001 From: Seppo Ingalsuo Date: Wed, 28 Feb 2024 18:18:33 +0200 Subject: [PATCH 1/4] Tools: Topology2: Build nocodec topologies for PTL and PTL FPGA This patch builds test topologies sof-ptl-nocodec.tplg, sof-ptl-nocodec-fpga-2ch-pdm0.tplg, and sof-ptl-nocodec-fpga-4ch.tplg. The changes include: - New ptl.conf where DMIC and SSP versions are updated vs. LNL and MTL. - The definitions for blob 3.0 format are added to instruct alsa-utils to process a new format SSP blob. Signed-off-by: Seppo Ingalsuo --- tools/topology/topology2/cavs-nocodec.conf | 1 + .../topology2/development/tplg-targets.cmake | 13 +++++++++++++ .../include/common/common_definitions.conf | 1 + tools/topology/topology2/include/dais/ssp.conf | 1 + 4 files changed, 16 insertions(+) diff --git a/tools/topology/topology2/cavs-nocodec.conf b/tools/topology/topology2/cavs-nocodec.conf index 09a13b4926ad..d1d505649835 100644 --- a/tools/topology/topology2/cavs-nocodec.conf +++ b/tools/topology/topology2/cavs-nocodec.conf @@ -101,6 +101,7 @@ IncludeByKey.PLATFORM { "adl" "platform/intel/tgl.conf" "mtl" "platform/intel/mtl.conf" "lnl" "platform/intel/lnl.conf" + "ptl" "platform/intel/ptl.conf" } # include DMIC config if needed. diff --git a/tools/topology/topology2/development/tplg-targets.cmake b/tools/topology/topology2/development/tplg-targets.cmake index bec343c58c04..b83a98816438 100644 --- a/tools/topology/topology2/development/tplg-targets.cmake +++ b/tools/topology/topology2/development/tplg-targets.cmake @@ -55,6 +55,19 @@ NHLT_BIN=nhlt-sof-lnl-nocodec-fpga-4ch.bin,PASSTHROUGH=true,DMIC_IO_CLK=19200000 "cavs-sdw\;sof-lnl-fpga-rt711-l0\;PLATFORM=lnl,NUM_HDMIS=0,PASSTHROUGH=true" +# SSP topology for PTL +"cavs-nocodec\;sof-ptl-nocodec\;PLATFORM=ptl,NUM_DMICS=4,PDM1_MIC_A_ENABLE=1,PDM1_MIC_B_ENABLE=1,\ +PREPROCESS_PLUGINS=nhlt,NHLT_BIN=nhlt-sof-ptl-nocodec.bin" + +# SSP topology for PTL FPGA with lower DMIC IO clock of 19.2MHz, 2ch PDM0 enabled +"cavs-nocodec\;sof-ptl-nocodec-fpga-2ch-pdm0\;PLATFORM=ptl,NUM_DMICS=2,PREPROCESS_PLUGINS=nhlt,\ +NHLT_BIN=nhlt-sof-ptl-nocodec-fpga-2ch-pdm0.bin,PASSTHROUGH=true,DMIC_IO_CLK=19200000" + +# SSP topology for PTL FPGA with lower DMIC IO clock of 19.2MHz, 4ch both PDM0 and PDM1 enabled +"cavs-nocodec\;sof-ptl-nocodec-fpga-4ch\;PLATFORM=ptl,NUM_DMICS=4,PDM1_MIC_A_ENABLE=1,\ +PDM1_MIC_B_ENABLE=1,PREPROCESS_PLUGINS=nhlt,\ +NHLT_BIN=nhlt-sof-ptl-nocodec-fpga-4ch.bin,PASSTHROUGH=true,DMIC_IO_CLK=19200000" + # CAVS HDA topology with mixer-based efx eq pipelines for HDA and passthrough pipelines for HDMI "sof-hda-generic\;sof-hda-efx-generic\;HDA_CONFIG=efx,HDA_MIC_ENHANCED_CAPTURE=true,\ EFX_FIR_PARAMS=passthrough,EFX_IIR_PARAMS=passthrough,EFX_DRC_PARAMS=passthrough,\ diff --git a/tools/topology/topology2/include/common/common_definitions.conf b/tools/topology/topology2/include/common/common_definitions.conf index fe4a2d6e142e..9da9fcb78f34 100644 --- a/tools/topology/topology2/include/common/common_definitions.conf +++ b/tools/topology/topology2/include/common/common_definitions.conf @@ -64,4 +64,5 @@ Define { SSP_BLOB_VERSION_1_0 0x100 SSP_BLOB_VERSION_1_5 0x105 + SSP_BLOB_VERSION_3_0 0x300 } diff --git a/tools/topology/topology2/include/dais/ssp.conf b/tools/topology/topology2/include/dais/ssp.conf index 6c0d91f2bd69..cccba74dea10 100644 --- a/tools/topology/topology2/include/dais/ssp.conf +++ b/tools/topology/topology2/include/dais/ssp.conf @@ -113,6 +113,7 @@ Class.Dai."SSP" { !valid_values [ $SSP_BLOB_VERSION_1_0 $SSP_BLOB_VERSION_1_5 + $SSP_BLOB_VERSION_3_0 ] } } From cde30f655f46d21f4fbb02974695d81aa315de7a Mon Sep 17 00:00:00 2001 From: Seppo Ingalsuo Date: Tue, 16 Jul 2024 18:39:41 +0300 Subject: [PATCH 2/4] Tools: Topology2: Add topology sof-ptl-max98357a-rt5682-ssp2-ssp0 The topology is built into development to be used for testing and further development. Signed-off-by: Seppo Ingalsuo --- tools/topology/topology2/cavs-rt5682.conf | 1 + tools/topology/topology2/development/tplg-targets.cmake | 7 +++++++ 2 files changed, 8 insertions(+) diff --git a/tools/topology/topology2/cavs-rt5682.conf b/tools/topology/topology2/cavs-rt5682.conf index f601ef878d47..91462a8c762f 100644 --- a/tools/topology/topology2/cavs-rt5682.conf +++ b/tools/topology/topology2/cavs-rt5682.conf @@ -129,6 +129,7 @@ Define { IncludeByKey.PLATFORM { "mtl" "platform/intel/mtl.conf" "lnl" "platform/intel/lnl.conf" + "ptl" "platform/intel/ptl.conf" } # include DMIC config if needed. diff --git a/tools/topology/topology2/development/tplg-targets.cmake b/tools/topology/topology2/development/tplg-targets.cmake index b83a98816438..783c3e515df1 100644 --- a/tools/topology/topology2/development/tplg-targets.cmake +++ b/tools/topology/topology2/development/tplg-targets.cmake @@ -68,6 +68,13 @@ NHLT_BIN=nhlt-sof-ptl-nocodec-fpga-2ch-pdm0.bin,PASSTHROUGH=true,DMIC_IO_CLK=192 PDM1_MIC_B_ENABLE=1,PREPROCESS_PLUGINS=nhlt,\ NHLT_BIN=nhlt-sof-ptl-nocodec-fpga-4ch.bin,PASSTHROUGH=true,DMIC_IO_CLK=19200000" +# Topology for PTL with max98357a and rt5682 +"cavs-rt5682\;sof-ptl-max98357a-rt5682-ssp2-ssp0\;PLATFORM=ptl,NUM_DMICS=4,PDM1_MIC_A_ENABLE=1,\ +PDM1_MIC_B_ENABLE=1,DMIC0_PCM_ID=99,PREPROCESS_PLUGINS=nhlt,\ +NHLT_BIN=nhlt-sof-ptl-max98357a-rt5682-ssp2-ssp0.bin,DEEPBUFFER_FW_DMA_MS=10,HEADSET_SSP_DAI_INDEX=2,\ +SPK_ID=6,SPEAKER_SSP_DAI_INDEX=0,HEADSET_CODEC_NAME=SSP2-Codec,SPEAKER_CODEC_NAME=SSP0-Codec,\ +BT_NAME=SSP1-BT,BT_INDEX=1,BT_ID=7,BT_PCM_NAME=Bluetooth,INCLUDE_ECHO_REF=true,DEEP_BUF_SPK=true" + # CAVS HDA topology with mixer-based efx eq pipelines for HDA and passthrough pipelines for HDMI "sof-hda-generic\;sof-hda-efx-generic\;HDA_CONFIG=efx,HDA_MIC_ENHANCED_CAPTURE=true,\ EFX_FIR_PARAMS=passthrough,EFX_IIR_PARAMS=passthrough,EFX_DRC_PARAMS=passthrough,\ From d5f6ea42373d0d3e40cf28a1f364c80d14d9d8b3 Mon Sep 17 00:00:00 2001 From: Seppo Ingalsuo Date: Thu, 25 Jul 2024 14:47:54 +0300 Subject: [PATCH 3/4] Tools: Topology2: Add build of 96 kHz DMIC nocodec topologies for PTL This patch adds build of topologies where DMIC0 related pipelines and PCMs are set to operate with 96 kHz rate. - sof-ptl-nocodec-dmic-4ch-96k.tplg - sof-ptl-nocodec-fpga-dmic-4ch-96k.tplg Signed-off-by: Seppo Ingalsuo --- tools/topology/topology2/cavs-nocodec.conf | 46 +++++++++++++++++++ .../topology2/development/tplg-targets.cmake | 9 ++++ .../platform/intel/dmic-generic.conf | 13 +++++- 3 files changed, 66 insertions(+), 2 deletions(-) diff --git a/tools/topology/topology2/cavs-nocodec.conf b/tools/topology/topology2/cavs-nocodec.conf index d1d505649835..4270457f1805 100644 --- a/tools/topology/topology2/cavs-nocodec.conf +++ b/tools/topology/topology2/cavs-nocodec.conf @@ -329,10 +329,12 @@ IncludeByKey.PASSTHROUGH { num_input_audio_formats 2 Object.Base.input_audio_format [ { + in_rate $DMIC0_RATE in_bit_depth 32 in_valid_bit_depth 32 } { + in_rate $DMIC0_RATE in_channels 4 in_bit_depth 32 in_valid_bit_depth 32 @@ -344,10 +346,12 @@ IncludeByKey.PASSTHROUGH { num_output_audio_formats 2 Object.Base.output_audio_format [ { + out_rate $DMIC0_RATE out_bit_depth 32 out_valid_bit_depth 32 } { + out_rate $DMIC0_RATE out_channels 4 out_bit_depth 32 out_valid_bit_depth 32 @@ -361,10 +365,12 @@ IncludeByKey.PASSTHROUGH { num_input_audio_formats 2 Object.Base.input_audio_format [ { + in_rate $DMIC0_RATE in_bit_depth 32 in_valid_bit_depth 32 } { + in_rate $DMIC0_RATE in_channels 4 in_bit_depth 32 in_valid_bit_depth 32 @@ -376,10 +382,12 @@ IncludeByKey.PASSTHROUGH { num_output_audio_formats 2 Object.Base.output_audio_format [ { + out_rate $DMIC0_RATE out_bit_depth 32 out_valid_bit_depth 32 } { + out_rate $DMIC0_RATE out_channels 4 out_bit_depth 32 out_valid_bit_depth 32 @@ -765,10 +773,12 @@ IncludeByKey.PASSTHROUGH { num_input_audio_formats 2 Object.Base.input_audio_format [ { + in_rate $DMIC0_RATE in_bit_depth 32 in_valid_bit_depth 32 } { + in_rate $DMIC0_RATE in_channels 4 in_bit_depth 32 in_valid_bit_depth 32 @@ -780,10 +790,12 @@ IncludeByKey.PASSTHROUGH { num_output_audio_formats 2 Object.Base.output_audio_format [ { + out_rate $DMIC0_RATE out_bit_depth 32 out_valid_bit_depth 32 } { + out_rate $DMIC0_RATE out_channels 4 out_bit_depth 32 out_valid_bit_depth 32 @@ -797,10 +809,12 @@ IncludeByKey.PASSTHROUGH { num_input_audio_formats 2 Object.Base.input_audio_format [ { + in_rate $DMIC0_RATE in_bit_depth 32 in_valid_bit_depth 32 } { + in_rate $DMIC0_RATE in_channels 4 in_bit_depth 32 in_valid_bit_depth 32 @@ -812,10 +826,12 @@ IncludeByKey.PASSTHROUGH { num_output_audio_formats 2 Object.Base.output_audio_format [ { + out_rate $DMIC0_RATE out_bit_depth 32 out_valid_bit_depth 32 } { + out_rate $DMIC0_RATE out_channels 4 out_bit_depth 32 out_valid_bit_depth 32 @@ -841,10 +857,12 @@ IncludeByKey.PASSTHROUGH { num_input_audio_formats 2 Object.Base.input_audio_format [ { + in_rate $DMIC0_RATE in_bit_depth 32 in_valid_bit_depth 32 } { + in_rate $DMIC0_RATE in_channels 4 in_bit_depth 32 in_valid_bit_depth 32 @@ -856,10 +874,12 @@ IncludeByKey.PASSTHROUGH { num_output_audio_formats 2 Object.Base.output_audio_format [ { + out_rate $DMIC0_RATE out_bit_depth 32 out_valid_bit_depth 32 } { + out_rate $DMIC0_RATE out_channels 4 out_bit_depth 32 out_valid_bit_depth 32 @@ -873,10 +893,12 @@ IncludeByKey.PASSTHROUGH { num_input_audio_formats 2 Object.Base.input_audio_format [ { + in_rate $DMIC0_RATE in_bit_depth 32 in_valid_bit_depth 32 } { + in_rate $DMIC0_RATE in_channels 4 in_bit_depth 32 in_valid_bit_depth 32 @@ -888,10 +910,12 @@ IncludeByKey.PASSTHROUGH { num_output_audio_formats 2 Object.Base.output_audio_format [ { + out_rate $DMIC0_RATE out_bit_depth 32 out_valid_bit_depth 32 } { + out_rate $DMIC0_RATE out_channels 4 out_bit_depth 32 out_valid_bit_depth 32 @@ -961,6 +985,17 @@ IncludeByKey.PASSTHROUGH { formats 'S32_LE' channels_min $NUM_DMICS channels_max $NUM_DMICS + IncludeByKey.DMIC0_RATE { + "16000" { + rates '16000' + } + "48000" { + rates '48000' + } + "96000" { + rates '96000' + } + } } } { @@ -975,6 +1010,17 @@ IncludeByKey.PASSTHROUGH { formats 'S32_LE' channels_min $NUM_DMICS channels_max $NUM_DMICS + IncludeByKey.DMIC0_RATE { + "16000" { + rates '16000' + } + "48000" { + rates '48000' + } + "96000" { + rates '96000' + } + } } } { diff --git a/tools/topology/topology2/development/tplg-targets.cmake b/tools/topology/topology2/development/tplg-targets.cmake index 783c3e515df1..4fa092f7bc6b 100644 --- a/tools/topology/topology2/development/tplg-targets.cmake +++ b/tools/topology/topology2/development/tplg-targets.cmake @@ -59,6 +59,10 @@ NHLT_BIN=nhlt-sof-lnl-nocodec-fpga-4ch.bin,PASSTHROUGH=true,DMIC_IO_CLK=19200000 "cavs-nocodec\;sof-ptl-nocodec\;PLATFORM=ptl,NUM_DMICS=4,PDM1_MIC_A_ENABLE=1,PDM1_MIC_B_ENABLE=1,\ PREPROCESS_PLUGINS=nhlt,NHLT_BIN=nhlt-sof-ptl-nocodec.bin" +# SSP topology for PTL with 96 kHz DMIC +"cavs-nocodec\;sof-ptl-nocodec-dmic-4ch-96k\;PLATFORM=ptl,NUM_DMICS=4,PDM1_MIC_A_ENABLE=1,PDM1_MIC_B_ENABLE=1,\ +DMIC0_RATE=96000,PREPROCESS_PLUGINS=nhlt,NHLT_BIN=nhlt-sof-ptl-nocodec-dmic-4ch-96k.bin" + # SSP topology for PTL FPGA with lower DMIC IO clock of 19.2MHz, 2ch PDM0 enabled "cavs-nocodec\;sof-ptl-nocodec-fpga-2ch-pdm0\;PLATFORM=ptl,NUM_DMICS=2,PREPROCESS_PLUGINS=nhlt,\ NHLT_BIN=nhlt-sof-ptl-nocodec-fpga-2ch-pdm0.bin,PASSTHROUGH=true,DMIC_IO_CLK=19200000" @@ -68,6 +72,11 @@ NHLT_BIN=nhlt-sof-ptl-nocodec-fpga-2ch-pdm0.bin,PASSTHROUGH=true,DMIC_IO_CLK=192 PDM1_MIC_B_ENABLE=1,PREPROCESS_PLUGINS=nhlt,\ NHLT_BIN=nhlt-sof-ptl-nocodec-fpga-4ch.bin,PASSTHROUGH=true,DMIC_IO_CLK=19200000" +# SSP topology for PTL FPGA with lower DMIC IO clock of 19.2MHz, 4ch both PDM0 and PDM1 enabled, with 96 kHz DMIC +"cavs-nocodec\;sof-ptl-nocodec-fpga-dmic-4ch-96k\;PLATFORM=ptl,NUM_DMICS=4,PDM1_MIC_A_ENABLE=1,\ +PDM1_MIC_B_ENABLE=1,DMIC0_RATE=96000,PREPROCESS_PLUGINS=nhlt,\ +NHLT_BIN=nhlt-sof-ptl-nocodec-fpga-dmic-4ch-96k.bin,PASSTHROUGH=true,DMIC_IO_CLK=19200000" + # Topology for PTL with max98357a and rt5682 "cavs-rt5682\;sof-ptl-max98357a-rt5682-ssp2-ssp0\;PLATFORM=ptl,NUM_DMICS=4,PDM1_MIC_A_ENABLE=1,\ PDM1_MIC_B_ENABLE=1,DMIC0_PCM_ID=99,PREPROCESS_PLUGINS=nhlt,\ diff --git a/tools/topology/topology2/platform/intel/dmic-generic.conf b/tools/topology/topology2/platform/intel/dmic-generic.conf index 22b811c18c83..4929fbab0687 100644 --- a/tools/topology/topology2/platform/intel/dmic-generic.conf +++ b/tools/topology/topology2/platform/intel/dmic-generic.conf @@ -721,8 +721,17 @@ Object.PCM.pcm [ formats 'S32_LE' channels_min $DMIC0_PCM_CHANNELS channels_max $DMIC0_PCM_CHANNELS - rate_min $DMIC0_RATE - rate_max $DMIC0_RATE + IncludeByKey.DMIC0_RATE { + "16000" { + rates '16000' + } + "48000" { + rates '48000' + } + "96000" { + rates '96000' + } + } } } ] From c0960b56b316124d3eebe0af8ad8f9894e950243 Mon Sep 17 00:00:00 2001 From: Seppo Ingalsuo Date: Fri, 26 Jul 2024 15:36:43 +0300 Subject: [PATCH 4/4] Tools: Topology2: Build nocodec topology for PTL with 96 kHz SSP This patch adds possibility to build with cavs-nocodec.conf topology in passthrough mode with other rate than 48 kHz. The topologies built are: - sof-ptl-nocodec-dmic-4ch-96k-ssp0-96k.tplg - sof-ptl-nocodec-fpga-dmic-4ch-96k-ssp0-96k.tplg Signed-off-by: Seppo Ingalsuo --- tools/topology/topology2/cavs-nocodec.conf | 205 +++++++++++++++++- .../topology2/development/tplg-targets.cmake | 10 + .../topology2/platform/intel/ssp-default.conf | 12 + 3 files changed, 221 insertions(+), 6 deletions(-) create mode 100644 tools/topology/topology2/platform/intel/ssp-default.conf diff --git a/tools/topology/topology2/cavs-nocodec.conf b/tools/topology/topology2/cavs-nocodec.conf index 4270457f1805..b749291e3336 100644 --- a/tools/topology/topology2/cavs-nocodec.conf +++ b/tools/topology/topology2/cavs-nocodec.conf @@ -50,6 +50,7 @@ + Define { MCLK 24576000 @@ -135,8 +136,18 @@ Object.Dai.SSP [ Object.Base.hw_config.1 { name "SSP0" id 0 - bclk_freq 3072000 - tdm_slot_width 32 + IncludeByKey.SSP0_RATE { + "48000" { + fsync_freq 48000 + bclk_freq 3072000 + tdm_slot_width 32 + } + "96000" { + fsync_freq 96000 + bclk_freq 6144000 + tdm_slot_width 32 + } + } # TODO: remove this. Needs alsaptlg change. Object.Base.link_config.1 { clock_source 1 @@ -156,8 +167,18 @@ Object.Dai.SSP [ Object.Base.hw_config.1 { name "SSP2" id 0 - bclk_freq 3072000 - tdm_slot_width 32 + IncludeByKey.SSP2_RATE { + "48000" { + fsync_freq 48000 + bclk_freq 3072000 + tdm_slot_width 32 + } + "96000" { + fsync_freq 96000 + bclk_freq 6144000 + tdm_slot_width 32 + } + } # TODO: remove this. Needs alsaptlg change. Object.Base.link_config.1 { clock_source 1 @@ -484,14 +505,17 @@ IncludeByKey.PASSTHROUGH { num_input_audio_formats 3 Object.Base.input_audio_format [ { + in_rate $SSP0_RATE in_bit_depth 16 in_valid_bit_depth 16 } { + in_rate $SSP0_RATE in_bit_depth 32 in_valid_bit_depth 24 } { + in_rate $SSP0_RATE in_bit_depth 32 in_valid_bit_depth 32 } @@ -499,14 +523,17 @@ IncludeByKey.PASSTHROUGH { num_output_audio_formats 3 Object.Base.output_audio_format [ { + out_rate $SSP0_RATE out_bit_depth 16 out_valid_bit_depth 16 } { + out_rate $SSP0_RATE out_bit_depth 32 out_valid_bit_depth 24 } { + out_rate $SSP0_RATE out_bit_depth 32 out_valid_bit_depth 32 } @@ -527,14 +554,17 @@ IncludeByKey.PASSTHROUGH { num_input_audio_formats 3 Object.Base.input_audio_format [ { + in_rate $SSP2_RATE in_bit_depth 16 in_valid_bit_depth 16 } { + in_rate $SSP2_RATE in_bit_depth 32 in_valid_bit_depth 24 } { + in_rate $SSP2_RATE in_bit_depth 32 in_valid_bit_depth 32 } @@ -542,14 +572,17 @@ IncludeByKey.PASSTHROUGH { num_output_audio_formats 3 Object.Base.output_audio_format [ { + out_rate $SSP2_RATE out_bit_depth 16 out_valid_bit_depth 16 } { + out_rate $SSP2_RATE out_bit_depth 32 out_valid_bit_depth 24 } { + out_rate $SSP2_RATE out_bit_depth 32 out_valid_bit_depth 32 } @@ -567,14 +600,17 @@ IncludeByKey.PASSTHROUGH { num_input_audio_formats 3 Object.Base.input_audio_format [ { + in_rate $SSP0_RATE in_bit_depth 16 in_valid_bit_depth 16 } { + in_rate $SSP0_RATE in_bit_depth 32 in_valid_bit_depth 24 } { + in_rate $SSP0_RATE in_bit_depth 32 in_valid_bit_depth 32 } @@ -582,14 +618,17 @@ IncludeByKey.PASSTHROUGH { num_output_audio_formats 3 Object.Base.output_audio_format [ { + out_rate $SSP0_RATE out_bit_depth 16 out_valid_bit_depth 16 } { + out_rate $SSP0_RATE out_bit_depth 32 out_valid_bit_depth 24 } { + out_rate $SSP0_RATE out_bit_depth 32 out_valid_bit_depth 32 } @@ -605,14 +644,17 @@ IncludeByKey.PASSTHROUGH { num_input_audio_formats 3 Object.Base.input_audio_format [ { + in_rate $SSP2_RATE in_bit_depth 16 in_valid_bit_depth 16 } { + in_rate $SSP2_RATE in_bit_depth 32 in_valid_bit_depth 24 } { + in_rate $SSP2_RATE in_bit_depth 32 in_valid_bit_depth 32 } @@ -620,14 +662,17 @@ IncludeByKey.PASSTHROUGH { num_output_audio_formats 3 Object.Base.output_audio_format [ { + out_rate $SSP2_RATE out_bit_depth 16 out_valid_bit_depth 16 } { + out_rate $SSP2_RATE out_bit_depth 32 out_valid_bit_depth 24 } { + out_rate $SSP2_RATE out_bit_depth 32 out_valid_bit_depth 32 } @@ -643,6 +688,42 @@ IncludeByKey.PASSTHROUGH { Object.Widget.host-copier.1 { stream_name 'SSP0 Capture' pcm_id 0 + num_input_audio_formats 3 + Object.Base.input_audio_format [ + { + in_rate $SSP0_RATE + in_bit_depth 16 + in_valid_bit_depth 16 + } + { + in_rate $SSP0_RATE + in_bit_depth 32 + in_valid_bit_depth 24 + } + { + in_rate $SSP0_RATE + in_bit_depth 32 + in_valid_bit_depth 32 + } + ] + num_output_audio_formats 3 + Object.Base.output_audio_format [ + { + out_rate $SSP0_RATE + out_bit_depth 16 + out_valid_bit_depth 16 + } + { + out_rate $SSP0_RATE + out_bit_depth 32 + out_valid_bit_depth 24 + } + { + out_rate $SSP0_RATE + out_bit_depth 32 + out_valid_bit_depth 32 + } + ] } } { @@ -652,6 +733,42 @@ IncludeByKey.PASSTHROUGH { Object.Widget.host-copier.1 { stream_name 'SSP2 Capture' pcm_id 2 + num_input_audio_formats 3 + Object.Base.input_audio_format [ + { + in_rate $SSP2_RATE + in_bit_depth 16 + in_valid_bit_depth 16 + } + { + in_rate $SSP2_RATE + in_bit_depth 32 + in_valid_bit_depth 24 + } + { + in_rate $SSP2_RATE + in_bit_depth 32 + in_valid_bit_depth 32 + } + ] + num_output_audio_formats 3 + Object.Base.output_audio_format [ + { + out_rate $SSP2_RATE + out_bit_depth 16 + out_valid_bit_depth 16 + } + { + out_rate $SSP2_RATE + out_bit_depth 32 + out_valid_bit_depth 24 + } + { + out_rate $SSP2_RATE + out_bit_depth 32 + out_valid_bit_depth 32 + } + ] } Object.Widget.pipeline."1" { @@ -677,6 +794,7 @@ IncludeByKey.PASSTHROUGH { Object.Base.input_audio_format [ { + in_rate $SSP0_RATE in_bit_depth 32 in_valid_bit_depth 32 } @@ -684,6 +802,7 @@ IncludeByKey.PASSTHROUGH { num_output_audio_formats 1 Object.Base.output_audio_format [ { + out_rate $SSP0_RATE out_bit_depth 32 out_valid_bit_depth 32 } @@ -711,6 +830,7 @@ Object.Pipeline.io-gateway-capture [ num_input_audio_formats 1 Object.Base.input_audio_format [ { + in_rate $SSP2_RATE in_bit_depth 32 in_valid_bit_depth 32 } @@ -718,6 +838,7 @@ Object.Pipeline.io-gateway-capture [ num_output_audio_formats 1 Object.Base.output_audio_format [ { + out_rate $SSP2_RATE out_bit_depth 32 out_valid_bit_depth 32 } @@ -948,12 +1069,28 @@ Object.PCM.pcm [ direction "playback" name "SSP0 Playback" formats 'S16_LE,S24_LE,S32_LE' + IncludeByKey.SSP0_RATE { + "48000" { + rates '48000' + } + "96000" { + rates '96000' + } + } } Object.PCM.pcm_caps.2 { direction "capture" name "SSP0 Capture" formats 'S16_LE,S24_LE,S32_LE' + IncludeByKey.SSP0_RATE { + "48000" { + rates '48000' + } + "96000" { + rates '96000' + } + } } } ] @@ -1064,12 +1201,28 @@ IncludeByKey.PASSTHROUGH { direction "playback" name "SSP2 Playback" formats 'S16_LE,S24_LE,S32_LE' + IncludeByKey.SSP2_RATE { + "48000" { + rates '48000' + } + "96000" { + rates '96000' + } + } } Object.PCM.pcm_caps.2 { direction "capture" name "SSP2 Capture" formats 'S16_LE,S24_LE,S32_LE' + IncludeByKey.SSP2_RATE { + "48000" { + rates '48000' + } + "96000" { + rates '96000' + } + } } } ] @@ -1216,8 +1369,18 @@ IncludeByKey.SSP1_ENABLED { Object.Base.hw_config.1 { name "SSP1" id 0 - bclk_freq 3072000 - tdm_slot_width 32 + IncludeByKey.SSP1_RATE { + "48000" { + fsync_freq 48000 + tdm_slot_width 32 + bclk_freq 3072000 + } + "96000" { + fsync_freq 96000 + tdm_slot_width 32 + bclk_freq 6144000 + } + } # TODO: remove this. Needs alsaptlg change. Object.Base.link_config.1 { clock_source 1 @@ -1243,6 +1406,7 @@ IncludeByKey.SSP1_ENABLED { num_input_audio_formats 1 Object.Base.input_audio_format [ { + in_rate $SSP1_RATE in_bit_depth 32 in_valid_bit_depth 32 } @@ -1250,6 +1414,7 @@ IncludeByKey.SSP1_ENABLED { num_output_audio_formats 1 Object.Base.output_audio_format [ { + out_rate $SSP1_RATE out_bit_depth 32 out_valid_bit_depth 32 } @@ -1341,14 +1506,17 @@ IncludeByKey.SSP1_ENABLED { num_input_audio_formats 3 Object.Base.input_audio_format [ { + in_rate $SSP1_RATE in_bit_depth 16 in_valid_bit_depth 16 } { + in_rate $SSP1_RATE in_bit_depth 32 in_valid_bit_depth 24 } { + in_rate $SSP1_RATE in_bit_depth 32 in_valid_bit_depth 32 } @@ -1356,14 +1524,17 @@ IncludeByKey.SSP1_ENABLED { num_output_audio_formats 3 Object.Base.output_audio_format [ { + out_rate $SSP1_RATE out_bit_depth 16 out_valid_bit_depth 16 } { + out_rate $SSP1_RATE out_bit_depth 32 out_valid_bit_depth 24 } { + out_rate $SSP1_RATE out_bit_depth 32 out_valid_bit_depth 32 } @@ -1380,14 +1551,17 @@ IncludeByKey.SSP1_ENABLED { num_input_audio_formats 3 Object.Base.input_audio_format [ { + in_rate $SSP1_RATE in_bit_depth 16 in_valid_bit_depth 16 } { + in_rate $SSP1_RATE in_bit_depth 32 in_valid_bit_depth 24 } { + in_rate $SSP1_RATE in_bit_depth 32 in_valid_bit_depth 32 } @@ -1395,14 +1569,17 @@ IncludeByKey.SSP1_ENABLED { num_output_audio_formats 3 Object.Base.output_audio_format [ { + out_rate $SSP1_RATE out_bit_depth 16 out_valid_bit_depth 16 } { + out_rate $SSP1_RATE out_bit_depth 32 out_valid_bit_depth 24 } { + out_rate $SSP1_RATE out_bit_depth 32 out_valid_bit_depth 32 } @@ -1426,12 +1603,28 @@ IncludeByKey.SSP1_ENABLED { direction "playback" name "SSP1 Playback" formats 'S16_LE,S24_LE,S32_LE' + IncludeByKey.SSP1_RATE { + "48000" { + rates '48000' + } + "96000" { + rates '96000' + } + } } Object.PCM.pcm_caps.2 { direction "capture" name "SSP1 Capture" formats 'S16_LE,S24_LE,S32_LE' + IncludeByKey.SSP1_RATE { + "48000" { + rates '48000' + } + "96000" { + rates '96000' + } + } } } ] diff --git a/tools/topology/topology2/development/tplg-targets.cmake b/tools/topology/topology2/development/tplg-targets.cmake index 4fa092f7bc6b..fc7e41719eca 100644 --- a/tools/topology/topology2/development/tplg-targets.cmake +++ b/tools/topology/topology2/development/tplg-targets.cmake @@ -63,6 +63,11 @@ PREPROCESS_PLUGINS=nhlt,NHLT_BIN=nhlt-sof-ptl-nocodec.bin" "cavs-nocodec\;sof-ptl-nocodec-dmic-4ch-96k\;PLATFORM=ptl,NUM_DMICS=4,PDM1_MIC_A_ENABLE=1,PDM1_MIC_B_ENABLE=1,\ DMIC0_RATE=96000,PREPROCESS_PLUGINS=nhlt,NHLT_BIN=nhlt-sof-ptl-nocodec-dmic-4ch-96k.bin" +# SSP topology for PTL with 96 kHz DMIC and 96 kHz SSP0 +"cavs-nocodec\;sof-ptl-nocodec-dmic-4ch-96k-ssp0-96k\;PLATFORM=ptl,NUM_DMICS=4,\ +PDM1_MIC_A_ENABLE=1,PDM1_MIC_B_ENABLE=1,DMIC0_RATE=96000,SSP0_RATE=96000,PASSTHROUGH=true,\ +PREPROCESS_PLUGINS=nhlt,NHLT_BIN=nhlt-sof-ptl-nocodec-dmic-4ch-96k-ssp0-96k.bin" + # SSP topology for PTL FPGA with lower DMIC IO clock of 19.2MHz, 2ch PDM0 enabled "cavs-nocodec\;sof-ptl-nocodec-fpga-2ch-pdm0\;PLATFORM=ptl,NUM_DMICS=2,PREPROCESS_PLUGINS=nhlt,\ NHLT_BIN=nhlt-sof-ptl-nocodec-fpga-2ch-pdm0.bin,PASSTHROUGH=true,DMIC_IO_CLK=19200000" @@ -77,6 +82,11 @@ NHLT_BIN=nhlt-sof-ptl-nocodec-fpga-4ch.bin,PASSTHROUGH=true,DMIC_IO_CLK=19200000 PDM1_MIC_B_ENABLE=1,DMIC0_RATE=96000,PREPROCESS_PLUGINS=nhlt,\ NHLT_BIN=nhlt-sof-ptl-nocodec-fpga-dmic-4ch-96k.bin,PASSTHROUGH=true,DMIC_IO_CLK=19200000" +# SSP topology for PTL FPGA, same as previous but with 96 kHz SSP0 +"cavs-nocodec\;sof-ptl-nocodec-fpga-dmic-4ch-96k-ssp0-96k\;PLATFORM=ptl,NUM_DMICS=4,PDM1_MIC_A_ENABLE=1,\ +PDM1_MIC_B_ENABLE=1,DMIC0_RATE=96000,SSP0_RATE=96000,PREPROCESS_PLUGINS=nhlt,\ +NHLT_BIN=nhlt-sof-ptl-nocodec-fpga-dmic-4ch-96k-ssp0-96k.bin,PASSTHROUGH=true,DMIC_IO_CLK=19200000" + # Topology for PTL with max98357a and rt5682 "cavs-rt5682\;sof-ptl-max98357a-rt5682-ssp2-ssp0\;PLATFORM=ptl,NUM_DMICS=4,PDM1_MIC_A_ENABLE=1,\ PDM1_MIC_B_ENABLE=1,DMIC0_PCM_ID=99,PREPROCESS_PLUGINS=nhlt,\ diff --git a/tools/topology/topology2/platform/intel/ssp-default.conf b/tools/topology/topology2/platform/intel/ssp-default.conf new file mode 100644 index 000000000000..cab144bd5da9 --- /dev/null +++ b/tools/topology/topology2/platform/intel/ssp-default.conf @@ -0,0 +1,12 @@ +# Default SSP variable definitions +Define { + SSP0_RATE 48000 + SSP0_BCLK_FREQ 3072000 + SSP0_TDM_SLOT_WIDTH 32 + SSP1_RATE 48000 + SSP1_BCLK_FREQ 3072000 + SSP1_TDM_SLOT_WIDTH 32 + SSP2_RATE 48000 + SSP2_BCLK_FREQ 3072000 + SSP2_TDM_SLOT_WIDTH 32 +}