Comprehensive verification suite for the AHB2APB Bridge design, featuring SystemVerilog and UVM-based methodologies. 🌉🚀

100DaysofRTL & System Verilog design: basic logic gates, mux, half/full subtractor, Encoder, D flipflop, 8 bit counter, LFSR, Custom Counter, Mux using case, JK flip flop, T flip flop, positive edge detection, Priority encoder, Barrel shifter, Signed Magnitude adder, Free Running Counter, Mod-m Counter, Edge Detector mealy Moore

System Verilog BootCamp

Implements a simple UVM based testbench for a simple memory DUT.

Ease the Life of Verification Engineers by helping them to analyze and understand failing simulation faster

Superscalar dual-issue RISC-V processor

uvm framework generator

Getting started with SystemVerilog: Hardware Description Language for design and verification.

Python script to create sequence item from spreadsheet

SystemVerilog Testbench Workshop Lab

Examples with UVM

A collection of decoders and their test benches simulated using Verilog.

It's a simple verilog based MIPS microarchitecture hardware design.

UVM-based functional verification of an APB-based UART Master Core RTL. Includes multi-agent environment, assertions, coverage collection, and multiple test scenarios (full/half duplex, parity, framing, timeout errors) achieving 100% functional coverage and protocol compliance.

Fully synthesizable and paramterizable, IEEE-754 compliant Floating Point Unit (FPU) in systemverilog. Supports fused multiply add, division and square root operations.

Functional verification using SystemVerilog's HVL feature

A Verilog-based bus routing module that connects one master to multiple slaves using address-based decoding logic. Includes a modular SystemVerilog testbench (driver, monitor, scoreboard, etc.) to verify correct routing and functionality across defined address ranges.

This repository documents a project undertaken as part of the EN2111 Electronic Circuit Design module at the University of Moratuwa, focusing on the implementation of a UART communication link between two FPGA boards.

UVM-based SystemVerilog testbench for CDC & Async FIFO: SVA assertions, functional coverage, agents/sequences/scoreboard, and VCS/Questa run scripts.

Repository of homeworks and projects of the verification class from Bootcamp Pre-Silicon at ITESO with INTEL