diff --git a/spec/cpu.typ b/spec/cpu.typ
index 0afa75f62..9036593ac 100644
--- a/spec/cpu.typ
+++ b/spec/cpu.typ
@@ -76,9 +76,8 @@ including the appropriate sign/zero extension, depending on `word_instr`.
 #render_constraint_table(chip, config, groups: "ext")
 
 === Other constraints
-
-#rj[proper ref to IsZero/IsEqual]
-For @cpu:c:is_equal, refer to the logic of IsZero or IsEqual, in combination with the subtraction of @cpu:c:sub.
+For @cpu:c:is_equal, note that @cpu:c:sub sets `res` to be the difference between `arg1` and `arg2` whenever `BEQ` is $1$.
+Given that this difference is $0$ when both are equal, @cpu:c:is_equal ensures `is_equal` is set to $1$ if and only if $#`arg1` = #`arg2`$ and `BEQ` is set.
 
 #render_constraint_table(chip, config, groups: "misc")
 
diff --git a/spec/src/shift.toml b/spec/src/shift.toml
index 4b7044e7d..591efb839 100644
--- a/spec/src/shift.toml
+++ b/spec/src/shift.toml
@@ -198,8 +198,8 @@ ref = "shift:c:bit_shift_if_right"
 multiplicity = "right"
 
 [[constraints.bit_shift]]
-kind = "template"
-tag = "IsZero"
+kind = "interaction"
+tag = "ZERO"
 input = ["bit_shift"]
 output = "zbs"
 ref = "shift:c:zbs"