From 9c707e2875f88be170f8afb5b8e685bcec4aefe4 Mon Sep 17 00:00:00 2001
From: Joaquin Carletti <joaquin.carletti@lambdaclass.com>
Date: Fri, 6 Feb 2026 09:03:05 -0300
Subject: [PATCH] add is_signed to bus

---
 prover/src/tables/cpu.rs  | 9 +++++++--
 prover/src/tables/load.rs | 7 ++++++-
 2 files changed, 13 insertions(+), 3 deletions(-)

diff --git a/prover/src/tables/cpu.rs b/prover/src/tables/cpu.rs
index f04db3f45..2b9060e48 100644
--- a/prover/src/tables/cpu.rs
+++ b/prover/src/tables/cpu.rs
@@ -1408,9 +1408,9 @@ pub fn bus_interactions() -> Vec<BusInteraction> {
     ));
 
     // -------------------------------------------------------------------------
-    // M6: LOAD[rvd; base_address, timestamp, read2, read4, read8] | LOAD
+    // M6: LOAD[rvd; base_address, timestamp, read2, read4, read8, signed] | LOAD
     // -------------------------------------------------------------------------
-    // LOAD receiver expects: [res::DWordBL(2), base_address::DWordWL(2), timestamp::DWordWL(2), flags(3)] = 9 elements
+    // LOAD receiver expects: [res::DWordBL(2), base_address::DWordWL(2), timestamp::DWordWL(2), flags(3), signed(1)] = 10 elements
     //
     // For CPU LOAD:
     // - rvd (the loaded result) corresponds to res
@@ -1450,6 +1450,11 @@ pub fn bus_interactions() -> Vec<BusInteraction> {
                 start_column: cols::MEMORY_8BYTES,
                 packing: Packing::Direct,
             },
+            // signed flag
+            BusValue::Packed {
+                start_column: cols::SIGNED,
+                packing: Packing::Direct,
+            },
         ],
     ));
 
diff --git a/prover/src/tables/load.rs b/prover/src/tables/load.rs
index 5e81958be..09da15aab 100644
--- a/prover/src/tables/load.rs
+++ b/prover/src/tables/load.rs
@@ -425,7 +425,7 @@ pub fn bus_interactions() -> Vec<BusInteraction> {
     // -------------------------------------------------------------------------
     // LOAD receiver (from CPU)
     // -------------------------------------------------------------------------
-    // Spec: LOAD[res::DWordWL; base_address, timestamp, read2, read4, read8] | -μ
+    // Spec: LOAD[res::DWordWL; base_address, timestamp, read2, read4, read8, signed] | -μ
     //
     // res is DWordBL (8 bytes) but packed as DWordWL (2 words) for the bus.
     // DWordBL packing: 8 bytes → 2 bus elements [lo32, hi32]
@@ -461,6 +461,11 @@ pub fn bus_interactions() -> Vec<BusInteraction> {
                 start_column: cols::READ8,
                 packing: Packing::Direct,
             },
+            // signed flag
+            BusValue::Packed {
+                start_column: cols::SIGNED,
+                packing: Packing::Direct,
+            },
         ],
     ));