Add MEMW_R register fast-path table#477
Conversation
Codex Code ReviewFindings
No other concrete security/correctness/performance issues stood out in the PR diff. |
|
/bench |
Benchmark — fib_iterative_8M (median of 3)Table parallelism: 32 (auto = cores / 3)
Commit: b1f365b · Baseline: cached · Runner: self-hosted bench |
Codex Code ReviewFindings
Could not run tests in this environment due sandboxed read-only |
Review: MEMW_R register fast-path tableOverall the design is sound and well-structured. The structural sharing of
|
Code reviewNo issues found. Checked for bugs and CLAUDE.md compliance. 🤖 Generated with Claude Code |
|
/bench |
* save work * Fix MEMW_R routing predicate to allow timestamp delta = 2^16 * promote old_timestamp assert, add IS_HALF vs LT doc, and expand test coverage * fix comment * Add underflow guard and change assert to debug_assert --------- Co-authored-by: Nicole <nicole.graus@lambdaclass.com>
Implements the
MEMW_Rregister fast path from spec PR #457.Adds a new 10-column table for register accesses.
Registers are always aligned 2-word accesses with
is_register=1, so this table strips the general-purpose memory columns (address decomposition, alignment mask, width flags, per-byte old timestamps)IS_HALFlookup instead ofLT, proving a delta in[1, 2^16].is_register_opsends eligible register ops toMEMW_Rat trace-build time.