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spec: CPU chip for RV64IMC #88
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,84 @@ | ||
| #import "/book.typ": book-page, rj | ||
| #import "/src.typ": load_config, load_chip | ||
| #import "/chip.typ": ( | ||
| render_chip_assumptions, | ||
| render_chip_column_table, | ||
| total_nr_variables, | ||
| total_nr_instantiated_columns, | ||
| render_constraint_table, | ||
| ) | ||
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| #let config = load_config() | ||
| #let chip = load_chip("src/cpu.toml", config) | ||
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| #show: book-page.with(title: "CPU chip") | ||
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| == Columns | ||
| #let nr_variables = total_nr_variables(chip) | ||
| #let nr_columns = total_nr_instantiated_columns(chip, config) | ||
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| The `CPU` chip is comprised of #nr_variables variables that are expressed using #nr_columns columns: | ||
| #render_chip_column_table(chip, config) | ||
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| == Assumptions | ||
| #render_chip_assumptions(chip, config) | ||
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| == Constraints | ||
| First, we perform a decoding lookup for the current PC. | ||
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| #render_constraint_table(chip, config, groups: "decode") | ||
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| #rj[All casts for interactions will have to be reviewed once other chip interfaces stabilise] | ||
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| === Range checks | ||
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| We constrain all columns to have the appropriate ranges. | ||
| The flags and register indices looked up from the decoding need to be checked, | ||
| as they are communicated through the interaction in a packed form. | ||
| In contrast, we know ahead of time that decoding will ensure proper range checks for `pc` and `imm`. | ||
| Similarly, since `next_pc` will propagate through the memory argument and be looked up | ||
| in the instruction decoding on the next cycle, it is forced to be in the correct range.#rj[is this true, do we need this elsewhere for chip assumptions?] | ||
| For the auxiliary columns, we need to check the limbs of `arg1`, `arg2`, and `res`. | ||
| The ranges of the other auxiliary columns are enforced through later constraints. | ||
| #rj[Make sure we argue for every column here] | ||
| #rj[is `rvd` still sufficiently constrained? (can also be done through the memory argument like `pc`?)] | ||
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| #render_constraint_table(chip, config, groups: "range") | ||
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| === ALU | ||
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| The ALU functionality is then obtained through judicious dispatching to the corresponding chips. | ||
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| #render_constraint_table(chip, config, groups: "alu") | ||
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| === Memory | ||
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| The interactions with the memory, both for register loading and storing, as for `LOAD` and `STORE` instructions are handled. | ||
| Note that since registers need no byte-addressing, we store them in the memory argument with `Word` limbs. | ||
| The timestamps are ensured to be disjoint for disjoint memory locations. | ||
| One consequence of that is that `next_pc` is written at `timestamp + 1` | ||
| to ensure the access is disjoint with the `pc` read into `rv1` as part of the `AUIPC` instruction. | ||
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| #render_constraint_table(chip, config, groups: "mem") | ||
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| === System | ||
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| The interactions with the wider system. | ||
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| #render_constraint_table(chip, config, groups: "sys") | ||
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| === Input and output to the ALU | ||
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| We constrain `arg1`, `arg2` and `rvd` to correspond to the wanted values, | ||
| including the appropriate sign/zero extension, depending on `word_instr`. | ||
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| #render_constraint_table(chip, config, groups: "ext") | ||
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| === Other constraints | ||
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| #rj[proper ref to IsZero/IsEqual] | ||
| For @cpu:c:is_equal, refer to the logic of IsZero or IsEqual, in combination with the subtraction of @cpu:c:sub. | ||
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| #render_constraint_table(chip, config, groups: "misc") | ||
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| #rj[Document the choice to not have a multiplicity column here for padding] | ||
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