From 1e9278d718f7eec0aaad4dc296757c70e7f0f68b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Alex=20R=C3=B8nne=20Petersen?= Date: Tue, 30 Jul 2024 00:11:12 +0200 Subject: [PATCH 1/6] std.Target: Remove `spir`/`spir64` architecture tags. These were for very old OpenCL have been long abandoned in favor of SPIR-V. * https://github.com/KhronosGroup/SPIR * https://github.com/KhronosGroup/SPIR-Tools --- lib/compiler/aro/aro/target.zig | 7 ------- lib/std/Target.zig | 18 ++---------------- src/Type.zig | 2 -- src/Zcu.zig | 2 -- src/codegen/llvm.zig | 6 ------ src/target.zig | 2 -- 6 files changed, 2 insertions(+), 35 deletions(-) diff --git a/lib/compiler/aro/aro/target.zig b/lib/compiler/aro/aro/target.zig index 8a864eb0adb3..5822801036b8 100644 --- a/lib/compiler/aro/aro/target.zig +++ b/lib/compiler/aro/aro/target.zig @@ -53,7 +53,6 @@ pub fn intPtrType(target: std.Target) Type { .xcore, .hexagon, .m68k, - .spir, .spirv32, .arc, .avr, @@ -473,7 +472,6 @@ pub fn get32BitArchVariant(target: std.Target) ?std.Target { .x86, .xcore, .nvptx, - .spir, .kalimba, .lanai, .wasm32, @@ -487,7 +485,6 @@ pub fn get32BitArchVariant(target: std.Target) ?std.Target { .aarch64_be => copy.cpu.arch = .armeb, .nvptx64 => copy.cpu.arch = .nvptx, .wasm64 => copy.cpu.arch = .wasm32, - .spir64 => copy.cpu.arch = .spir, .spirv64 => copy.cpu.arch = .spirv32, .loongarch64 => copy.cpu.arch = .loongarch32, .mips64 => copy.cpu.arch = .mips, @@ -526,7 +523,6 @@ pub fn get64BitArchVariant(target: std.Target) ?std.Target { .bpfel, .nvptx64, .wasm64, - .spir64, .spirv64, .loongarch64, .mips64, @@ -550,7 +546,6 @@ pub fn get64BitArchVariant(target: std.Target) ?std.Target { .powerpcle => copy.cpu.arch = .powerpc64le, .riscv32 => copy.cpu.arch = .riscv64, .sparc => copy.cpu.arch = .sparc64, - .spir => copy.cpu.arch = .spir64, .spirv32 => copy.cpu.arch = .spirv64, .thumb => copy.cpu.arch = .aarch64, .thumbeb => copy.cpu.arch = .aarch64_be, @@ -607,8 +602,6 @@ pub fn toLLVMTriple(target: std.Target, buf: []u8) []const u8 { .xtensa => "xtensa", .nvptx => "nvptx", .nvptx64 => "nvptx64", - .spir => "spir", - .spir64 => "spir64", .spirv32 => "spirv32", .spirv64 => "spirv64", .kalimba => "kalimba", diff --git a/lib/std/Target.zig b/lib/std/Target.zig index a69038fae4ac..d76eb885c0e8 100644 --- a/lib/std/Target.zig +++ b/lib/std/Target.zig @@ -1027,8 +1027,6 @@ pub const Cpu = struct { xtensa, nvptx, nvptx64, - spir, - spir64, spirv, spirv32, spirv64, @@ -1048,6 +1046,8 @@ pub const Cpu = struct { // - amdil64 // - hsail // - hsail64 + // - spir + // - spir64 // - shave // - renderscript32 // - renderscript64 @@ -1178,7 +1178,6 @@ pub const Cpu = struct { .xcore => .XCORE, .xtensa => .XTENSA, .nvptx => .NONE, - .spir => .NONE, .kalimba => .CSR_KALIMBA, .lanai => .LANAI, .wasm32 => .NONE, @@ -1191,7 +1190,6 @@ pub const Cpu = struct { .riscv64 => .RISCV, .x86_64 => .X86_64, .nvptx64 => .NONE, - .spir64 => .NONE, .wasm64 => .NONE, .amdgcn => .AMDGPU, .bpfel => .BPF, @@ -1231,7 +1229,6 @@ pub const Cpu = struct { .xcore => .Unknown, .xtensa => .Unknown, .nvptx => .Unknown, - .spir => .Unknown, .kalimba => .Unknown, .lanai => .Unknown, .wasm32 => .Unknown, @@ -1244,7 +1241,6 @@ pub const Cpu = struct { .riscv64 => .RISCV64, .x86_64 => .X64, .nvptx64 => .Unknown, - .spir64 => .Unknown, .wasm64 => .Unknown, .amdgcn => .Unknown, .bpfel => .Unknown, @@ -1289,8 +1285,6 @@ pub const Cpu = struct { .wasm64, .xcore, .thumb, - .spir, - .spir64, .ve, .spu_2, // GPU bitness is opaque. For now, assume little endian. @@ -1769,8 +1763,6 @@ pub const DynamicLinker = struct { .msp430, .amdgcn, .xcore, - .spir, - .spir64, .kalimba, .lanai, .ve, @@ -1868,7 +1860,6 @@ pub fn ptrBitWidth_cpu_abi(cpu: Cpu, abi: Abi) u16 { .x86, .xcore, .nvptx, - .spir, .kalimba, .lanai, .wasm32, @@ -1887,7 +1878,6 @@ pub fn ptrBitWidth_cpu_abi(cpu: Cpu, abi: Abi) u16 { .riscv64, .x86_64, .nvptx64, - .spir64, .wasm64, .amdgcn, .bpfel, @@ -2368,7 +2358,6 @@ pub fn c_type_alignment(target: Target, c_type: CType) u16 { .xcore, .dxil, .loongarch32, - .spir, .spirv32, .kalimba, .ve, @@ -2391,7 +2380,6 @@ pub fn c_type_alignment(target: Target, c_type: CType) u16 { .nvptx, .nvptx64, .s390x, - .spir64, .spirv64, => 8, @@ -2476,7 +2464,6 @@ pub fn c_type_preferred_alignment(target: Target, c_type: CType) u16 { .xcore, .dxil, .loongarch32, - .spir, .spirv32, .kalimba, .ve, @@ -2506,7 +2493,6 @@ pub fn c_type_preferred_alignment(target: Target, c_type: CType) u16 { .nvptx, .nvptx64, .s390x, - .spir64, .spirv64, => 8, diff --git a/src/Type.zig b/src/Type.zig index 5bcffed6b73a..22e293101942 100644 --- a/src/Type.zig +++ b/src/Type.zig @@ -1647,11 +1647,9 @@ pub fn maxIntAlignment(target: std.Target, use_llvm: bool) u16 { .csky, .arc, .m68k, - .spir, .kalimba, .spirv, .spirv32, - .spir64, .ve, .spirv64, .dxil, diff --git a/src/Zcu.zig b/src/Zcu.zig index c644dcce64b4..bc7d2d2e494d 100644 --- a/src/Zcu.zig +++ b/src/Zcu.zig @@ -3253,7 +3253,6 @@ pub fn atomicPtrAlignment( .thumbeb, .x86, .xcore, - .spir, .kalimba, .lanai, .wasm32, @@ -3275,7 +3274,6 @@ pub fn atomicPtrAlignment( .riscv64, .sparc64, .s390x, - .spir64, .wasm64, .ve, .spirv64, diff --git a/src/codegen/llvm.zig b/src/codegen/llvm.zig index 23f423ab2c80..fcbfa06bd2b2 100644 --- a/src/codegen/llvm.zig +++ b/src/codegen/llvm.zig @@ -79,8 +79,6 @@ pub fn targetTriple(allocator: Allocator, target: std.Target) ![]const u8 { .xtensa => "xtensa", .nvptx => "nvptx", .nvptx64 => "nvptx64", - .spir => "spir", - .spir64 => "spir64", .spirv => "spirv", .spirv32 => "spirv32", .spirv64 => "spirv64", @@ -292,8 +290,6 @@ pub fn targetArch(arch_tag: std.Target.Cpu.Arch) llvm.ArchType { .xtensa => .xtensa, .nvptx => .nvptx, .nvptx64 => .nvptx64, - .spir => .spir, - .spir64 => .spir64, .spirv => .spirv, .spirv32 => .spirv32, .spirv64 => .spirv64, @@ -12095,8 +12091,6 @@ pub fn initializeLLVMTarget(arch: std.Target.Cpu.Arch) void { }, // LLVM backends that have no initialization functions. - .spir, - .spir64, .spirv, .spirv32, .spirv64, diff --git a/src/target.zig b/src/target.zig index ccf3ceb62620..e30743f65c30 100644 --- a/src/target.zig +++ b/src/target.zig @@ -148,8 +148,6 @@ pub fn hasLlvmSupport(target: std.Target, ofmt: std.Target.ObjectFormat) bool { .xtensa, .nvptx, .nvptx64, - .spir, - .spir64, .spirv, .spirv32, .spirv64, From c8ca05e93a5ad482279c9dd95e330ed6c1027c3b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Alex=20R=C3=B8nne=20Petersen?= Date: Tue, 30 Jul 2024 02:31:25 +0200 Subject: [PATCH 2/6] std.Target: Remove `sparcel` architecture tag. MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit What is `sparcel`, you might ask? Good question! If you take a peek in the SPARC v8 manual, §2.2, it is quite explicit that SPARC v8 is a big-endian architecture. No little-endian or mixed-endian support to be found here. On the other hand, the SPARC v9 manual, in §3.2.1.2, states that it has support for mixed-endian operation, with big-endian mode being the default. Ok, so `sparcel` must just be referring to SPARC v9 running in little-endian mode, surely? Nope: * https://github.com/llvm/llvm-project/blob/40b4fd7a3e81d32b29364a1b15337bcf817659c0/llvm/lib/Target/Sparc/SparcTargetMachine.cpp#L226 * https://github.com/llvm/llvm-project/blob/40b4fd7a3e81d32b29364a1b15337bcf817659c0/llvm/lib/Target/Sparc/SparcTargetMachine.cpp#L104 So, `sparcel` in LLVM is referring to some sort of fantastical little-endian SPARC v8 architecture. I've scoured the internet and I can find absolutely no evidence that such a thing exists or has ever existed. In fact, I can find no evidence that a little-endian implementation of SPARC v9 ever existed, either. Or any SPARC version, actually! The support was added here: https://reviews.llvm.org/D8741 Notably, there is no mention whatsoever of what CPU this might be referring to, and no justification given for the "but some are little" comment added in the patch. My best guess is that this might have been some private exercise in creating a little-endian version of SPARC that never saw the light of day. Given that SPARC v8 explicitly doesn't support little-endian operation (let alone little-endian instruction encoding!), and no CPU is known to be implemented as such, I think it's very reasonable for us to just remove this support. --- lib/compiler/aro/aro/Compilation.zig | 4 ++-- lib/compiler/aro/aro/Driver/GCCDetector.zig | 2 +- lib/compiler/aro/aro/target.zig | 9 +++---- lib/compiler/aro/aro/toolchains/Linux.zig | 1 - lib/compiler_rt/atomics.zig | 2 +- lib/compiler_rt/clear_cache.zig | 2 +- lib/std/Target.zig | 26 +++++++-------------- lib/std/atomic.zig | 1 - lib/std/builtin.zig | 2 +- lib/std/c.zig | 6 ++--- lib/std/os/linux.zig | 4 +--- lib/std/os/linux/ioctl.zig | 1 - src/Type.zig | 1 - src/Zcu.zig | 1 - src/codegen/llvm.zig | 5 +--- src/glibc.zig | 4 ++-- src/link/Elf.zig | 2 +- src/link/Plan9/aout.zig | 2 +- src/target.zig | 4 +--- test/behavior/align.zig | 1 - test/llvm_targets.zig | 2 -- 21 files changed, 27 insertions(+), 55 deletions(-) diff --git a/lib/compiler/aro/aro/Compilation.zig b/lib/compiler/aro/aro/Compilation.zig index d03f5dc997f2..21d682325349 100644 --- a/lib/compiler/aro/aro/Compilation.zig +++ b/lib/compiler/aro/aro/Compilation.zig @@ -363,7 +363,7 @@ fn generateSystemDefines(comp: *Compilation, w: anytype) !void { \\#define __sparc_v9__ 1 \\ ), - .sparc, .sparcel => try w.writeAll( + .sparc => try w.writeAll( \\#define __sparc__ 1 \\#define __sparc 1 \\ @@ -534,7 +534,7 @@ pub fn generateBuiltinMacros(comp: *Compilation, system_defines_mode: SystemDefi if (system_defines_mode == .include_system_defines) { try buf.appendSlice( - \\#define __VERSION__ "Aro + \\#define __VERSION__ "Aro ++ @import("../backend.zig").version_str ++ "\"\n" ++ \\#define __Aro__ \\ diff --git a/lib/compiler/aro/aro/Driver/GCCDetector.zig b/lib/compiler/aro/aro/Driver/GCCDetector.zig index d13a63985db4..720254316e81 100644 --- a/lib/compiler/aro/aro/Driver/GCCDetector.zig +++ b/lib/compiler/aro/aro/Driver/GCCDetector.zig @@ -376,7 +376,7 @@ fn collectLibDirsAndTriples( biarch_libdirs.appendSliceAssumeCapacity(&RISCV32LibDirs); biarch_triple_aliases.appendSliceAssumeCapacity(&RISCV32Triples); }, - .sparc, .sparcel => { + .sparc => { lib_dirs.appendSliceAssumeCapacity(&SPARCv8LibDirs); triple_aliases.appendSliceAssumeCapacity(&SPARCv8Triples); biarch_libdirs.appendSliceAssumeCapacity(&SPARCv9LibDirs); diff --git a/lib/compiler/aro/aro/target.zig b/lib/compiler/aro/aro/target.zig index 5822801036b8..1035bbaf7a01 100644 --- a/lib/compiler/aro/aro/target.zig +++ b/lib/compiler/aro/aro/target.zig @@ -58,7 +58,7 @@ pub fn intPtrType(target: std.Target) Type { .avr, => return .{ .specifier = .int }, - .sparc, .sparcel => switch (target.os.tag) { + .sparc => switch (target.os.tag) { .netbsd, .openbsd => {}, else => return .{ .specifier = .int }, }, @@ -132,7 +132,7 @@ pub fn defaultFunctionAlignment(target: std.Target) u8 { return switch (target.cpu.arch) { .arm, .armeb => 4, .aarch64, .aarch64_be => 4, - .sparc, .sparcel, .sparc64 => 4, + .sparc, .sparc64 => 4, .riscv64 => 2, else => 1, }; @@ -426,7 +426,7 @@ pub fn ldEmulationOption(target: std.Target, arm_endianness: ?std.builtin.Endian .powerpc64le => "elf64lppc", .riscv32 => "elf32lriscv", .riscv64 => "elf64lriscv", - .sparc, .sparcel => "elf32_sparc", + .sparc => "elf32_sparc", .sparc64 => "elf64_sparc", .loongarch32 => "elf32loongarch", .loongarch64 => "elf64loongarch", @@ -466,7 +466,6 @@ pub fn get32BitArchVariant(target: std.Target) ?std.Target { .powerpcle, .riscv32, .sparc, - .sparcel, .thumb, .thumbeb, .x86, @@ -510,7 +509,6 @@ pub fn get64BitArchVariant(target: std.Target) ?std.Target { .lanai, .m68k, .msp430, - .sparcel, .spu_2, .xcore, .xtensa, @@ -592,7 +590,6 @@ pub fn toLLVMTriple(target: std.Target, buf: []u8) []const u8 { .riscv64 => "riscv64", .sparc => "sparc", .sparc64 => "sparc64", - .sparcel => "sparcel", .s390x => "s390x", .thumb => "thumb", .thumbeb => "thumbeb", diff --git a/lib/compiler/aro/aro/toolchains/Linux.zig b/lib/compiler/aro/aro/toolchains/Linux.zig index f166e9e68354..36ab916b10fb 100644 --- a/lib/compiler/aro/aro/toolchains/Linux.zig +++ b/lib/compiler/aro/aro/toolchains/Linux.zig @@ -357,7 +357,6 @@ fn getOSLibDir(target: std.Target) []const u8 { .powerpc, .powerpcle, .sparc, - .sparcel, => return "lib32", else => {}, } diff --git a/lib/compiler_rt/atomics.zig b/lib/compiler_rt/atomics.zig index 77519ee9a7f2..e82b6ab055fe 100644 --- a/lib/compiler_rt/atomics.zig +++ b/lib/compiler_rt/atomics.zig @@ -30,7 +30,7 @@ const largest_atomic_size = switch (arch) { // On SPARC systems that lacks CAS and/or swap instructions, the only // available atomic operation is a test-and-set (`ldstub`), so we force // every atomic memory access to go through the lock. - .sparc, .sparcel => if (cpu.features.featureSetHas(.hasleoncasa)) @sizeOf(usize) else 0, + .sparc => if (cpu.features.featureSetHas(.hasleoncasa)) @sizeOf(usize) else 0, // XXX: On x86/x86_64 we could check the presence of cmpxchg8b/cmpxchg16b // and set this parameter accordingly. diff --git a/lib/compiler_rt/clear_cache.zig b/lib/compiler_rt/clear_cache.zig index a5740c63febc..5e5f20292849 100644 --- a/lib/compiler_rt/clear_cache.zig +++ b/lib/compiler_rt/clear_cache.zig @@ -41,7 +41,7 @@ fn clear_cache(start: usize, end: usize) callconv(.C) void { else => false, }; const sparc = switch (arch) { - .sparc, .sparc64, .sparcel => true, + .sparc, .sparc64 => true, else => false, }; const apple = switch (os) { diff --git a/lib/std/Target.zig b/lib/std/Target.zig index d76eb885c0e8..729b7ff2ce0c 100644 --- a/lib/std/Target.zig +++ b/lib/std/Target.zig @@ -201,7 +201,7 @@ pub const Os = struct { .mips, .mipsel, .mips64, .mips64el => "mips", .powerpc, .powerpcle, .powerpc64, .powerpc64le => "powerpc", .riscv32, .riscv64 => "riscv", - .sparc, .sparcel, .sparc64 => "sparc", + .sparc, .sparc64 => "sparc", .x86, .x86_64 => "x86", else => @tagName(arch), }, @@ -1017,7 +1017,6 @@ pub const Cpu = struct { riscv64, sparc, sparc64, - sparcel, s390x, thumb, thumbeb, @@ -1040,6 +1039,7 @@ pub const Cpu = struct { // LLVM tags deliberately omitted: // - aarch64_32 // - r600 + // - sparcel // - le32 // - le64 // - amdil @@ -1121,7 +1121,7 @@ pub const Cpu = struct { pub inline fn isSPARC(arch: Arch) bool { return switch (arch) { - .sparc, .sparcel, .sparc64 => true, + .sparc, .sparc64 => true, else => false, }; } @@ -1171,7 +1171,6 @@ pub const Cpu = struct { .powerpc, .powerpcle => .PPC, .riscv32 => .RISCV, .sparc => .SPARC, - .sparcel => .SPARC, .thumb => .ARM, .thumbeb => .ARM, .x86 => .@"386", @@ -1222,7 +1221,6 @@ pub const Cpu = struct { .powerpc, .powerpcle => .POWERPC, .riscv32 => .RISCV32, .sparc => .Unknown, - .sparcel => .Unknown, .thumb => .Thumb, .thumbeb => .Thumb, .x86 => .I386, @@ -1274,7 +1272,6 @@ pub const Cpu = struct { .msp430, .nvptx, .nvptx64, - .sparcel, .powerpcle, .powerpc64le, .riscv32, @@ -1341,7 +1338,7 @@ pub const Cpu = struct { .powerpc, .powerpcle, .powerpc64, .powerpc64le => "powerpc", .amdgcn => "amdgpu", .riscv32, .riscv64 => "riscv", - .sparc, .sparc64, .sparcel => "sparc", + .sparc, .sparc64 => "sparc", .s390x => "s390x", .x86, .x86_64 => "x86", .nvptx, .nvptx64 => "nvptx", @@ -1368,7 +1365,7 @@ pub const Cpu = struct { .powerpc, .powerpcle, .powerpc64, .powerpc64le => &powerpc.all_features, .amdgcn => &amdgpu.all_features, .riscv32, .riscv64 => &riscv.all_features, - .sparc, .sparc64, .sparcel => &sparc.all_features, + .sparc, .sparc64 => &sparc.all_features, .spirv32, .spirv64 => &spirv.all_features, .s390x => &s390x.all_features, .x86, .x86_64 => &x86.all_features, @@ -1398,7 +1395,7 @@ pub const Cpu = struct { .powerpc, .powerpcle, .powerpc64, .powerpc64le => comptime allCpusFromDecls(powerpc.cpu), .amdgcn => comptime allCpusFromDecls(amdgpu.cpu), .riscv32, .riscv64 => comptime allCpusFromDecls(riscv.cpu), - .sparc, .sparc64, .sparcel => comptime allCpusFromDecls(sparc.cpu), + .sparc, .sparc64 => comptime allCpusFromDecls(sparc.cpu), .spirv32, .spirv64 => comptime allCpusFromDecls(spirv.cpu), .s390x => comptime allCpusFromDecls(s390x.cpu), .x86, .x86_64 => comptime allCpusFromDecls(x86.cpu), @@ -1490,7 +1487,7 @@ pub const Cpu = struct { .riscv32 => &riscv.cpu.generic_rv32, .riscv64 => &riscv.cpu.generic_rv64, .spirv32, .spirv64 => &spirv.cpu.generic, - .sparc, .sparcel => &sparc.cpu.generic, + .sparc => &sparc.cpu.generic, .sparc64 => &sparc.cpu.v9, // 64-bit SPARC needs v9 as the baseline .s390x => &s390x.cpu.generic, .x86 => &x86.cpu.i386, @@ -1511,7 +1508,7 @@ pub const Cpu = struct { .x86 => &x86.cpu.pentium4, .nvptx, .nvptx64 => &nvptx.cpu.sm_20, .s390x => &s390x.cpu.arch8, - .sparc, .sparcel => &sparc.cpu.v8, + .sparc => &sparc.cpu.v8, .loongarch64 => &loongarch.cpu.loongarch64, else => generic(arch), @@ -1696,7 +1693,6 @@ pub const DynamicLinker = struct { .linux => switch (cpu.arch) { .x86, .sparc, - .sparcel, => init("/lib/ld-linux.so.2"), .aarch64 => init("/lib/ld-linux-aarch64.so.1"), @@ -1854,7 +1850,6 @@ pub fn ptrBitWidth_cpu_abi(cpu: Cpu, abi: Abi) u16 { .powerpc, .powerpcle, .riscv32, - .sparcel, .thumb, .thumbeb, .x86, @@ -1914,7 +1909,6 @@ pub fn stackAlignment(target: Target) u16 { .mips, .mipsel, .sparc, - .sparcel, => 8, .aarch64, .aarch64_be, @@ -2075,7 +2069,6 @@ pub fn c_type_bit_size(target: Target, c_type: CType) u16 { .s390x, .sparc, .sparc64, - .sparcel, .wasm32, .wasm64, => return 128, @@ -2180,7 +2173,6 @@ pub fn c_type_bit_size(target: Target, c_type: CType) u16 { .mips64el, .sparc, .sparc64, - .sparcel, .wasm32, .wasm64, => return 128, @@ -2374,7 +2366,6 @@ pub fn c_type_alignment(target: Target, c_type: CType) u16 { .mips, .mipsel, .sparc, - .sparcel, .sparc64, .lanai, .nvptx, @@ -2487,7 +2478,6 @@ pub fn c_type_preferred_alignment(target: Target, c_type: CType) u16 { .mips, .mipsel, .sparc, - .sparcel, .sparc64, .lanai, .nvptx, diff --git a/lib/std/atomic.zig b/lib/std/atomic.zig index be7203c0cffb..6de6d5437bd5 100644 --- a/lib/std/atomic.zig +++ b/lib/std/atomic.zig @@ -486,7 +486,6 @@ pub const cache_line = switch (builtin.cpu.arch) { .riscv32, .riscv64, .sparc, - .sparcel, .sparc64, => 32, diff --git a/lib/std/builtin.zig b/lib/std/builtin.zig index 86f8da6cd4ef..176b17dd07b4 100644 --- a/lib/std/builtin.zig +++ b/lib/std/builtin.zig @@ -615,7 +615,7 @@ pub const VaList = switch (builtin.cpu.arch) { else => VaListPowerPc, }, .powerpc64, .powerpc64le => *u8, - .sparc, .sparcel, .sparc64 => *anyopaque, + .sparc, .sparc64 => *anyopaque, .spirv32, .spirv64 => *anyopaque, .s390x => VaListS390x, .wasm32, .wasm64 => *anyopaque, diff --git a/lib/std/c.zig b/lib/std/c.zig index ff2c7dbd85bc..f6398720bf2e 100644 --- a/lib/std/c.zig +++ b/lib/std/c.zig @@ -5779,7 +5779,7 @@ pub const ucontext_t = switch (native_os) { .x86 => 4, .mips, .mipsel, .mips64, .mips64el => 14, .arm, .armeb, .thumb, .thumbeb => 1, - .sparc, .sparcel, .sparc64 => if (@sizeOf(usize) == 4) 43 else 8, + .sparc, .sparc64 => if (@sizeOf(usize) == 4) 43 else 8, else => 0, } ]u32, @@ -6821,7 +6821,7 @@ pub const pthread_key_t = switch (native_os) { pub const padded_pthread_spin_t = switch (native_os) { .netbsd => switch (builtin.cpu.arch) { .x86, .x86_64 => u32, - .sparc, .sparcel, .sparc64 => u32, + .sparc, .sparc64 => u32, else => pthread_spin_t, }, else => void, @@ -6834,7 +6834,7 @@ pub const pthread_spin_t = switch (native_os) { .powerpc, .powerpc64, .powerpc64le => i32, .x86, .x86_64 => u8, .arm, .armeb, .thumb, .thumbeb => i32, - .sparc, .sparcel, .sparc64 => u8, + .sparc, .sparc64 => u8, .riscv32, .riscv64 => u32, else => @compileError("undefined pthread_spin_t for this arch"), }, diff --git a/lib/std/os/linux.zig b/lib/std/os/linux.zig index 4f3db110b261..7bc8439370d8 100644 --- a/lib/std/os/linux.zig +++ b/lib/std/os/linux.zig @@ -2485,7 +2485,7 @@ pub const E = switch (native_arch) { pub const init = errnoFromSyscall; }, - .sparc, .sparcel, .sparc64 => enum(u16) { + .sparc, .sparc64 => enum(u16) { /// No error occurred. SUCCESS = 0, @@ -4832,7 +4832,6 @@ pub const MINSIGSTKSZ = switch (native_arch) { => 2048, .loongarch64, .sparc, - .sparcel, .sparc64, => 4096, .aarch64, @@ -4869,7 +4868,6 @@ pub const SIGSTKSZ = switch (native_arch) { .aarch64_be, .loongarch64, .sparc, - .sparcel, .sparc64, => 16384, .powerpc64, diff --git a/lib/std/os/linux/ioctl.zig b/lib/std/os/linux/ioctl.zig index 7f5d36b72db8..8b7cc80af968 100644 --- a/lib/std/os/linux/ioctl.zig +++ b/lib/std/os/linux/ioctl.zig @@ -11,7 +11,6 @@ const bits = switch (@import("builtin").cpu.arch) { .powerpc64le, .sparc, .sparc64, - .sparcel, => .{ .size = 13, .dir = 3, .none = 1, .read = 2, .write = 4 }, else => .{ .size = 14, .dir = 2, .none = 0, .read = 2, .write = 1 }, }; diff --git a/src/Type.zig b/src/Type.zig index 22e293101942..52844f7ca5f0 100644 --- a/src/Type.zig +++ b/src/Type.zig @@ -1602,7 +1602,6 @@ pub fn maxIntAlignment(target: std.Target, use_llvm: bool) u16 { .amdgcn, .riscv32, .sparc, - .sparcel, .s390x, .lanai, .wasm32, diff --git a/src/Zcu.zig b/src/Zcu.zig index bc7d2d2e494d..54faf34bf471 100644 --- a/src/Zcu.zig +++ b/src/Zcu.zig @@ -3248,7 +3248,6 @@ pub fn atomicPtrAlignment( .powerpcle, .riscv32, .sparc, - .sparcel, .thumb, .thumbeb, .x86, diff --git a/src/codegen/llvm.zig b/src/codegen/llvm.zig index fcbfa06bd2b2..4317c1b41fe3 100644 --- a/src/codegen/llvm.zig +++ b/src/codegen/llvm.zig @@ -69,7 +69,6 @@ pub fn targetTriple(allocator: Allocator, target: std.Target) ![]const u8 { .riscv64 => "riscv64", .sparc => "sparc", .sparc64 => "sparc64", - .sparcel => "sparcel", .s390x => "s390x", .thumb => "thumb", .thumbeb => "thumbeb", @@ -280,7 +279,6 @@ pub fn targetArch(arch_tag: std.Target.Cpu.Arch) llvm.ArchType { .riscv64 => .riscv64, .sparc => .sparc, .sparc64 => .sparcv9, // In LLVM, sparc64 == sparcv9. - .sparcel => .sparcel, .s390x => .systemz, .thumb => .thumb, .thumbeb => .thumbeb, @@ -469,7 +467,6 @@ const DataLayoutBuilder = struct { .powerpcle, .riscv32, .sparc, - .sparcel, .thumb, .thumbeb, .xtensa, @@ -12004,7 +12001,7 @@ pub fn initializeLLVMTarget(arch: std.Target.Cpu.Arch) void { llvm.LLVMInitializeRISCVAsmPrinter(); llvm.LLVMInitializeRISCVAsmParser(); }, - .sparc, .sparc64, .sparcel => { + .sparc, .sparc64 => { llvm.LLVMInitializeSparcTarget(); llvm.LLVMInitializeSparcTargetInfo(); llvm.LLVMInitializeSparcTargetMC(); diff --git a/src/glibc.zig b/src/glibc.zig index 6474a23dce02..5214d0a977cb 100644 --- a/src/glibc.zig +++ b/src/glibc.zig @@ -394,7 +394,7 @@ fn start_asm_path(comp: *Compilation, arena: Allocator, basename: []const u8) ![ const arch = comp.getTarget().cpu.arch; const is_ppc = arch == .powerpc or arch == .powerpc64 or arch == .powerpc64le; const is_aarch64 = arch == .aarch64 or arch == .aarch64_be; - const is_sparc = arch == .sparc or arch == .sparcel or arch == .sparc64; + const is_sparc = arch == .sparc or arch == .sparc64; const is_64 = comp.getTarget().ptrBitWidth() == 64; const s = path.sep_str; @@ -532,7 +532,7 @@ fn add_include_dirs_arch( const is_x86 = arch == .x86 or arch == .x86_64; const is_aarch64 = arch == .aarch64 or arch == .aarch64_be; const is_ppc = arch == .powerpc or arch == .powerpc64 or arch == .powerpc64le; - const is_sparc = arch == .sparc or arch == .sparcel or arch == .sparc64; + const is_sparc = arch == .sparc or arch == .sparc64; const is_64 = target.ptrBitWidth() == 64; const s = path.sep_str; diff --git a/src/link/Elf.zig b/src/link/Elf.zig index 5e5c05c1cdb1..70c28dfa351d 100644 --- a/src/link/Elf.zig +++ b/src/link/Elf.zig @@ -5175,7 +5175,7 @@ fn getLDMOption(target: std.Target) ?[]const u8 { .powerpc => return "elf32ppclinux", .powerpc64 => return "elf64ppc", .powerpc64le => return "elf64lppc", - .sparc, .sparcel => return "elf32_sparc", + .sparc => return "elf32_sparc", .sparc64 => return "elf64_sparc", .mips => return "elf32btsmip", .mipsel => return "elf32ltsmip", diff --git a/src/link/Plan9/aout.zig b/src/link/Plan9/aout.zig index 12dfc4587398..3d35bb9acbba 100644 --- a/src/link/Plan9/aout.zig +++ b/src/link/Plan9/aout.zig @@ -110,7 +110,7 @@ pub const R_MAGIC = _MAGIC(HDR_MAGIC, 28); // arm64 pub fn magicFromArch(arch: std.Target.Cpu.Arch) !u32 { return switch (arch) { .x86 => I_MAGIC, - .sparc => K_MAGIC, // TODO should sparc64 and sparcel go here? + .sparc => K_MAGIC, // TODO should sparc64 go here? .mips => V_MAGIC, .arm => E_MAGIC, .aarch64 => R_MAGIC, diff --git a/src/target.zig b/src/target.zig index e30743f65c30..62f3e52cb806 100644 --- a/src/target.zig +++ b/src/target.zig @@ -138,7 +138,6 @@ pub fn hasLlvmSupport(target: std.Target, ofmt: std.Target.ObjectFormat) bool { .riscv64, .sparc, .sparc64, - .sparcel, .s390x, .thumb, .thumbeb, @@ -408,7 +407,7 @@ pub fn defaultFunctionAlignment(target: std.Target) Alignment { return switch (target.cpu.arch) { .arm, .armeb => .@"4", .aarch64, .aarch64_be => .@"4", - .sparc, .sparcel, .sparc64 => .@"4", + .sparc, .sparc64 => .@"4", .riscv64 => .@"2", else => .@"1", }; @@ -423,7 +422,6 @@ pub fn minFunctionAlignment(target: std.Target) Alignment { .riscv32, .riscv64, .sparc, - .sparcel, .sparc64, => .@"2", else => .@"1", diff --git a/test/behavior/align.zig b/test/behavior/align.zig index 564e08bac13a..2c3fd6641287 100644 --- a/test/behavior/align.zig +++ b/test/behavior/align.zig @@ -95,7 +95,6 @@ test "alignment and size of structs with 128-bit fields" { .amdgcn, .riscv32, .sparc, - .sparcel, .s390x, .lanai, .wasm32, diff --git a/test/llvm_targets.zig b/test/llvm_targets.zig index 853ca1587922..71dc9e30a387 100644 --- a/test/llvm_targets.zig +++ b/test/llvm_targets.zig @@ -87,8 +87,6 @@ const targets = [_]std.Target.Query{ .{ .cpu_arch = .sparc, .os_tag = .freestanding, .abi = .none }, .{ .cpu_arch = .sparc, .os_tag = .linux, .abi = .gnu }, .{ .cpu_arch = .sparc, .os_tag = .linux, .abi = .none }, - .{ .cpu_arch = .sparcel, .os_tag = .freestanding, .abi = .none }, - .{ .cpu_arch = .sparcel, .os_tag = .linux, .abi = .gnu }, .{ .cpu_arch = .sparc64, .os_tag = .freestanding, .abi = .none }, .{ .cpu_arch = .sparc64, .os_tag = .linux, .abi = .gnu }, //.{ .cpu_arch = .spirv32, .os_tag = .opencl, .abi = .none }, From ef06e4b6e41b44b6be7417f2e29d7546aefa7b5e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Alex=20R=C3=B8nne=20Petersen?= Date: Tue, 30 Jul 2024 02:15:39 +0200 Subject: [PATCH 3/6] std.Target: Remove `ananas` OS tag. This is a fairly small hobby OS that has not seen development in 2 years. Our current policy is that hobby OSs should use the `other` tag. https://github.com/zhmu/ananas --- lib/compiler/aro/aro/target.zig | 1 - lib/std/Target.zig | 7 ------- src/codegen/llvm.zig | 2 -- 3 files changed, 10 deletions(-) diff --git a/lib/compiler/aro/aro/target.zig b/lib/compiler/aro/aro/target.zig index 1035bbaf7a01..f5387212815a 100644 --- a/lib/compiler/aro/aro/target.zig +++ b/lib/compiler/aro/aro/target.zig @@ -614,7 +614,6 @@ pub fn toLLVMTriple(target: std.Target, buf: []u8) []const u8 { const llvm_os = switch (target.os.tag) { .freestanding => "unknown", - .ananas => "ananas", .cloudabi => "cloudabi", .dragonfly => "dragonfly", .freebsd => "freebsd", diff --git a/lib/std/Target.zig b/lib/std/Target.zig index 729b7ff2ce0c..3557bc1c7200 100644 --- a/lib/std/Target.zig +++ b/lib/std/Target.zig @@ -17,7 +17,6 @@ pub const Os = struct { pub const Tag = enum { freestanding, - ananas, cloudabi, dragonfly, freebsd, @@ -140,7 +139,6 @@ pub const Os = struct { pub inline fn getVersionRangeTag(tag: Tag) @typeInfo(TaggedVersionRange).Union.tag_type.? { return switch (tag) { .freestanding, - .ananas, .cloudabi, .fuchsia, .ps3, @@ -372,7 +370,6 @@ pub const Os = struct { pub fn default(tag: Tag, arch: Cpu.Arch) VersionRange { return switch (tag) { .freestanding, - .ananas, .cloudabi, .fuchsia, .ps3, @@ -559,7 +556,6 @@ pub const Os = struct { .linux, .windows, .freestanding, - .ananas, .cloudabi, .fuchsia, .ps3, @@ -666,7 +662,6 @@ pub const Abi = enum { pub fn default(arch: Cpu.Arch, os: Os) Abi { return if (arch.isWasm()) .musl else switch (os.tag) { .freestanding, - .ananas, .cloudabi, .dragonfly, .ps3, @@ -1796,7 +1791,6 @@ pub const DynamicLinker = struct { // TODO go over each item in this list and either move it to the above list, or // implement the standard dynamic linker path code for it. - .ananas, .cloudabi, .fuchsia, .ps3, @@ -2089,7 +2083,6 @@ pub fn c_type_bit_size(target: Target, c_type: CType) u16 { .solaris, .illumos, .haiku, - .ananas, .fuchsia, .minix, => switch (target.cpu.arch) { diff --git a/src/codegen/llvm.zig b/src/codegen/llvm.zig index 4317c1b41fe3..8f042cf26564 100644 --- a/src/codegen/llvm.zig +++ b/src/codegen/llvm.zig @@ -133,7 +133,6 @@ pub fn targetTriple(allocator: Allocator, target: std.Target) ![]const u8 { .opencl, .glsl450, .plan9, - .ananas, .cloudabi, .minix, .contiki, @@ -205,7 +204,6 @@ pub fn targetOs(os_tag: std.Target.Os.Tag) llvm.OSType { .opencl, .glsl450, .plan9, - .ananas, .cloudabi, .minix, .contiki, From b49b7501cf040349eb6d86b63041c5152f23e5e8 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Alex=20R=C3=B8nne=20Petersen?= Date: Tue, 30 Jul 2024 02:17:00 +0200 Subject: [PATCH 4/6] std.Target: Remove `cloudabi` OS tag. It's discontinued in favor of WASI. https://github.com/NuxiNL/cloudlibc --- lib/compiler/aro/aro/target.zig | 1 - lib/std/Target.zig | 7 ------- src/codegen/llvm.zig | 2 -- 3 files changed, 10 deletions(-) diff --git a/lib/compiler/aro/aro/target.zig b/lib/compiler/aro/aro/target.zig index f5387212815a..2f46ebd60540 100644 --- a/lib/compiler/aro/aro/target.zig +++ b/lib/compiler/aro/aro/target.zig @@ -614,7 +614,6 @@ pub fn toLLVMTriple(target: std.Target, buf: []u8) []const u8 { const llvm_os = switch (target.os.tag) { .freestanding => "unknown", - .cloudabi => "cloudabi", .dragonfly => "dragonfly", .freebsd => "freebsd", .fuchsia => "fuchsia", diff --git a/lib/std/Target.zig b/lib/std/Target.zig index 3557bc1c7200..190a2e553fe7 100644 --- a/lib/std/Target.zig +++ b/lib/std/Target.zig @@ -17,7 +17,6 @@ pub const Os = struct { pub const Tag = enum { freestanding, - cloudabi, dragonfly, freebsd, fuchsia, @@ -139,7 +138,6 @@ pub const Os = struct { pub inline fn getVersionRangeTag(tag: Tag) @typeInfo(TaggedVersionRange).Union.tag_type.? { return switch (tag) { .freestanding, - .cloudabi, .fuchsia, .ps3, .zos, @@ -370,7 +368,6 @@ pub const Os = struct { pub fn default(tag: Tag, arch: Cpu.Arch) VersionRange { return switch (tag) { .freestanding, - .cloudabi, .fuchsia, .ps3, .zos, @@ -556,7 +553,6 @@ pub const Os = struct { .linux, .windows, .freestanding, - .cloudabi, .fuchsia, .ps3, .zos, @@ -662,7 +658,6 @@ pub const Abi = enum { pub fn default(arch: Cpu.Arch, os: Os) Abi { return if (arch.isWasm()) .musl else switch (os.tag) { .freestanding, - .cloudabi, .dragonfly, .ps3, .zos, @@ -1791,7 +1786,6 @@ pub const DynamicLinker = struct { // TODO go over each item in this list and either move it to the above list, or // implement the standard dynamic linker path code for it. - .cloudabi, .fuchsia, .ps3, .zos, @@ -2275,7 +2269,6 @@ pub fn c_type_bit_size(target: Target, c_type: CType) u16 { .longdouble => return 80, }, - .cloudabi, .ps3, .zos, .rtems, diff --git a/src/codegen/llvm.zig b/src/codegen/llvm.zig index 8f042cf26564..23e39caa987a 100644 --- a/src/codegen/llvm.zig +++ b/src/codegen/llvm.zig @@ -133,7 +133,6 @@ pub fn targetTriple(allocator: Allocator, target: std.Target) ![]const u8 { .opencl, .glsl450, .plan9, - .cloudabi, .minix, .contiki, .other, @@ -204,7 +203,6 @@ pub fn targetOs(os_tag: std.Target.Os.Tag) llvm.OSType { .opencl, .glsl450, .plan9, - .cloudabi, .minix, .contiki, => .UnknownOS, From c377316420be53f5db36f2fd2848d2abbfe34007 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Alex=20R=C3=B8nne=20Petersen?= Date: Tue, 30 Jul 2024 03:29:37 +0200 Subject: [PATCH 5/6] std.Target: Add `tce`/`tcele` to the comment listing omitted architectures. --- lib/std/Target.zig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/lib/std/Target.zig b/lib/std/Target.zig index 190a2e553fe7..1165bebf08c8 100644 --- a/lib/std/Target.zig +++ b/lib/std/Target.zig @@ -1030,6 +1030,8 @@ pub const Cpu = struct { // - aarch64_32 // - r600 // - sparcel + // - tce + // - tcele // - le32 // - le64 // - amdil From 62a01851d9c433ea3f2e98cc986e75d32aece443 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Alex=20R=C3=B8nne=20Petersen?= Date: Tue, 30 Jul 2024 04:36:43 +0200 Subject: [PATCH 6/6] glibc: Add a temporary hack in abilists loading due to sparcel removal. Revert this commit on the next glibc abilists update. --- src/glibc.zig | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/src/glibc.zig b/src/glibc.zig index 5214d0a977cb..85f1828ad432 100644 --- a/src/glibc.zig +++ b/src/glibc.zig @@ -122,6 +122,17 @@ pub fn loadMetaData(gpa: Allocator, contents: []const u8) LoadMetaDataError!*ABI return error.ZigInstallationCorrupt; }; const arch_tag = std.meta.stringToEnum(std.Target.Cpu.Arch, arch_name) orelse { + // TODO: Remove this on the next glibc abilists update. + if (mem.eql(u8, arch_name, "sparcel")) { + targets[i] = .{ + .arch = .sparc, + .os = .linux, + .abi = .gnu, + }; + + continue; + } + log.err("abilists: unrecognized arch: '{s}'", .{arch_name}); return error.ZigInstallationCorrupt; };