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Bumps [actions/stale](https://github.com/actions/stale) from 5 to 6. - [Release notes](https://github.com/actions/stale/releases) - [Changelog](https://github.com/actions/stale/blob/main/CHANGELOG.md) - [Commits](actions/stale@v5...v6) --- updated-dependencies: - dependency-name: actions/stale dependency-type: direct:production update-type: version-update:semver-major ... Signed-off-by: dependabot[bot] <support@github.com>
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Aug 4, 2024
…requency (memtest86plus#306) Read the memory controller configuration (instead of just relying on SPD data) to get the actual live settings. Currently supported platforms: * Intel SNB to RPL (Core 2nd Gen to Core 13th Gen) - Desktop only (no Server nor Mobile) * AMD SMR to RPL (Zen to Zen4) - Desktop only (no Server, Mobile nor APU). Individual commits below for archival: * First functions skeleton for reading IMC/ECC Registers * Change directory name from 'chipsets' to 'mch' (Memory Controller Hub) * Add Intel HSW and fix new files encoding * First Intel HSW IMC implementation * Add an option to disable MCH registers polling * Remove old include from Makefiles * Better Makefile and padding fixes * Statically init 'imc' struct to generate string relocation record * Small typos & code fixes * Add IMC support for Intel Core 6/7/8/9th Gen (SKL/KBL/CFL/CML) This is a bit more complex than Haswell and below because MMIO switched to 64-bit with Skylake (lot of) betatesting needed * Add IMC read support for Intel SNB/IVB (2nd/3rd gen Core) * Fix hard-lock on Intel SNB/IVB due to wrong access type on MCHBAR pointer * Move AMD SMN Registers & offsets to a specific header file * Add IMC Read support for AMD Zen/Zen2 CPUs * Change 'IMC' to 'MCH' in Makefiles to match actual mch/ directory * Add IMC Reading support for Intel ADL&RPL CPUs (Core Gen12&13) * Add support for Intel Rocket Lake (Core 11th Gen) and AMD Vermeer * Add IMC reading for AMD Zen4 'Raphael' AM5 CPUs * Various Cleanup #1 Change terminology from Intel-based 'MCH' (Memory Controller Hub) to more universal 'IMC' (Integrated Memory Controller) Integrate imc_type var into imc struct. Remove previously created AMD SNM header file * Various Cleanup 2 * Change DDR5 display format for IMC specs DDR5 Freq can be > 10000 and timings up to 63-127-127-127, which overwflow the available space. This commit remove the raw frequency on DDR5 (which may be incorrect due to Gear mechanism) and leave a bit of space to display the Gear engaged in the future
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Feb 8, 2025
…C CPUs (memtest86plus#485) * Change Address tests from SEQ to ONE for (much) faster startup on HCC CPUs This change will dramatically decreases the time needed to find the first fault on high core count CPUs by switching the address tests from all cores to one core. There is probably no (or very very few) cases where a computer will be allowed to pass basic POST if all cores can't reach all areas of the RAM, so this is probably the way to go * Removed and excluded mt8plus binary and switched Test #1 to ONE
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Bumps actions/stale from 5 to 6.
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3de2653Update changelog for v6.0.0 (#829)02e44c8fix(options)!: Makenot_plannedthe defaultclose-issue-reason(#807)Dependabot will resolve any conflicts with this PR as long as you don't alter it yourself. You can also trigger a rebase manually by commenting
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