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Merged
ATherkel merged 4 commits into from
May 6, 2024
Merged

Project 3 #4

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22e4ea8
Create .hdl files
ATherkel May 6, 2024
c55d26d
Out files
ATherkel May 6, 2024
2d43806
Images for forum question
ATherkel May 6, 2024
be13a59
Create project3.zip
ATherkel May 6, 2024
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3 changes: 2 additions & 1 deletion nand2tetris/projects/3/a/Bit.hdl
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Original file line number Diff line number Diff line change
Expand Up @@ -13,5 +13,6 @@ CHIP Bit {
OUT out;

PARTS:
//// Replace this comment with your code.
Mux(a = dffout, b = in, sel = load, out = dffin);
DFF(in = dffin, out = out, out = dffout);
}
215 changes: 215 additions & 0 deletions nand2tetris/projects/3/a/Bit.out
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Original file line number Diff line number Diff line change
@@ -0,0 +1,215 @@
| time |in |load|out|
| 0+ | 0 | 0 | 0 |
| 1 | 0 | 0 | 0 |
| 1+ | 0 | 1 | 0 |
| 2 | 0 | 1 | 0 |
| 2+ | 1 | 0 | 0 |
| 3 | 1 | 0 | 0 |
| 3+ | 1 | 1 | 0 |
| 4 | 1 | 1 | 1 |
| 4+ | 0 | 0 | 1 |
| 5 | 0 | 0 | 1 |
| 5+ | 1 | 0 | 1 |
| 6 | 1 | 0 | 1 |
| 6+ | 0 | 1 | 1 |
| 7 | 0 | 1 | 0 |
| 7+ | 1 | 1 | 0 |
| 8 | 1 | 1 | 1 |
| 8+ | 0 | 0 | 1 |
| 9 | 0 | 0 | 1 |
| 9+ | 0 | 0 | 1 |
| 10 | 0 | 0 | 1 |
| 10+ | 0 | 0 | 1 |
| 11 | 0 | 0 | 1 |
| 11+ | 0 | 0 | 1 |
| 12 | 0 | 0 | 1 |
| 12+ | 0 | 0 | 1 |
| 13 | 0 | 0 | 1 |
| 13+ | 0 | 0 | 1 |
| 14 | 0 | 0 | 1 |
| 14+ | 0 | 0 | 1 |
| 15 | 0 | 0 | 1 |
| 15+ | 0 | 0 | 1 |
| 16 | 0 | 0 | 1 |
| 16+ | 0 | 0 | 1 |
| 17 | 0 | 0 | 1 |
| 17+ | 0 | 0 | 1 |
| 18 | 0 | 0 | 1 |
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| 84+ | 1 | 0 | 0 |
| 85 | 1 | 0 | 0 |
| 85+ | 1 | 0 | 0 |
| 86 | 1 | 0 | 0 |
| 86+ | 1 | 0 | 0 |
| 87 | 1 | 0 | 0 |
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| 88+ | 1 | 0 | 0 |
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| 105+ | 1 | 0 | 0 |
| 106 | 1 | 0 | 0 |
| 106+ | 1 | 0 | 0 |
| 107 | 1 | 0 | 0 |
49 changes: 48 additions & 1 deletion nand2tetris/projects/3/a/PC.hdl
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Original file line number Diff line number Diff line change
Expand Up @@ -14,5 +14,52 @@ CHIP PC {
OUT out[16];

PARTS:
//// Replace this comment with your code.

/*
reset = 1:
0
reset = 0:
load = 1:
in
load = 0:
inc = 1:
out + 1
inc = 0
out

*/

Inc16(
in = regout,
out = incout
);

Mux16(
a = regout,
b = incout,
sel = inc,
out = outOrInc
);

Mux16(
a = outOrInc,
b = in,
sel = load,
out = outOrIncOrLoad
);

Mux16(
a = outOrIncOrLoad,
b = false,
sel = reset,
out = regin
);


Register(
in = regin,
load = true,
out = regout,
out = out
);
}
31 changes: 31 additions & 0 deletions nand2tetris/projects/3/a/PC.out
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Original file line number Diff line number Diff line change
@@ -0,0 +1,31 @@
|time | in |reset|load | inc | out |
| 0+ | 0 | 0 | 0 | 0 | 0 |
| 1 | 0 | 0 | 0 | 0 | 0 |
| 1+ | 0 | 0 | 0 | 1 | 0 |
| 2 | 0 | 0 | 0 | 1 | 1 |
| 2+ | -32123 | 0 | 0 | 1 | 1 |
| 3 | -32123 | 0 | 0 | 1 | 2 |
| 3+ | -32123 | 0 | 1 | 1 | 2 |
| 4 | -32123 | 0 | 1 | 1 | -32123 |
| 4+ | -32123 | 0 | 0 | 1 | -32123 |
| 5 | -32123 | 0 | 0 | 1 | -32122 |
| 5+ | -32123 | 0 | 0 | 1 | -32122 |
| 6 | -32123 | 0 | 0 | 1 | -32121 |
| 6+ | 12345 | 0 | 1 | 0 | -32121 |
| 7 | 12345 | 0 | 1 | 0 | 12345 |
| 7+ | 12345 | 1 | 1 | 0 | 12345 |
| 8 | 12345 | 1 | 1 | 0 | 0 |
| 8+ | 12345 | 0 | 1 | 1 | 0 |
| 9 | 12345 | 0 | 1 | 1 | 12345 |
| 9+ | 12345 | 1 | 1 | 1 | 12345 |
| 10 | 12345 | 1 | 1 | 1 | 0 |
| 10+ | 12345 | 0 | 0 | 1 | 0 |
| 11 | 12345 | 0 | 0 | 1 | 1 |
| 11+ | 12345 | 1 | 0 | 1 | 1 |
| 12 | 12345 | 1 | 0 | 1 | 0 |
| 12+ | 0 | 0 | 1 | 1 | 0 |
| 13 | 0 | 0 | 1 | 1 | 0 |
| 13+ | 0 | 0 | 0 | 1 | 0 |
| 14 | 0 | 0 | 0 | 1 | 1 |
| 14+ | 22222 | 1 | 0 | 0 | 1 |
| 15 | 22222 | 1 | 0 | 0 | 0 |
31 changes: 30 additions & 1 deletion nand2tetris/projects/3/a/RAM64.hdl
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Original file line number Diff line number Diff line change
Expand Up @@ -13,5 +13,34 @@ CHIP RAM64 {
OUT out[16];

PARTS:
//// Replace this comment with your code.
DMux8Way(in = load, sel = address[3..5],
a = selram0,
b = selram1,
c = selram2,
d = selram3,
e = selram4,
f = selram5,
g = selram6,
h = selram7);

RAM8(in = in, load = selram0, address = address[0..2], out = ram0);
RAM8(in = in, load = selram1, address = address[0..2], out = ram1);
RAM8(in = in, load = selram2, address = address[0..2], out = ram2);
RAM8(in = in, load = selram3, address = address[0..2], out = ram3);
RAM8(in = in, load = selram4, address = address[0..2], out = ram4);
RAM8(in = in, load = selram5, address = address[0..2], out = ram5);
RAM8(in = in, load = selram6, address = address[0..2], out = ram6);
RAM8(in = in, load = selram7, address = address[0..2], out = ram7);

Mux8Way16(
a = ram0,
b = ram1,
c = ram2,
d = ram3,
e = ram4,
f = ram5,
g = ram6,
h = ram7,
sel = address[3..5],
out = out);
}
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