Why does the larger the capacity of CMT, the smaller the end-to-end delay?

[nayoaixw]

Hello, I now encountered a problem : after many experiments, I found that the larger the capacity of CMT, the smaller the end-to-end delay, which is contrary to my idea. My workload is wsrch-samll, and the configuration only changes the CMT _ Capacity ( 256KB, 512KB, 1MB, 2MB... ) on the basis of the project source code. May I have some suggestions? I have seen before someone asked this question, but the issue is now closed, I am very anxious now, hope you can help me. Best wishes!

[Liao-Liwei]

from the DFTL paper, we learn that the larger the size of CMT, the more LPN-PPN mappings can be cached, leading to an increase in CMT_HIT and a reduction in CMT_MISS and the associated Double Read in the flash memory. This decreases flash reads, resulting in lower end-to-end latency.