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ChipFlow / chipflow-lib Public

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feat(rtl): support Verilog module parameters in RTLWrapper#162

Merged

lanserge merged 4 commits into

mainChipFlow/chipflow-lib:mainfrom

rtl/wrapper-parametersChipFlow/chipflow-lib:rtl/wrapper-parametersCopy head branch name to clipboard

Apr 22, 2026

Conversation Commits4 (4)Checks Files changed

Merged

feat(rtl): support Verilog module parameters in RTLWrapper#162
lanserge merged 4 commits into
mainfrom
rtl/wrapper-parameters

Commits

Commits on Apr 22, 2026

feat(rtl): support Verilog module parameters in RTLWrapper
lanserge
committed
test(rtl): cover RTLWrapper parameter merge and emission
lanserge
committed
docs: add RTL wrapper reference page linking to training docs
lanserge
committed
ci: trigger CI workflow after re-enable
lanserge
committed

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