invalid register pair

[nickdesaulniers]

(working around #1356)
This one looks like a codegen bug to me:

$ ARCH=s390 CROSS_COMPILE=s390x-linux-gnu- make -j72 CC=clang LLVM_IAS=1 -j72 defconfig arch/s390/lib/test_unwind.o
...
arch/s390/lib/test_unwind.c:177:4: error: invalid register pair
                        "       mvcl    %%r1,%%r1\n"
                        ^
<inline asm>:1:8: note: instantiated into assembly here
                mvcl    %r1,%r1
                        ^

[uweigand]

The Linux code in question:

                /*
                 * trigger specification exception
                 */
                asm volatile(
                        "       mvcl    %%r1,%%r1\n"
                        "0:     nopr    %%r7\n"
                        EX_TABLE(0b, 0b)
                        :);

deliberately creates an invalid instruction that will always trap at runtime. Apparently this is intended to verify that the kernel exception handling logic works and catches this trap.

However, the LLVM inline assembler validates the instruction, and as it is indeed invalid, refuses to accept it. I don't think it would be a good idea to remove that check from LLVM, it is generally very useful.

Probably the best way would be to rewrite this in the Linux sources, e.g. by just hard-coding the insn opcode.

[nickdesaulniers]

We have something like __inst_arm for encoding problematic instructions (which I used in e9d54be). Need to check if there's an equivalent for s390.

Looks like mvcl %r1, %r1 would be encoded as:

0e 11                   mvcl    %r1,%r1

[ihalip]

We have something like __inst_arm for encoding problematic instructions. Need to check if there's an equivalent for s390.

Looks easy enough, mind if I look at this?

[ihalip]

Submitted: https://lore.kernel.org/linux-s390/20211117174822.3632412-1-ilie.halip@gmail.com/T/#u

[ihalip]

Now in linux-next. https://git.kernel.org/pub/scm/linux/kernel/git/s390/linux.git/commit/?h=fixes&id=53ae7230918154d1f4281d7aa3aae9650436eadf

[ihalip]

Merged in 5.16-rc4.