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In the current code, the bl808_fill_tx_fifo() is called first (if we still have some data to send). It will decrease the msg_buf_remaining field, possibility to 0. If we have more messages to send, the next if statement will be true and a bl808_i2c_start_transfer() will be called for the next message without waiting for actually finishing the message that we have just filled the FIFO for. This patch changes the order, to: 1. (unchanged) If no more bytes to send and no more messages, we're done. 2. Otherwise if we don't have bytes to send (but we have more messages because otherwise we would leave at step 1), prepare next message for sending. 3. Otherwise, we have some data to send in current message so fill the TX FIFO up.
In current code, the TX FIFO is only filled when we get the TXF interrupt. This means that at the moment the transaction is started by setting the M_EN bit in CONFIG register, the TX FIFO is empty. This should trigger both the TXF (because TX FIFO is empty) and FER (with TX underflow) because the controller has nothing to send. We don't know what is the exact condition that trigger TX underflow because apparently in most cases we get TXF first but maybe if we are not fast enough, we may actually get FER? Let's remove that uncertainty by filling the TX FIFO before starting the transaction.
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@kadamski i find it very nice of you to help me get the code out, so i am really glad for your input 😊 |
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If you still have patience for my changes, let's check if maybe those two fixes can help the TX fifo underflow problem.