Aspiring VLSI engineer with interests in RTL design, verification, and computer architecture.
- Hyderabad
- in/kuncham-koteswar
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RISC-V-Out-of-Order-Pipeline-Processor
RISC-V-Out-of-Order-Pipeline-Processor PublicDesigned and simulation based verification on RISC-V Out-of-Order processor using SystemVerilog, supporting dynamic scheduling, register renaming, and in-order retirement. Developed synthesizable R…
SystemVerilog 2
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Telegram-AI-Bot
Telegram-AI-Bot PublicA Telegram bot that uses Google's Gemini AI for chat, image analysis, and web search.
Python 1
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