Verilog Project Template

Fibonacci Youtube Video

Mr Chips Report

Mr Chips Greencard

We chose to implement a MIPS architecture because we were most familiar with it from class. At first, we wanted to implement an 8-bit CPU with 8-bit instructions, but this design would not allow for enough instructions. When realizing this, we decided that we should use 16-bit instructions. Somewhere down this line, we decided that we may as well make the ALU operand size 16-bits as well. As the sages say, “good design demands good compromise.”

To compile then simulate:

make clean compile simulate

To disply simulation using GTKWAVE:

make display

Then choose "mr_chips_tb" as your SST. Highlight "uut" and choose all signals, dragging them to Signal area to right. Once done, got to menu Time -> Zoom -> Zoom Bet Fit.

To clean up:

make clean