Validator does not check assignments properly

[EAlexJ]

The following tweaked JAL is not legal, but passes the validator:

InstructionSet Bugged extends RISCVBase{
    instructions {
        JAL {
            encoding: imm[20:20] :: imm[10:1] :: imm[11:11] :: imm[19:12] :: rd[4:0] :: 7'b1101111;
            assembly: "{name(rd)}, {imm:#0x}";
            behavior: if(rd >= RFS) raise(0, 2); else {
                unsigned<XLEN> new_pc = (unsigned<XLEN>)(PC + (signed)imm);
                if (new_pc % INSTR_ALIGNMENT) {
                    set_tval(new_pc);
                    raise(0, 0);
                } else {
                    if (rd != 0) X[rd] = (PC + 4); // should be (unsigned<XLEN>)(PC + 4) as addition increases size 
                    PC = new_pc;
                }
            }
        }
    }
}