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@JDBetteridge JDBetteridge commented May 27, 2022

This is just an idea for how to avoid using the py-cpuinfo package.

To be completely honest I'm not sure this is even necessary:

  • It will only work on x86_64 architectures (this is also true of py-cpuinfo)
  • It feels hacky
  • The default of PYOP2_SIMD_WIDTH=4 covers almost all use cases (with the exception of AVX512*)

If a user really wants to change the SIMD width used within PYOP2 they should manually set PYOP2_SIMD_WIDTH, I don't really think we should try and sniff this value.

*My impression is that using AVX512 normally incurs a performance penalty due to the CPU having to downclock. A benchmark might convince me otherwise.

@connorjward
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I agree. I think defaulting to 4, and allowing users to change things, is a completely reasonable approach here.

Are there ever circumstances where this might cause a breakage?

@wence-
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wence- commented May 28, 2022

I agree. I think defaulting to 4, and allowing users to change things, is a completely reasonable approach here.

Are there ever circumstances where this might cause a breakage?

M1 cores have 128bit vectors. But I think that going for four wide (effectively 256bit vectors) would be fine.

@sv2518 sv2518 marked this pull request as ready for review June 22, 2022 14:14
@sv2518 sv2518 merged commit 2840f28 into vectorisation-sprint Jun 22, 2022
@sv2518 sv2518 deleted the JDBetteridge/vectorisation-sprint branch June 22, 2022 14:14
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sv2518 commented Jun 22, 2022

Thanks, Jack!

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5 participants