SN54H87: 4 bit True/Compliment, Zero/One Elements

library/SubcircuitLibrary/74ACT11240/SC_74ACT11240-cache.lib

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+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# d_inverter
+#
+DEF d_inverter U 0 40 Y Y 1 F N
+F0 "U" 0 -100 60 H V C CNN
+F1 "d_inverter" 0 150 60 H V C CNN
+F2 "" 50 -50 60 H V C CNN
+F3 "" 50 -50 60 H V C CNN
+DRAW
+P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N
+X ~ 1 -300 0 200 R 50 50 1 1 I
+X ~ 2 300 0 200 L 50 50 1 1 O I
+ENDDRAW
+ENDDEF
+#
+# d_tristate
+#
+DEF d_tristate U 0 40 Y Y 1 F N
+F0 "U" -250 250 60 H V C CNN
+F1 "d_tristate" -200 450 60 H V C CNN
+F2 "" -100 350 60 H V C CNN
+F3 "" -100 350 60 H V C CNN
+DRAW
+P 4 0 1 0 -400 550 -400 150 350 350 -400 550 N
+X IN 1 -600 350 200 R 50 50 1 1 I
+X EN 2 -50 50 193 U 50 50 1 1 I
+X OUT 3 550 350 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+#End Library

library/SubcircuitLibrary/74ACT11240/SC_74ACT11240.cir

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+* C:\FOSSEE2\eSim\library\SubcircuitLibrary\SC_74ACT11240\SC_74ACT11240.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 06/17/25 21:34:12
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+U2  Net-_U1-Pad24_ Net-_U2-Pad2_ d_inverter		
+U3  Net-_U1-Pad23_ Net-_U2-Pad2_ Net-_U3-Pad3_ d_tristate		
+U4  Net-_U1-Pad22_ Net-_U2-Pad2_ Net-_U4-Pad3_ d_tristate		
+U5  Net-_U1-Pad21_ Net-_U2-Pad2_ Net-_U5-Pad3_ d_tristate		
+U6  Net-_U1-Pad20_ Net-_U2-Pad2_ Net-_U10-Pad1_ d_tristate		
+U11  Net-_U1-Pad13_ Net-_U11-Pad2_ d_inverter		
+U12  Net-_U1-Pad17_ Net-_U11-Pad2_ Net-_U12-Pad3_ d_tristate		
+U13  Net-_U1-Pad16_ Net-_U11-Pad2_ Net-_U13-Pad3_ d_tristate		
+U14  Net-_U1-Pad15_ Net-_U11-Pad2_ Net-_U14-Pad3_ d_tristate		
+U15  Net-_U1-Pad14_ Net-_U11-Pad2_ Net-_U15-Pad3_ d_tristate		
+U1  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ ? ? ? ? Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ Net-_U1-Pad15_ Net-_U1-Pad16_ Net-_U1-Pad17_ ? ? Net-_U1-Pad20_ Net-_U1-Pad21_ Net-_U1-Pad22_ Net-_U1-Pad23_ Net-_U1-Pad24_ PORT		
+U7  Net-_U3-Pad3_ Net-_U1-Pad1_ d_inverter		
+U8  Net-_U4-Pad3_ Net-_U1-Pad2_ d_inverter		
+U9  Net-_U5-Pad3_ Net-_U1-Pad3_ d_inverter		
+U10  Net-_U10-Pad1_ Net-_U1-Pad4_ d_inverter		
+U16  Net-_U12-Pad3_ Net-_U1-Pad9_ d_inverter		
+U17  Net-_U13-Pad3_ Net-_U1-Pad10_ d_inverter		
+U18  Net-_U14-Pad3_ Net-_U1-Pad11_ d_inverter		
+U19  Net-_U15-Pad3_ Net-_U1-Pad12_ d_inverter		
+
+.end

library/SubcircuitLibrary/74ACT11240/SC_74ACT11240.cir.out

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+* c:\fossee2\esim\library\subcircuitlibrary\sc_74act11240\sc_74act11240.cir
+
+* u2  net-_u1-pad24_ net-_u2-pad2_ d_inverter
+* u3  net-_u1-pad23_ net-_u2-pad2_ net-_u3-pad3_ d_tristate
+* u4  net-_u1-pad22_ net-_u2-pad2_ net-_u4-pad3_ d_tristate
+* u5  net-_u1-pad21_ net-_u2-pad2_ net-_u5-pad3_ d_tristate
+* u6  net-_u1-pad20_ net-_u2-pad2_ net-_u10-pad1_ d_tristate
+* u11  net-_u1-pad13_ net-_u11-pad2_ d_inverter
+* u12  net-_u1-pad17_ net-_u11-pad2_ net-_u12-pad3_ d_tristate
+* u13  net-_u1-pad16_ net-_u11-pad2_ net-_u13-pad3_ d_tristate
+* u14  net-_u1-pad15_ net-_u11-pad2_ net-_u14-pad3_ d_tristate
+* u15  net-_u1-pad14_ net-_u11-pad2_ net-_u15-pad3_ d_tristate
+* u1  net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ ? ? ? ? net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ net-_u1-pad16_ net-_u1-pad17_ ? ? net-_u1-pad20_ net-_u1-pad21_ net-_u1-pad22_ net-_u1-pad23_ net-_u1-pad24_ port
+* u7  net-_u3-pad3_ net-_u1-pad1_ d_inverter
+* u8  net-_u4-pad3_ net-_u1-pad2_ d_inverter
+* u9  net-_u5-pad3_ net-_u1-pad3_ d_inverter
+* u10  net-_u10-pad1_ net-_u1-pad4_ d_inverter
+* u16  net-_u12-pad3_ net-_u1-pad9_ d_inverter
+* u17  net-_u13-pad3_ net-_u1-pad10_ d_inverter
+* u18  net-_u14-pad3_ net-_u1-pad11_ d_inverter
+* u19  net-_u15-pad3_ net-_u1-pad12_ d_inverter
+a1 net-_u1-pad24_ net-_u2-pad2_ u2
+a2 net-_u1-pad23_ net-_u2-pad2_ net-_u3-pad3_ u3
+a3 net-_u1-pad22_ net-_u2-pad2_ net-_u4-pad3_ u4
+a4 net-_u1-pad21_ net-_u2-pad2_ net-_u5-pad3_ u5
+a5 net-_u1-pad20_ net-_u2-pad2_ net-_u10-pad1_ u6
+a6 net-_u1-pad13_ net-_u11-pad2_ u11
+a7 net-_u1-pad17_ net-_u11-pad2_ net-_u12-pad3_ u12
+a8 net-_u1-pad16_ net-_u11-pad2_ net-_u13-pad3_ u13
+a9 net-_u1-pad15_ net-_u11-pad2_ net-_u14-pad3_ u14
+a10 net-_u1-pad14_ net-_u11-pad2_ net-_u15-pad3_ u15
+a11 net-_u3-pad3_ net-_u1-pad1_ u7
+a12 net-_u4-pad3_ net-_u1-pad2_ u8
+a13 net-_u5-pad3_ net-_u1-pad3_ u9
+a14 net-_u10-pad1_ net-_u1-pad4_ u10
+a15 net-_u12-pad3_ net-_u1-pad9_ u16
+a16 net-_u13-pad3_ net-_u1-pad10_ u17
+a17 net-_u14-pad3_ net-_u1-pad11_ u18
+a18 net-_u15-pad3_ net-_u1-pad12_ u19
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_tristate, NgSpice Name: d_tristate
+.model u3 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) 
+* Schematic Name:                             d_tristate, NgSpice Name: d_tristate
+.model u4 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) 
+* Schematic Name:                             d_tristate, NgSpice Name: d_tristate
+.model u5 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) 
+* Schematic Name:                             d_tristate, NgSpice Name: d_tristate
+.model u6 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u11 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_tristate, NgSpice Name: d_tristate
+.model u12 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) 
+* Schematic Name:                             d_tristate, NgSpice Name: d_tristate
+.model u13 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) 
+* Schematic Name:                             d_tristate, NgSpice Name: d_tristate
+.model u14 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) 
+* Schematic Name:                             d_tristate, NgSpice Name: d_tristate
+.model u15 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u8 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u9 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u10 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u16 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u17 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u18 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u19 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+.tran 10e-03 100e-03 0e-03
+
+* Control Statements 
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end

library/SubcircuitLibrary/74ACT11240/SC_74ACT11240.pro

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+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_Nghdl
+LibName38=eSim_Ngveri
+LibName39=eSim_SKY130
+LibName40=eSim_SKY130_Subckts