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add fp32 input #1706

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Merged
valarLip merged 7 commits into from
Dec 24, 2025
Merged

add fp32 input #1706

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6490ffd
add fp32 input
amd-zfyu Dec 22, 2025
2fdbd0c
format code
amd-zfyu Dec 22, 2025
27138f5
perf bug fix
amd-zfyu Dec 22, 2025
4594cf9
logic fix : out type != input type
amd-zfyu Dec 22, 2025
5758cf0
bug fix
amd-zfyu Dec 23, 2025
3ba2d82
format code
amd-zfyu Dec 23, 2025
449504c
remove dtype convert before act_and_mul in fused_moe
junhaha666 Dec 23, 2025
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8 changes: 4 additions & 4 deletions aiter/fused_moe.py
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Original file line number Diff line number Diff line change
Expand Up @@ -1132,9 +1132,9 @@ def asm_stage1(
)
if ksplit > 0:
if activation == ActivationType.Silu:
aiter.silu_and_mul(out, tmp_out.view(dtypes.fp32).to(dtype))
aiter.silu_and_mul(out, tmp_out.view(dtypes.fp32))
else:
aiter.gelu_and_mul(out, tmp_out.view(dtypes.fp32).to(dtype))
aiter.gelu_and_mul(out, tmp_out.view(dtypes.fp32))
return out


Expand Down Expand Up @@ -1446,9 +1446,9 @@ def ck_moe_stage1(
)
if splitk > 1:
if activation == ActivationType.Silu:
aiter.silu_and_mul(out, tmp_out.view(dtypes.fp32).to(out.dtype))
aiter.silu_and_mul(out, tmp_out.view(dtypes.fp32))
else:
aiter.gelu_and_mul(out, tmp_out.view(dtypes.fp32).to(out.dtype))
aiter.gelu_and_mul(out, tmp_out.view(dtypes.fp32))
return out


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