Dispatch combine #571
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Dispatch combine #571
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valarLip
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Jul 2, 2025
fsx950223
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Jul 2, 2025
* add dispatch combine * fix dispatch combine bug * add moe ep to test * format * ci * remove ck_moe * fix prebuild * update ck * update test for mori update * update * clear code * update test * add quant argument for test --------- Co-authored-by: valarLip <340077269@qq.com> Co-authored-by: TianDi101 <Di.Tian2@amd.com> Co-authored-by: amd-ruitang3 <Rui.Tang2@amd.com>
valarLip
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Jul 2, 2025
* refresh pa rocm * optimize performance * remove useless deps * adapt for gfx950 draft * pass v cache one test * fix mtp bugs * remove print * format code * fix a bug * support vary query length * remove torch deps * enable pa mtp * update api * remove useless template arg * optimize performance * revert changes * fix format * revert change * revert change * support head dim 256 * fix ci error * fix unit test * fix bugs * remove descrpted api * remove comments * fix api * fix alibi slopes * fix polential bug * support gqa32 * strip archs * add pa v1 api * update pa * add paged attention v * optimize performance * fix fp8 vlds * add debug log * add env * add logs to utils * fix pa v1 fp8 accuracy issue * optimize performance a little * optimize perf a little * fix a bug * fix workspace bug * refactor pa ragged * fix format * remove useless file * remove useless file * remove useless code * robust utils * add rocm6.4 support * fix type hint * fix pa rocm unit test * adapt to latest triton * Dispatch combine (#571) * add dispatch combine * fix dispatch combine bug * add moe ep to test * format * ci * remove ck_moe * fix prebuild * update ck * update test for mori update * update * clear code * update test * add quant argument for test --------- Co-authored-by: valarLip <340077269@qq.com> Co-authored-by: TianDi101 <Di.Tian2@amd.com> Co-authored-by: amd-ruitang3 <Rui.Tang2@amd.com> --------- Co-authored-by: chenjun <46212055+junhaha666@users.noreply.github.com> Co-authored-by: valarLip <340077269@qq.com> Co-authored-by: TianDi101 <Di.Tian2@amd.com> Co-authored-by: amd-ruitang3 <Rui.Tang2@amd.com>
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