Digital logic implementation and verification using hardware description languages.
This repository is meant for logic design and verification, starting from the simplest of blocks such as a half adder, all the way to FSMs and beyond.
The repository has been divided into two main directories :
- Concepts -> Contains the theoretical aspects of digital circuits, starting from logic gates
- Implementation and Results -> Contains the HDL implementation and test suite for simulating the
behaviour of each of the blocks
System verilog has been used in all the cases for coding. 2012 SV Manual has been uploaded as well for quick lookup.