Code reorganization for I/O APIC support

LICENSE

@@ -1,6 +1,6 @@
 MIT License
 
-Copyright (c) 2023 Return Infinity
+Copyright (c) 2024 Return Infinity
 
 Permission is hereby granted, free of charge, to any person obtaining a copy
 of this software and associated documentation files (the "Software"), to deal

docs/CREDITS.TXT

@@ -1,6 +1,6 @@
 ===============================================================================
 Pure64 -- a 64-bit loader written in Assembly for x86-64 systems
-Copyright (C) 2008-2023 Return Infinity -- see LICENSE.TXT
+Copyright (C) 2008-2024 Return Infinity -- see LICENSE.TXT
 ===============================================================================
 
 

docs/README.md

@@ -175,18 +175,47 @@ The Pure64 information table is located at `0x0000000000005000` and ends at `0x0
 <tr><td>0x5016 - 0x501F</td><td>&nbsp;</td><td>&nbsp;</td><td>For future use</td></tr>
 <tr><td>0x5020</td><td>32-bit</td><td>RAMAMOUNT</td><td>Amount of system RAM in Mebibytes (<a href="http://en.wikipedia.org/wiki/Mebibyte">MiB</a>)</td></tr>
 <tr><td>0x5022 - 0x502F</td><td>&nbsp;</td><td>&nbsp;</td><td>For future use</td></tr>
-<tr><td>0x5030</td><td>8-bit</td><td>IOAPIC_COUNT</td><td>Number of IO-APICs in the system</td></tr>
-<tr><td>0x5031 - 0x503F</td><td>&nbsp;</td><td>&nbsp;</td><td>For future use</td></tr>
+<tr><td>0x5030</td><td>8-bit</td><td>IOAPIC_COUNT</td><td>Number of I/O APICs in the system</td></tr>
+<tr><td>0x5031</td><td>8-bit</td><td>IOAPIC_INTSOURCE_COUNT</td><td>Number of I/O APIC Interrupt Source Override</td></tr>
+<tr><td>0x5032 - 0x503F</td><td>&nbsp;</td><td>&nbsp;</td><td>For future use</td></tr>
 <tr><td>0x5040</td><td>64-bit</td><td>HPET</td><td>Base memory address for the High Precision Event Timer</td></tr>
 <tr><td>0x5048 - 0x505F</td><td>&nbsp;</td><td>&nbsp;</td><td>For future use</td></tr>
 <tr><td>0x5060</td><td>64-bit</td><td>LAPIC</td><td>Local APIC address</td></tr>
-<tr><td>0x5068 - 0x507F</td><td>64-bit</td><td>IOAPIC</td><td>IO-APIC addresses (based on IOAPIC_COUNT)</td></tr>
+<tr><td>0x5068 - 0x507F</td><td>&nbsp;</td><td>&nbsp;</td><td>For future use</td></tr>
 <tr><td>0x5080</td><td>32-bit</td><td>VIDEO_BASE</td><td>Base memory for video (if graphics mode set)</td></tr>
 <tr><td>0x5084</td><td>16-bit</td><td>VIDEO_X</td><td>X resolution</td></tr>
 <tr><td>0x5086</td><td>16-bit</td><td>VIDEO_Y</td><td>Y resolution</td></tr>
 <tr><td>0x5088</td><td>8-bit</td><td>VIDEO_DEPTH</td><td>Color depth</td></tr>
 <tr><td>0x5089 - 0x50FF</td><td>&nbsp;</td><td>&nbsp;</td><td>For future use</td></tr>
-<tr><td>0x5100...</td><td>8-bit</td><td>APIC_ID</td><td>APIC ID's for valid CPU cores (based on CORES_ACTIVE)</td></tr>
+<tr><td>0x5100 - 0x51FF</td><td>8-bit</td><td>APIC_ID</td><td>APIC ID's for valid CPU cores (based on CORES_ACTIVE)</td></tr>
+<tr><td>0x5200 - 0x56FF</td><td>&nbsp;</td><td>&nbsp;</td><td>For future use</td></tr>
+<tr><td>0x5600 - 0x56FF</td><td>16 byte entries</td><td>IOAPIC</td><td>I/O APIC addresses (based on IOAPIC_COUNT)</td></tr>
+<tr><td>0x5700 - 0x57FF</td><td>8 byte entries</td><td>IOAPIC_INTSOURCE</td><td>I/O APIC Interrupt Source Override Entries (based on IOAPIC_INTSOURCE_COUNT)</td></tr>
+</table>
+
+IOAPIC list format:
+<table border="1" cellpadding="2" cellspacing="0">
+<tr><th>Offset</th><th>Variable Size</th><th>Name</th><th>Description</th></tr>
+<tr><td>0x00</td><td>32-bit</td><td>I/O APIC ID</td><td>The ID of an I/O APIC</td></tr>
+<tr><td>0x00</td><td>32-bit</td><td>I/O APIC Address</td><td>The 32-bit physical address to access this I/O APIC</td></tr>
+<tr><td>0x00</td><td>32-bit</td><td>Global System Interrupt Base</td><td>The global system interrupt number where this I/O APIC’s interrupt inputs start</td></tr>
+<tr><td>0x00</td><td>32-bit</td><td>Reserved</td><td>This value should be 0</td></tr>
+</table>
+
+IOAPIC_INTSOURCE list format:
+<table border="1" cellpadding="2" cellspacing="0">
+<tr><th>Offset</th><th>Variable Size</th><th>Name</th><th>Description</th></tr>
+<tr><td>0x00</td><td>8-bit</td><td>Bus</td><td>0</td></tr>
+<tr><td>0x00</td><td>8-bit</td><td>Source</td><td>Bus-relative interrupt source</td></tr>
+<tr><td>0x00</td><td>32-bit</td><td>Global System Interrupt</td><td>The Global System Interrupt that this bus-relative interrupt source will signal</td></tr>
+<tr><td>0x00</td><td>16-bit</td><td>Flags</td><td>MPS INTI flags</td></tr>
+</table>
+
+MPS INTI flags:
+<table border="1" cellpadding="2" cellspacing="0">
+<tr><th>Flags</th><th>Bit Length</th><th>Bit Offset</th><th>Description</th></tr>
+<tr><td>Polarity</td><td>2</td><td>0</td><td>01 Active high, 11 Active low</td></tr>
+<tr><td>Trigger Mode</td><td>2</td><td>2</td><td>01 Edge-triggered, 11 Level-triggered</td></tr>
 </table>
 
 A copy of the E820 System Memory Map is stored at memory address `0x0000000000006000`. Each E820 record is 32 bytes in length and the memory map is terminated by a blank record.

src/boot/mbr.asm

@@ -1,6 +1,6 @@
 ; =============================================================================
 ; Pure64 MBR -- a 64-bit OS/software loader written in Assembly for x86-64 systems
-; Copyright (C) 2008-2023 Return Infinity -- see LICENSE.TXT
+; Copyright (C) 2008-2024 Return Infinity -- see LICENSE.TXT
 ;
 ; This Master Boot Record will load Pure64 from a pre-defined location on the
 ; hard drive without making use of the file system.
@@ -225,7 +225,7 @@ times 510-$+$$ db 0
 
 sign dw 0xAA55
 
-VBEModeInfoBlock: equ 0x5C00
+VBEModeInfoBlock: equ 0x5F00
 ; VESA
 ; Mandatory information for all VBE revisions
 VBEModeInfoBlock.ModeAttributes		equ VBEModeInfoBlock + 0	; DW - mode attributes

src/boot/multiboot.asm

@@ -1,6 +1,6 @@
 ; =============================================================================
 ; Pure64 Multiboot -- a 64-bit OS/software loader written in Assembly for x86-64 systems
-; Copyright (C) 2008-2023 Return Infinity -- see LICENSE.TXT
+; Copyright (C) 2008-2024 Return Infinity -- see LICENSE.TXT
 ;
 ; http://stackoverflow.com/questions/33488194/creating-a-simple-multiboot-kernel-loaded-with-grub2
 ; https://www.gnu.org/software/grub/manual/multiboot/multiboot.html#OS-image-format

src/boot/multiboot2.asm

@@ -1,6 +1,6 @@
 ; =============================================================================
 ; Pure64 Multiboot 2 -- a 64-bit OS/software loader written in Assembly for x86-64 systems
-; Copyright (C) 2008-2023 Return Infinity -- see LICENSE.TXT
+; Copyright (C) 2008-2024 Return Infinity -- see LICENSE.TXT
 ;
 ; http://nongnu.askapache.com/grub/phcoder/multiboot.pdf
 ; =============================================================================

src/boot/pxestart.asm

@@ -1,6 +1,6 @@
 ; =============================================================================
 ; Pure64 PXE Start -- a 64-bit OS/software loader written in Assembly for x86-64 systems
-; Copyright (C) 2008-2023 Return Infinity -- see LICENSE.TXT
+; Copyright (C) 2008-2024 Return Infinity -- see LICENSE.TXT
 ;
 ; This is a stub file for loading Pure64 and a kernel/software package via PXE.
 ;
@@ -191,7 +191,7 @@ sign dw 0xAA55				; BIOS boot sector signature
 
 times 1024-$+$$ db 0			; Padding so that Pure64 will be aligned at 0x8000
 
-VBEModeInfoBlock: equ 0x5C00
+VBEModeInfoBlock: equ 0x5F00
 ; VESA
 ; Mandatory information for all VBE revisions
 VBEModeInfoBlock.ModeAttributes		equ VBEModeInfoBlock + 0	; DW - mode attributes

src/boot/uefi.asm

@@ -1,6 +1,6 @@
 ; =============================================================================
 ; UEFI loader for Pure64
-; Copyright (C) 2008-2023 Return Infinity -- see LICENSE.TXT
+; Copyright (C) 2008-2024 Return Infinity -- see LICENSE.TXT
 ;
 ; Adapted from https://stackoverflow.com/questions/72947069/how-to-write-hello-world-efi-application-in-nasm
 ; and https://github.com/charlesap/nasm-uefi/blob/master/shoe-x64.asm

src/init/acpi.asm

@@ -1,13 +1,13 @@
 ; =============================================================================
 ; Pure64 -- a 64-bit OS/software loader written in Assembly for x86-64 systems
-; Copyright (C) 2008-2023 Return Infinity -- see LICENSE.TXT
+; Copyright (C) 2008-2024 Return Infinity -- see LICENSE.TXT
 ;
 ; INIT ACPI
 ; =============================================================================
 
 
 init_acpi:
-	mov al, [BootMode]
+	mov al, [p_BootMode]
 	cmp al, 'U'
 	je foundACPIfromUEFI
 	mov esi, 0x000E0000		; Start looking for the Root System Description Pointer Structure
@@ -58,7 +58,7 @@ foundACPIv1:
 	cmp eax, 'RSDT'			; Make sure the signature is valid
 	jne novalidacpi			; Not the same? Bail out
 	sub rsi, 4
-	mov [os_ACPITableAddress], rsi	; Save the RSDT Table Address
+	mov [p_ACPITableAddress], rsi	; Save the RSDT Table Address
 	add rsi, 4
 	xor eax, eax
 	lodsd				; Length
@@ -84,7 +84,7 @@ foundACPIv2:
 	cmp eax, 'XSDT'			; Make sure the signature is valid
 	jne novalidacpi			; Not the same? Bail out
 	sub rsi, 4
-	mov [os_ACPITableAddress], rsi	; Save the XSDT Table Address
+	mov [p_ACPITableAddress], rsi	; Save the XSDT Table Address
 	add rsi, 4
 	xor eax, eax
 	lodsd				; Length
@@ -112,6 +112,9 @@ nextACPITable:
 	mov ebx, 'HPET'			; Signature for the HPET Description Table
 	cmp eax, ebx
 	je foundHPETTable
+;	mov ebx, 'MCFG'			; Signature for the PCIe Enhanced Configuration Mechanism
+;	cmp eax, ebx
+;	je foundMCFGTable
 	cmp ecx, edx
 	jne nextACPITable
 	jmp init_smp_acpi_done		;noACPIAPIC
@@ -124,6 +127,10 @@ foundHPETTable:
 	call parseHPETTable
 	jmp nextACPITable
 
+;foundMCFGTable:
+;	call parseMCFGTable
+;	jmp nextACPITable
+
 init_smp_acpi_done:
 	ret
 
@@ -148,10 +155,8 @@ parseAPICTable:
 	lodsd				; OEM Revision
 	lodsd				; Creator ID
 	lodsd				; Creator Revision
-	xor eax, eax
-	lodsd				; Local APIC Address
-	mov [os_LocalAPICAddress], rax	; Save the Address of the Local APIC
-	lodsd				; Flags
+	lodsd				; Local APIC Address (This should match what was pulled already via the MSR)
+	lodsd				; Flags (1 = Dual 8259 Legacy PICs Installed)
 	add ebx, 44
 	mov rdi, 0x0000000000005100	; Valid CPU IDs
 
@@ -171,14 +176,20 @@ readAPICstructures:
 ;	je APIClocalapicnmi
 ;	cmp al, 0x05			; Local APIC Address Override
 ;	je APICaddressoverride
-	cmp al, 0x09			; Processor Local x2APIC
-	je APICx2apic
+;	cmp al, 0x06			; I/O SAPIC Structure
+;	je APICiosapic
+;	cmp al, 0x07			; Local SAPIC Structure
+;	je APIClocalsapic
+;	cmp al, 0x08			; Platform Interrupt Source Structure
+;	je APICplatformint
+;	cmp al, 0x09			; Processor Local x2APIC
+;	je APICx2apic
 ;	cmp al, 0x0A			; Local x2APIC NMI
 ;	je APICx2nmi
 
 	jmp APICignore
 
-APICapic:
+APICapic:				; Entry Type 0
 	xor eax, eax
 	xor edx, edx
 	lodsb				; Length (will be set to 8)
@@ -189,60 +200,75 @@ APICapic:
 	lodsd				; Flags (Bit 0 set if enabled/usable)
 	bt eax, 0			; Test to see if usable
 	jnc readAPICstructures		; Read the next structure if CPU not usable
-	inc word [cpu_detected]
+	inc word [p_cpu_detected]
 	xchg eax, edx			; Restore the APIC ID back to EAX
 	stosb
 	jmp readAPICstructures		; Read the next structure
 
-APICioapic:
+APICioapic:				; Entry Type 1
 	xor eax, eax
 	lodsb				; Length (will be set to 12)
 	add ebx, eax
-	lodsb				; IO APIC ID
-	lodsb				; Reserved
-	xor eax, eax
-	lodsd				; IO APIC Address
 	push rdi
 	push rcx
-	mov rdi, os_IOAPICAddress
+	mov rdi, IM_IOAPICAddress	; Copy this data directly to the InfoMap
 	xor ecx, ecx
-	mov cl, [os_IOAPICCount]
-	shl cx, 3			; Quick multiply by 8
+	mov cl, [p_IOAPICCount]
+	shl cx, 4			; Quick multiply by 16
 	add rdi, rcx
 	pop rcx
-	stosd				; Store the IO APIC Address
-	lodsd				; System Vector Base
-	stosd				; Store the IO APIC Vector Base
+	xor eax, eax
+	lodsb				; IO APIC ID
+	stosd
+	lodsb				; Reserved
+	lodsd				; I/O APIC Address
+	stosd
+	lodsd				; Global System Interrupt Base
+	stosd
 	pop rdi
-	inc byte [os_IOAPICCount]
+	inc byte [p_IOAPICCount]
 	jmp readAPICstructures		; Read the next structure
 
-APICinterruptsourceoverride:
+APICinterruptsourceoverride:		; Entry Type 2
 	xor eax, eax
 	lodsb				; Length (will be set to 10)
 	add ebx, eax
-	lodsb				; Bus
-	lodsb				; Source
+	push rdi
+	push rcx
+	mov rdi, IM_IOAPICIntSource	; Copy this data directly to the InfoMap
+	xor ecx, ecx
+	mov cl, [p_IOAPICIntSourceC]
+	shl cx, 3			; Quick multiply by 8
+	add rdi, rcx
+	lodsb				; Bus Source
+	stosb
+	lodsb				; IRQ Source
+	stosb
 	lodsd				; Global System Interrupt
-	lodsw				; Flags
+	stosd
+	lodsw				; Flags - bit 1 Low(1)/High(0), Bit 3 Level(1)/Edge(0)
+	stosw
+	pop rcx
+	pop rdi
+	inc byte [p_IOAPICIntSourceC]
 	jmp readAPICstructures		; Read the next structure
 
-APICx2apic:
-	xor eax, eax
-	xor edx, edx
-	lodsb				; Length (will be set to 16)
-	add ebx, eax
-	lodsw				; Reserved; Must be Zero
-	lodsd
-	xchg eax, edx			; Save the x2APIC ID to EDX
-	lodsd				; Flags (Bit 0 set if enabled/usable)
-	bt eax, 0			; Test to see if usable
-	jnc APICx2apicEnd		; Read the next structure if CPU not usable
-	xchg eax, edx			; Restore the x2APIC ID back to EAX
-	; TODO - Save the ID's somewhere
-APICx2apicEnd:
-	lodsd				; ACPI Processor UID
-	jmp readAPICstructures		; Read the next structure
+;APICx2apic:				; Entry Type 9
+;	xor eax, eax
+;	xor edx, edx
+;	lodsb				; Length (will be set to 16)
+;	add ebx, eax
+;	lodsw				; Reserved; Must be Zero
+;	lodsd
+;	xchg eax, edx			; Save the x2APIC ID to EDX
+;	lodsd				; Flags (Bit 0 set if enabled/usable)
+;	bt eax, 0			; Test to see if usable
+;	jnc APICx2apicEnd		; Read the next structure if CPU not usable
+;	xchg eax, edx			; Restore the x2APIC ID back to EAX
+;	; TODO - Save the ID's somewhere
+;APICx2apicEnd:
+;	lodsd				; ACPI Processor UID
+;	jmp readAPICstructures		; Read the next structure
 
 APICignore:
 	xor eax, eax
@@ -273,13 +299,37 @@ parseHPETTable:
 	lodsd				; Event Timer Block ID
 	lodsd				; Base Address Settings
 	lodsq				; Base Address Value
-	mov [os_HPETAddress], rax	; Save the Address of the HPET
+	mov [p_HPETAddress], rax	; Save the Address of the HPET
 	lodsb				; HPET Number
 	lodsw				; Main Counter Minimum
 	lodsw				; Page Protection And OEM Attribute
 	ret
 ; -----------------------------------------------------------------------------
 
 
+; -----------------------------------------------------------------------------
+;parseMCFGTable:
+;	lodsd				; Length of MCFG in bytes
+;	lodsb				; Revision
+;	lodsb				; Checksum
+;	lodsd				; OEMID (First 4 bytes)
+;	lodsw				; OEMID (Last 2 bytes)
+;	lodsq				; OEM Table ID
+;	lodsd				; OEM Revision
+;	lodsd				; Creator ID
+;	lodsd				; Creator Revision
+;	lodsq				; Reserved
+;
+;	; Loop through each entry
+;	lodsq				; Base address of enhanced configuration mechanism
+;	lodsw				; PCI Segment Group Number
+;	lodsb				; Start PCI bus number decoded by this host bridge
+;	lodsb				; End PCI bus number decoded by this host bridge
+;	lodsd				; Reserved
+;
+;	ret
+; -----------------------------------------------------------------------------
+
+
 ; =============================================================================
 ; EOF