Add support for PCI Express

docs/README.md

@@ -186,13 +186,26 @@ The Pure64 information table is located at `0x0000000000005000` and ends at `0x0
 <tr><td>0x5084</td><td>16-bit</td><td>VIDEO_X</td><td>X resolution</td></tr>
 <tr><td>0x5086</td><td>16-bit</td><td>VIDEO_Y</td><td>Y resolution</td></tr>
 <tr><td>0x5088</td><td>8-bit</td><td>VIDEO_DEPTH</td><td>Color depth</td></tr>
-<tr><td>0x5089 - 0x50FF</td><td>&nbsp;</td><td>&nbsp;</td><td>For future use</td></tr>
+<tr><td>0x5089 - 0x508F</td><td>&nbsp;</td><td>&nbsp;</td><td>For future use</td></tr>
+<tr><td>0x5090 - 0x5091</td><td>16-bit</td><td>PCIE_COUNT</td><td>Number of PCIe buses</td></tr>
+<tr><td>0x5092 - 0x50FF</td><td>&nbsp;</td><td>&nbsp;</td><td>For future use</td></tr>
 <tr><td>0x5100 - 0x51FF</td><td>8-bit</td><td>APIC_ID</td><td>APIC ID's for valid CPU cores (based on CORES_ACTIVE)</td></tr>
-<tr><td>0x5200 - 0x56FF</td><td>&nbsp;</td><td>&nbsp;</td><td>For future use</td></tr>
+<tr><td>0x5200 - 0x53FF</td><td>&nbsp;</td><td>&nbsp;</td><td>For future use</td></tr>
+<tr><td>0x5400 - 0x55FF</td><td>16 byte entries</td><td>PCIE</td><td>PCIe bus data</td></tr>
 <tr><td>0x5600 - 0x56FF</td><td>16 byte entries</td><td>IOAPIC</td><td>I/O APIC addresses (based on IOAPIC_COUNT)</td></tr>
 <tr><td>0x5700 - 0x57FF</td><td>8 byte entries</td><td>IOAPIC_INTSOURCE</td><td>I/O APIC Interrupt Source Override Entries (based on IOAPIC_INTSOURCE_COUNT)</td></tr>
 </table>
 
+PCIE list format:
+<table border="1" cellpadding="2" cellspacing="0">
+<tr><th>Offset</th><th>Variable Size</th><th>Name</th><th>Description</th></tr>
+<tr><td>0x00</td><td>64-bit</td><td>Base</td><td>The base address of enhanced configuration mechanism</td></tr>
+<tr><td>0x08</td><td>16-bit</td><td>Group</td><td>The PCI segment group number</td></tr>
+<tr><td>0x0A</td><td>8-bit</td><td>Start Bus</td><td>Start PCI bus number decoded by this host bridge</td></tr>
+<tr><td>0x0B</td><td>8-bit</td><td>End Bus</td><td>End PCI bus number decoded by this host bridge</td></tr>
+<tr><td>0x0C</td><td>32-bit</td><td>Reserved</td><td>This value should be 0</td></tr>
+</table>
+
 IOAPIC list format:
 <table border="1" cellpadding="2" cellspacing="0">
 <tr><th>Offset</th><th>Variable Size</th><th>Name</th><th>Description</th></tr>

src/init/acpi.asm

@@ -112,9 +112,9 @@ nextACPITable:
 	mov ebx, 'HPET'			; Signature for the HPET Description Table
 	cmp eax, ebx
 	je foundHPETTable
-;	mov ebx, 'MCFG'			; Signature for the PCIe Enhanced Configuration Mechanism
-;	cmp eax, ebx
-;	je foundMCFGTable
+	mov ebx, 'MCFG'			; Signature for the PCIe Enhanced Configuration Mechanism
+	cmp eax, ebx
+	je foundMCFGTable
 	cmp ecx, edx
 	jne nextACPITable
 	jmp init_smp_acpi_done		;noACPIAPIC
@@ -127,9 +127,9 @@ foundHPETTable:
 	call parseHPETTable
 	jmp nextACPITable
 
-;foundMCFGTable:
-;	call parseMCFGTable
-;	jmp nextACPITable
+foundMCFGTable:
+	call parseMCFGTable
+	jmp nextACPITable
 
 init_smp_acpi_done:
 	ret
@@ -308,26 +308,48 @@ parseHPETTable:
 
 
 ; -----------------------------------------------------------------------------
-;parseMCFGTable:
-;	lodsd				; Length of MCFG in bytes
-;	lodsb				; Revision
-;	lodsb				; Checksum
-;	lodsd				; OEMID (First 4 bytes)
-;	lodsw				; OEMID (Last 2 bytes)
-;	lodsq				; OEM Table ID
-;	lodsd				; OEM Revision
-;	lodsd				; Creator ID
-;	lodsd				; Creator Revision
-;	lodsq				; Reserved
-;
-;	; Loop through each entry
-;	lodsq				; Base address of enhanced configuration mechanism
-;	lodsw				; PCI Segment Group Number
-;	lodsb				; Start PCI bus number decoded by this host bridge
-;	lodsb				; End PCI bus number decoded by this host bridge
-;	lodsd				; Reserved
-;
-;	ret
+parseMCFGTable:
+	push rdi
+	push rcx
+	xor eax, eax
+	xor ecx, ecx
+	mov cx, [p_PCIECount]
+	shl ecx, 4
+	mov rdi, IM_PCIE
+	add rdi, rcx
+	lodsd				; Length of MCFG in bytes
+	sub eax, 44			; Subtract the size of the table header
+	shr eax, 4			; Quick divide by 16
+	mov ecx, eax			; ECX now stores the number of 16-byte records
+	add word [p_PCIECount], cx
+	lodsb				; Revision
+	lodsb				; Checksum
+	lodsd				; OEMID (First 4 bytes)
+	lodsw				; OEMID (Last 2 bytes)
+	lodsq				; OEM Table ID
+	lodsd				; OEM Revision
+	lodsd				; Creator ID
+	lodsd				; Creator Revision
+	lodsq				; Reserved
+
+	; Loop through each entry
+parseMCFGTable_next:
+	lodsq				; Base address of enhanced configuration mechanism
+	stosq
+	lodsw				; PCI Segment Group Number
+	stosw
+	lodsb				; Start PCI bus number decoded by this host bridge
+	stosb
+	lodsb				; End PCI bus number decoded by this host bridge
+	stosb
+	lodsd				; Reserved
+	stosd
+	sub ecx, 1
+	jnz parseMCFGTable_next
+
+	pop rcx
+	pop rdi
+	ret
 ; -----------------------------------------------------------------------------
 
 

src/pure64.asm

@@ -528,6 +528,10 @@ clearmapnext:
 	mov al, [VBEModeInfoBlock.BitsPerPixel]		; Color depth
 	stosb
 
+	mov di, 0x5090
+	mov ax, [p_PCIECount]
+	stosw
+
 ; Move the trailing binary to its final location
 	mov esi, 0x8000+PURE64SIZE	; Memory offset to end of pure64.sys
 	mov edi, 0x100000		; Destination address at the 1MiB mark

src/sysvar.asm

@@ -14,6 +14,7 @@ cfg_smpinit:		db 1		; By default SMP is enabled. Set to 0 to disable.
 ; Memory locations
 E820Map:		equ 0x0000000000004000
 InfoMap:		equ 0x0000000000005000
+IM_PCIE:		equ 0x0000000000005400		; 16 bytes per entry
 IM_IOAPICAddress:	equ 0x0000000000005600		; 16 bytes per entry
 IM_IOAPICIntSource:	equ 0x0000000000005700		; 8 bytes per entry
 SystemVariables:	equ 0x0000000000005800
@@ -34,6 +35,7 @@ p_mem_amount:		equ SystemVariables + 0x84	; in MiB
 p_cpu_speed:		equ SystemVariables + 0x100
 p_cpu_activated:	equ SystemVariables + 0x102
 p_cpu_detected:		equ SystemVariables + 0x104
+p_PCIECount:		equ SystemVariables + 0x106
 
 ; DB - Starting at offset 0x180, increments by 1
 p_IOAPICCount:		equ SystemVariables + 0x180