Skip to content
This repository was archived by the owner on Jun 7, 2023. It is now read-only.

Add: Copy over a Verilog test bench if present. #117

Merged
bnmnetp merged 1 commit into from
Dec 6, 2022
Merged

Add: Copy over a Verilog test bench if present. #117

bnmnetp merged 1 commit into from
Dec 6, 2022

Conversation

@bjones1
Copy link
Collaborator

@bjones1 bjones1 commented Dec 6, 2022

No description provided.

@bjones1 bjones1 marked this pull request as ready for review December 6, 2022 03:55
@bjones1 bjones1 requested a review from bnmnetp December 6, 2022 03:55
@bjones1
Copy link
Collaborator Author

bjones1 commented Dec 6, 2022

Thanks! Would you merge this? Since test fail, I don't have permission to merge.

@bnmnetp bnmnetp merged commit 9ac899a into RunestoneInteractive:main Dec 6, 2022
@bjones1 bjones1 deleted the verilog-test-vectors branch December 6, 2022 18:33
Sign up for free to subscribe to this conversation on GitHub. Already have an account? Sign in.

Reviewers

1 more reviewer

@bnmnetp bnmnetp bnmnetp approved these changes

Reviewers whose approvals may not affect merge requirements

Assignees

No one assigned

Labels

None yet

Projects

None yet

Milestone

No milestone

Development

Successfully merging this pull request may close these issues.

2 participants

@bjones1 @bnmnetp