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Devin Review found 2 potential issues.
🐛 2 issues in files not directly in the diff
🐛 ICMP always writes result to R0 instead of destination register (rs1) (src/flux/vm/interpreter.py:551)
The ICMP handler hardcodes rd = 0 at line 551, but all the updated tests expect the comparison result to be written to the register specified by rs1 (the second operand byte). For example, test_icmp_writes_to_dest_register_not_r0 encodes [ICMP, 0, 3, 1] and expects R3=1 and R0=99 (unchanged), but the interpreter writes to R0, producing R0=1 and R3=5 (unchanged). Similarly, test_icmp_eq encodes [ICMP, 0, 1, 2] and asserts vm.regs.read_gp(1) == 1, but the interpreter writes to R0 so R1 remains at its MOVI-loaded value of 5. Every new ICMP test (tests/test_vm_complete.py:114-239) will fail because of this mismatch.
🐛 New opcodes missing from FORMAT_D/FORMAT_E sets cause incorrect instruction_size() (src/flux/bytecode/opcodes.py:143-152)
The seven new opcodes (EVOLVE=0x7C, INSTINCT=0x7D, WITNESS=0x7E, SNAPSHOT=0x7F, CONF=0x3D, RESTORE=0x3F, MERGE=0x3E) are not added to the FORMAT_D or FORMAT_E frozensets in opcodes.py. They all default to FORMAT_C (3 bytes), but the interpreter decodes them as 4-byte instructions via _decode_operands_D() or _decode_operands_E(). This means get_format() and instruction_size() return wrong values (format='C', size=3 instead of 'D'/4 or 'E'/4). These functions are used by the bytecode decoder (src/flux/bytecode/decoder.py:321), disassembler (src/flux/disasm.py:246), validator (src/flux/bytecode/validator.py:149), and debugger — all of which will misalign instruction boundaries when encountering any of these opcodes, corrupting all subsequent instruction decoding in the stream.
View 5 additional findings in Devin Review.
T-009: Add GitHub Actions build badges
Adds CI/build status badges to README.md for fleet visibility.
Badges added:
benchmark.ymlworkflow badgeci.ymlworkflow badgerelease.ymlworkflow badge🤖 Auto-generated by Super Z (FLUX Fleet Greenhorn)