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Model accuracy improvements #337

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Merged
jj16791 merged 9 commits into from
Oct 13, 2023
Merged

Model accuracy improvements #337

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37a3e2b
Updated a64fx_sme config.
FinnWilkinson Jul 28, 2023
7882953
Reversed LSQ restrictions to apply requests per cycle to targets not …
Jul 19, 2023
84ca576
Fixed some latency values in a64fx config file
Jul 31, 2023
c39f3b8
Reverted accidental changes
Jul 31, 2023
815b8f6
Copy of updated a64fx latency values into sme counterpart
jj16791 Aug 14, 2023
e584cd6
Changes to relfect PR comments
jj16791 Oct 9, 2023
35155bd
Typo fix
jj16791 Oct 9, 2023
868f963
Changes to a64fx config files to match requests from PR
jj16791 Oct 11, 2023
9dce6e9
comment fix
jj16791 Oct 11, 2023
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125 changes: 122 additions & 3 deletions configs/a64fx.yaml
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Original file line number Diff line number Diff line change
Expand Up @@ -113,17 +113,17 @@ Reservation-Stations:
- EXB
2:
Size: 10
Dispatch-Rate: 2
Dispatch-Rate: 1
Ports:
- EAGA
3:
Size: 10
Dispatch-Rate: 2
Dispatch-Rate: 1
Ports:
- EAGB
4:
Size: 19
Dispatch-Rate: 2
Dispatch-Rate: 1
Ports:
- BR
Execution-Units:
Expand Down Expand Up @@ -245,6 +245,125 @@ Latencies:
- STORE_ADDRESS_SVE
Execution-Latency: 6
Execution-Throughput: 1
# Indexed FMLA instructions split into 2 dependent µops. Latency increased to 15 to mimic such behaviour
# NOTE: Any changes to the capstone opcode list could invalidate the mapping between ARM instructions and the values below
11:
Instruction-Groups:
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FinnWilkinson marked this conversation as resolved.
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Execution-Latency: 15
Execution-Throughput: 1
# CPU-Info mainly used to generate a replica of the special (or system) file directory
# structure
CPU-Info:
Expand Down
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