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Speculated assertions#414

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dANW34V3R merged 64 commits intodevfrom
speculatedAssertions
Jul 9, 2024
Merged

Speculated assertions#414
dANW34V3R merged 64 commits intodevfrom
speculatedAssertions

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@dANW34V3R dANW34V3R commented May 24, 2024

This PR updates logic used to decode compressed instructions. Previously, assertions were used to check for invalid usages of instructions but unfortunately these could be falsely triggered by speculated instructions which did not retire. Logic has been updated to cause an exception if one of these instructions reaches the commit stage. RISC-V instruction objects now carry a small string to provide extra information when the exception is printed.

Instructions with parameters that encode HINTS are now allowed to pass freely through the pipeline as they will cause no architectural state change. Quote from the spec: "HINTs are encoded as integer computational instructions with rd=x0. Hence, like the NOP instruction, HINTs do not change any architecturally visible state, except for advancing the pc and any applicable performance counters. Implementations are always allowed to ignore the encoded hints. ... [They] are usually used to communicate performance hints to the microarchitecture"

@dANW34V3R dANW34V3R requested review from ABenC377, FinnWilkinson, JosephMoore25 and jj16791 and removed request for jj16791 May 24, 2024 16:30
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ABenC377 previously approved these changes Jun 5, 2024
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@FinnWilkinson FinnWilkinson left a comment

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I really like this concept of being able to add extra information to an instruction when an exception occurs. Could you also add this to the aarch64 instruction class and ExceptionHandler?

Comment thread src/lib/arch/riscv/InstructionMetadata.cc
Comment thread src/include/simeng/arch/riscv/Instruction.hh Outdated
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#rerun tests

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Holding off on approval until #414 (comment) has been resolved

Comment thread src/lib/arch/aarch64/ExceptionHandler.cc Outdated
Comment thread src/lib/arch/riscv/ExceptionHandler.cc Outdated
@dANW34V3R dANW34V3R merged commit 5e58710 into dev Jul 9, 2024
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5 participants