feat: Add support for FPGAs connected via the vfio-platform driver#783
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IgnoreWarnings wants to merge 7 commits into
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feat: Add support for FPGAs connected via the vfio-platform driver#783IgnoreWarnings wants to merge 7 commits into
IgnoreWarnings wants to merge 7 commits into
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stv0g
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May 22, 2024
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This is a first round of review. I will need to go a bit deeper into the actual logic.
Some general things:
- Please reformat all your changes with clang-format
- Make sure your comments have a DCO sign-off (the CI check is failing)
- Please try to consolitate/stash your commits in a way it makes the code easier to review. E.g. not everything into one commit, but smaller groups of changes which are logically belong together.
stv0g
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This is just a draft to track the progress. It's clear that it needs squashing, signing-off and formatting. It may also make sense to split it into multiple PRs. |
n-eiling
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Oh okay, sorry I did not see that this PR was a draft. |
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I accidentally opened a PR at first and then changed to draft. Since this is work in progress, many of the changes requested are already outdated/fixed. |
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n-eiling
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| // Save ID in card so we can create mappings later when needed (e.g. when | ||
| // allocating DMA memory in host RAM) | ||
| card->addrSpaceIdDeviceToHost = | ||
| mm.getOrCreateAddressSpace("zynq_ultra_ps_e_0/HPC0_DDR_LOW"); |
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does this need to be hardcoded?
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Signed-off-by: Pascal Bauer <pascal.bauer@rwth-aachen.de>
Signed-off-by: Pascal Bauer <pascal.bauer@rwth-aachen.de>
Signed-off-by: Pascal Bauer <pascal.bauer@rwth-aachen.de>
Signed-off-by: Pascal Bauer <pascal.bauer@rwth-aachen.de>
Signed-off-by: Pascal Bauer <pascal.bauer@rwth-aachen.de>
Signed-off-by: Pascal Bauer <pascal.bauer@rwth-aachen.de>
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Merged through individual PRs |
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DO NOT MERGE!
This is a draft only to discuss and track progress. Changes will come in smaller PRs.
Integration of platform based fpgas.
Current Status:
Working:
✅ VFIO Driver binding
✅ VFIO Writing to registers / configuring devices
✅ VFIO interrupts
✅ Hardware loopback verified working
Not working:
❌ Some memorygraph mappings from host RAM (dma required) are incorrect / hardcoded. Zynq only has one master addrSpace, but needs mapping to all ram areas.