HLS bug:
#pragma HLS INTERFACE axis port=in_data.int1 name=i_int1
The name gets ignored here, the resulting RTL ports are still called in_data_int1_V_TDATA and not i_int1_TDATA.
This is also broken for ap_fifo. The documentation does not mention anything about unsupported combinations: https://japan.xilinx.com/html_docs/xilinx2017_4/sdaccel_doc/jit1504034365862.html