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  1. ddr_proj ddr_proj Public

    DDR Controller for Cyclone II

    VHDL

  2. cisco-hwic-3g-cdma cisco-hwic-3g-cdma Public

    Forked from tomverbeure/cisco-hwic-3g-cdma

    Reverse Engineering of the Cisco HWIC-3G-CDMA PCB

    Verilog

  3. jtag_uart_example jtag_uart_example Public

    Forked from tomverbeure/jtag_uart_example

    Mini CPU design with JTAG UART support

    Verilog