Merge rv32im and rv64gc into one

[xiaoxiang781216]

32bit and 64bit riscv share the same specification, it doesn't make sense to support two most identical arch by two code base.

[btashton]

We should be aware that some cores do have some ISA extensions (like GAP8) I'm not sure how much that will matter.
The rv32e has different a register count and some other limitations, but I don't know of any publicly available chips using this yet.
https://github.com/lowRISC/ibex has a "micro" mode that use rv32e so that could probably used for a test on an FPGA.

[xiaoxiang781216]

Yes, but these variants are minor and can be controlled by Kconfig. Since the spec is controlled by a mature committee who are considering the compatibility seriously, it expect that the potential conflict between 32bit and 64bit should be very small. On the other hand, it's better to support the experimental/predated implementation by the duplicated arch code.

[btashton]

@xiaoxiang781216 I am fine with this change. nr5m100 RTL was never released publicly and Ken never responded. While the GAP8 is real, I think is also unused and we already heard back from the contributor that they were fine, it an early PULP design, that I think they are replacing with a new chip.

[xiaoxiang781216]

@btashton Ok, I will found time to merge 32bit and 64bit into one.