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Summary

PR included
#13717
#13651
#13662
#13623
#13737

Impact

RELEASE

Testing

CI

hujun260 and others added 5 commits October 10, 2024 12:51
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Espressif HAL for 3rd Party Platforms: b4c723a119344b4b71d69819019d55637fb570fd
common/xtensa_cpupause.c: In function 'xtensa_pause_handler':
common/xtensa_cpupause.c:240:3: warning: implicit declaration of function 'xtensa_savestate'; did you mean 'xtensa_setps'? [-Wimplicit-function-declaration]
  240 |   xtensa_savestate(tcb->xcp.regs);
      |   ^~~~~~~~~~~~~~~~
      |   xtensa_setps
common/xtensa_cpupause.c:243:3: warning: implicit declaration of function 'xtensa_restorestate'; did you mean 'xtensa_context_restore'? [-Wimplicit-function-declaration]
  243 |   xtensa_restorestate(tcb->xcp.regs);
      |   ^~~~~~~~~~~~~~~~~~~
      |   xtensa_context_restore

Signed-off-by: hujun5 <hujun5@xiaomi.com>
for the citimon stats:

thread 0:                     thread 1:
enter_critical (t0)
up_switch_context
note suspend thread0 (t1)

                              thread running
                              IRQ happen, in ISR:
                                post thread0
                                up_switch_context
                                note resume thread0 (t2)
                                ISR continue f1
                                ISR continue f2
                                ...
                                ISR continue fn

leave_critical (t3)

You will see, the thread 0, critical_section time is:
(t1 - t0) + (t3 - t2)

BUT, this result contains f1 f2 .. fn time spent, it is wrong
to tell user thead0 hold the critical lots of time but actually
not belong to it.

Resolve:
change the nxsched_suspend/resume_scheduler to real hanppends

Signed-off-by: ligd <liguiding1@xiaomi.com>
this is caused by:
35c8c80

Signed-off-by: ligd <liguiding1@xiaomi.com>
…th other functionalities removed.

reason:
by doing this we can reduce context switch time,
When we exit from an interrupt handler, we directly use tcb->xcp.regs

before
text    data     bss     dec     hex filename
178368     876  130604  309848   4ba58 nuttx
after
text    data     bss     dec     hex filename
178120     876  130212  309208   4b7d8 nuttx

szie change -248

Signed-off-by: hujun5 <hujun5@xiaomi.com>
CXX:  libcxxmini/libxx_new.cxx "/home/guoshichao/work_profile/vela_os/vela_qemu_1/nuttx/include/arch/armv7-m/irq.h", line 594: error apache#3422:
          use of the "register" storage class specifier is not allowed
    register uint32_t sp;
    ^

"/home/guoshichao/work_profile/vela_os/vela_qemu_1/nuttx/include/arch/armv7-m/irq.h", line 594: error apache#3422:
          use of the "register" storage class specifier is not allowed
    register uint32_t sp;
    ^

"/home/guoshichao/work_profile/vela_os/vela_qemu_1/nuttx/include/arch/armv7-m/irq.h", line 594: error apache#3422:
          use of the "register" storage class specifier is not allowed
    register uint32_t sp;
    ^

make[1]: *** [Makefile:69: libxx_delete_sized.o] Error 1
make[1]: *** Waiting for unfinished jobs....
make[1]: *** [Makefile:69: libxx_deletea_sized.o] Error 1
make[1]: *** [Makefile:69: libxx_new.o] Error 1
"/home/guoshichao/work_profile/vela_os/vela_qemu_1/nuttx/include/arch/armv7-m/irq.h", line 594: error apache#3422:
          use of the "register" storage class specifier is not allowed
    register uint32_t sp;
    ^

"/home/guoshichao/work_profile/vela_os/vela_qemu_1/nuttx/include/arch/armv7-m/irq.h", line 594: error apache#3422:
          use of the "register" storage class specifier is not allowed
    register uint32_t sp;
    ^

Signed-off-by: guoshichao <guoshichao@xiaomi.com>
@github-actions github-actions bot added Arch: arm Issues related to ARM (32-bit) architecture Arch: arm64 Issues related to ARM64 (64-bit) architecture Arch: ceva Issues related to CEVA architecture Arch: risc-v Issues related to the RISC-V (32-bit or 64-bit) architecture Arch: x86 Issues related to the x86 architecture Arch: x86_64 Issues related to the x86_64 architecture Arch: xtensa Issues related to the Xtensa architecture Size: L The size of the change in this PR is large labels Oct 10, 2024
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nuttxpr commented Oct 10, 2024

[Experimental Bot, please feedback here]

It's impossible to determine if the PRs meet the NuttX requirements without their content. Providing just the PR URLs isn't enough.

To assess if these PRs meet the requirements, I need to see the actual changes and descriptions within each PR.

Here's why:

  • Summary: The PR titles alone don't provide enough context about the changes, their necessity, and how they work.
  • Impact: Without knowing the specifics of the changes, it's impossible to assess their impact on users, build processes, hardware, documentation, security, or compatibility.
  • Testing: "CI" simply means Continuous Integration, implying automated tests ran. However, the requirements ask for specifics about the testing environment (host and target details) and the actual test logs before and after the changes. This information is crucial to verify the PRs' functionality.

To get a proper evaluation, please provide the following for each PR:

  • PR Content: Share the actual code changes, either by linking to specific commits or providing diffs.
  • PR Description: Copy-paste the full description from each PR, including any explanations, justification for the changes, and testing details provided by the author.

With this information, I can help you determine if the PRs meet the NuttX requirements.

@raiden00pl raiden00pl merged commit bb8eb93 into apache:releases/12.7 Oct 10, 2024
@jerpelea jerpelea deleted the sched branch October 10, 2024 13:37
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Arch: arm Issues related to ARM (32-bit) architecture Arch: arm64 Issues related to ARM64 (64-bit) architecture Arch: ceva Issues related to CEVA architecture Arch: risc-v Issues related to the RISC-V (32-bit or 64-bit) architecture Arch: x86 Issues related to the x86 architecture Arch: x86_64 Issues related to the x86_64 architecture Arch: xtensa Issues related to the Xtensa architecture Size: L The size of the change in this PR is large

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7 participants