riscv/mpfs: Add boilerplate code for SMP #14397
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Otherwise querying for hartid doesn't work.
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Arch: risc-v
MPFS implements external interrupt control on a per-hart basis i.e. there are PLIC control registers for each hart separately. This means we need a procedure to initialize such registers for each hart individually, instead of only for the boot hart like it is now. Fix this by implementing mpfs_plic_init_hart which can be called by each hart as needed. Note: it is not a good idea to initialize all harts from the boot hart, as the boot hart may not know which harts are used by NuttX in AMP configuration. It is better that the hart initializes itself. Note: The hartid must be provided as explicit parameter, as it cannot be queried via riscv_mhartid() yet; the per-cpu structure is initialized later on which means riscv_mhartid() would return 0 for all harts except the boot hart.
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[Experimental Bot, please feedback here] Fill In The Commit Message: This PR contains a Commit with an Empty Commit Message. Please fill in the Commit Message with the PR Summary. Yes, the PR appears to meet the NuttX requirements. Here's why:
Suggestions for Improvement (to make it even stronger):
By adding these minor enhancements, the PR would be even stronger and easier for reviewers to assess. |
xiaoxiang781216
approved these changes
Oct 18, 2024
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Summary
Add boilerplate code for enabling SMP mode for MPFS target.
Impact
Add SMP build support for MPFS target. No other target is affected.
Testing
Build passes
Simple MPFS SMP target boots to nsh console