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arch/xtensa: use arch atomic when enable iram heap #14805
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[Experimental Bot, please feedback here] This PR appears to mostly meet the NuttX requirements, but is missing some key information. Missing/Needs Improvement:
Example of Improved Impact Section: By providing more complete information in these sections, the PR will be much easier to review and merge. |
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Hi @zyfeier , I'll test on our internal CI, thanks! |
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Hi @zyfeier , I still couldn't make it work for NuttX: 74610b0 (this PR's commit) Built/flashed with: Compiler's version: Anything Am I missing here? |
@tmedicci From the disassembly file, it can be seen that the s32c1i instruction is still used,could you to check if -D__STDC_NO_ATOMICS__ was include in compile flag? |
Hi @zyfeier ! Thanks fo your quick response! In fact, I had to set |
@tmedicci I found that when compiling esp32/common, scripts/Make.defs is included twice, which causes the flags in ARCHCFLAGS to be doubled. |
That's perfect! I was able to make it work (and, in fact, it fixes |
@tmedicci wamr_wasi_debug build issue will fixed in PR #14827, and also i move the Make.def modify to PR #14855 |
tmedicci
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Approved. Thanks, @zyfeier !
S32C1I instructions may target cached, cache-bypass, and data RAM memory locations. S32C1I instructions are not permitted to access memory addresses in data ROM, instruction memory or the address region allocated to the XLMI port. Attempts to direct the S32C1I at these addresses will cause an exception. Signed-off-by: zhangyuan29 <zhangyuan29@xiaomi.com>
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let's ignore the ci error which is fixed by #15047 |

Summary
This PR fixed EPS32 issue after enable #14465
Use arch atomic when enable iram heap.
S32C1I instructions may target cached, cache-bypass, and data RAM memory locations. S32C1I instructions are not permitted to access memory addresses in data ROM, instruction memory or the address region allocated to the XLMI port. Attempts to direct the S32C1I at these addresses will cause an exception.
Impact
ESP32 iram heap
Testing
esp32-devkit:sotest boot success