Skip to content

Conversation

@jlaitine
Copy link
Contributor

@jlaitine jlaitine commented Nov 19, 2025

Summary

This PR adds a function imx9_lpspi_select_cs to assert CS at the start of an SPI transfer and keep it asserted until called again to de-assert it. This can be called by board-provided imx9_lpspi_select, in case the CS needs to be controlled via the LPSPI block and not GPIO.

The TCR register CONT (continue) bit is asserted to prevent CS toggling during the transfer, and the PCS bits are set to mark the correct CS

In addition this corrects some TCR register PCS bit definitions which are not valid for IMX9 device. I expect that this is a copy-paste error from some other i.MX platform.

Impact

Impacts only imx9 designs using LPSPI. Doesn't impact existing designs, adds a new feature, enabling to use the internal CS signal of the SPI block.

Testing

Tested on a custom IMX9 board, with icm42605 IMU sensor connected to LPSPI. Previously, had the CS signal muxed to GPIO1_IO11 (IOMUXC_PAD_SAI1_TXFS_GPIO1_IO11), and moved that to internal PCS signal (IOMUXC_PAD_SAI1_TXFS_LPSPI1_PCS0).

Tested in PX4 environment, showing that the sensor in question works:

> listener sensor_gyro -i 2

TOPIC: sensor_gyro instance 2 #1
 sensor_gyro
    timestamp: 13508265 (0.001096 seconds ago)
    timestamp_sample: 13508135 (130 us before timestamp)
    device_id: 2686986 (Type: 0x29, SPI:1 (0x00))
    x: -0.00207
    y: 0.00133
    z: -0.00756
    temperature: 50.4
    error_count: 0
    clip_counter: [0, 0, 0]
    samples: 10

According to the TRM, only bits 24-25 are reserved for chip select, and
the maximum number of internal chip selects is 3 (on LPSPI4 bus only).

Fix the TCR_PCS_MASK and remove extra definitions.

Signed-off-by: Jukka Laitinen <jukka.laitinen@tii.ae>
Add a function imx9_lpspi_select_cs to assert CS at the start of
an SPI transfer and keep it asserted until called again to
de-assert it. This can be called by board-provided imx9_lpspi_select,
in case the CS needs to be controlled via the LPSPI block and not
GPIO.

The TCR register CONT (continue) bit is asserted to prevent CS toggling
during the transfer, and the PCS bits are set to mark the correct CS

Signed-off-by: Jukka Laitinen <jukka.laitinen@tii.ae>
@github-actions github-actions bot added Arch: arm64 Issues related to ARM64 (64-bit) architecture Size: S The size of the change in this PR is small labels Nov 19, 2025
@acassis acassis merged commit f641298 into apache:master Nov 19, 2025
13 checks passed
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment

Labels

Arch: arm64 Issues related to ARM64 (64-bit) architecture Size: S The size of the change in this PR is small

Projects

None yet

Development

Successfully merging this pull request may close these issues.

4 participants