FlexCAN driver for i.MX RT1060 MCU

arch/arm/src/imxrt/Kconfig

@@ -155,6 +155,11 @@ config IMXRT_HAVE_LPUART
 	bool
 	default n
 
+config IMXRT_FLEXCAN
+	bool
+	default n
+	select ARCH_HAVE_NETDEV_STATISTICS
+
 config IMXRT_LPI2C
 	bool
 	default n
@@ -411,6 +416,94 @@ config IMXRT_LPUART_INVERT
 
 endmenu # LPUART Configuration
 
+menu "FLEXCAN Peripherals"
+
+config IMXRT_FLEXCAN1
+	bool "FLEXCAN1"
+	default n
+	select IMXRT_FLEXCAN
+	select NET_CAN_HAVE_TX_DEADLINE
+
+config IMXRT_FLEXCAN2
+	bool "FLEXCAN2"
+	default n
+	select IMXRT_FLEXCAN
+	select NET_CAN_HAVE_TX_DEADLINE
+
+config IMXRT_FLEXCAN3
+	bool "FLEXCAN3"
+	default n
+	select IMXRT_FLEXCAN
+	select NET_CAN_HAVE_TX_DEADLINE
+	select NET_CAN_HAVE_CANFD
+
+endmenu # FLEXCAN Peripherals
+
+menu "FLEXCAN1 Configuration"
+	depends on IMXRT_FLEXCAN1
+
+config FLEXCAN1_BITRATE
+	int "CAN bitrate"
+	depends on !NET_CAN_CANFD
+	default 1000000
+
+config FLEXCAN1_SAMPLEP
+	int "CAN sample point"
+	depends on !NET_CAN_CANFD
+	default 80
+
+endmenu # IMXRT_FLEXCAN1
+
+menu "FLEXCAN2 Configuration"
+	depends on IMXRT_FLEXCAN2
+
+config FLEXCAN2_BITRATE
+	int "CAN bitrate"
+	depends on !NET_CAN_CANFD
+	default 1000000
+
+config FLEXCAN2_SAMPLEP
+	int "CAN sample point"
+	depends on !NET_CAN_CANFD
+	default 80
+
+endmenu # IMXRT_FLEXCAN2
+
+menu "FLEXCAN3 Configuration"
+	depends on IMXRT_FLEXCAN3
+
+config FLEXCAN3_BITRATE
+	int "CAN bitrate"
+	depends on !NET_CAN_CANFD
+	default 1000000
+
+config FLEXCAN3_SAMPLEP
+	int "CAN sample point"
+	depends on !NET_CAN_CANFD
+	default 80
+
+config FLEXCAN3_ARBI_BITRATE
+	int "CAN FD Arbitration phase bitrate"
+	depends on NET_CAN_CANFD
+	default 1000000
+
+config FLEXCAN3_ARBI_SAMPLEP
+	int "CAN FD Arbitration phase sample point"
+	depends on NET_CAN_CANFD
+	default 80
+
+config FLEXCAN3_DATA_BITRATE
+	int "CAN FD Data phase bitrate"
+	depends on NET_CAN_CANFD
+	default 4000000
+
+config FLEXCAN3_DATA_SAMPLEP
+	int "CAN FD Data phase sample point"
+	depends on NET_CAN_CANFD
+	default 90
+
+endmenu # IMXRT_FLEXCAN3
+
 menu "LPI2C Peripherals"
 
 menuconfig IMXRT_LPI2C1

arch/arm/src/imxrt/Make.defs

@@ -133,6 +133,10 @@ ifeq ($(CONFIG_IMXRT_LCD),y)
 CHIP_CSRCS += imxrt_lcd.c
 endif
 
+ifeq ($(CONFIG_IMXRT_FLEXCAN),y)
+CHIP_CSRCS += imxrt_flexcan.c
+endif
+
 ifeq ($(CONFIG_IMXRT_SNVS_LPSRTC),y)
 CHIP_CSRCS += imxrt_lpsrtc.c
 CHIP_CSRCS += imxrt_hprtc.c

arch/arm/src/imxrt/hardware/imxrt_iomuxc.h

@@ -165,6 +165,9 @@
 #define IOMUX_ENET_TX_CLK_DEFAULT             (IOMUX_SLEW_FAST | IOMUX_DRIVE_40OHM | IOMUX_SPEED_LOW | \
                                                IOMUX_PULL_DOWN_100K | IOMUX_PULL_KEEP | GPIO_SION_ENABLE )
 
+#define IOMUX_CAN_DEFAULT                     (IOMUX_SLEW_SLOW | \
+                                               IOMUX_DRIVE_50OHM | IOMUX_SPEED_LOW )
+
 #define IOMUX_USDHC1_DATAX_DEFAULT            (IOMUX_SLEW_FAST | IOMUX_DRIVE_130OHM | \
                                                IOMUX_PULL_UP_47K | IOMUX_SCHMITT_TRIGGER)
 #define IOMUX_USDHC1_CMD_DEFAULT              (IOMUX_SLEW_FAST | IOMUX_DRIVE_130OHM | \

arch/arm/src/imxrt/hardware/rt106x/imxrt106x_ccm.h

@@ -51,7 +51,7 @@
 /* Register offsets *****************************************************************************************/
 
 #define IMXRT_CCM_CCR_OFFSET                     0x0000  /* CCM Control Register */
-                                              /* 0x0004  Reserved */
+                                                         /* 0x0004  Reserved */
 #define IMXRT_CCM_CSR_OFFSET                     0x0008  /* CCM Status Register */
 #define IMXRT_CCM_CCSR_OFFSET                    0x000c  /* CCM Clock Switcher Register */
 #define IMXRT_CCM_CACRR_OFFSET                   0x0010  /* CCM Arm Clock Root Register */
@@ -63,14 +63,14 @@
 #define IMXRT_CCM_CS1CDR_OFFSET                  0x0028  /* CCM Clock Divider Register */
 #define IMXRT_CCM_CS2CDR_OFFSET                  0x002c  /* CCM Clock Divider Register */
 #define IMXRT_CCM_CDCDR_OFFSET                   0x0030  /* CCM D1 Clock Divider Register */
-                                              /* 0x0034  Reserved */
+                                                         /* 0x0034  Reserved */
 #define IMXRT_CCM_CSCDR2_OFFSET                  0x0038  /* CCM Serial Clock Divider Register 2 */
 #define IMXRT_CCM_CSCDR3_OFFSET                  0x003c  /* CCM Serial Clock Divider Register 3 */
-                                              /* 0x0040  Reserved */
-                                              /* 0x0044  Reserved */
+                                                         /* 0x0040  Reserved */
+                                                         /* 0x0044  Reserved */
 #define IMXRT_CCM_CDHIPR_OFFSET                  0x0048  /* CCM Divider Handshake In-Process Register */
-                                              /* 0x004c  Reserved */
-                                              /* 0x0050  Reserved */
+                                                         /* 0x004c  Reserved */
+                                                         /* 0x0050  Reserved */
 #define IMXRT_CCM_CLPCR_OFFSET                   0x0054  /* CCM Low Power Control Register */
 
 #define IMXRT_CCM_CISR_OFFSET                    0x0058  /* CCM Interrupt Status Register */
@@ -84,7 +84,8 @@
 #define IMXRT_CCM_CCGR4_OFFSET                   0x0078  /* CCM Clock Gating Register 4 */
 #define IMXRT_CCM_CCGR5_OFFSET                   0x007c  /* CCM Clock Gating Register 5 */
 #define IMXRT_CCM_CCGR6_OFFSET                   0x0080  /* CCM Clock Gating Register 6 */
-                                              /* 0x0084  Reserved */
+#define IMXRT_CCM_CCGR7_OFFSET                   0x0084  /* CCM Clock Gating Register 7 */
+                                                         /* 0x0084  Reserved */
 #define IMXRT_CCM_CMEOR_OFFSET                   0x0088  /* CCM Module Enable Override Register */
 
 /* Analog */
@@ -138,6 +139,7 @@
 #define IMXRT_CCM_CCGR4                          (IMXRT_CCM_BASE + IMXRT_CCM_CCGR4_OFFSET)
 #define IMXRT_CCM_CCGR5                          (IMXRT_CCM_BASE + IMXRT_CCM_CCGR5_OFFSET)
 #define IMXRT_CCM_CCGR6                          (IMXRT_CCM_BASE + IMXRT_CCM_CCGR6_OFFSET)
+#define IMXRT_CCM_CCGR7                          (IMXRT_CCM_BASE + IMXRT_CCM_CCGR7_OFFSET)
 #define IMXRT_CCM_CMEOR                          (IMXRT_CCM_BASE + IMXRT_CCM_CMEOR_OFFSET)
 
 #define IMXRT_CCM_ANALOG_PLL_ARM                 (IMXRT_ANATOP_BASE + IMXRT_CCM_ANALOG_PLL_ARM_OFFSET)
@@ -180,6 +182,7 @@
 #  define CCM_CCR_REG_BYPASS_COUNT(n)            ((uint32_t)(n) << CCM_CCR_REG_BYPASS_COUNT_SHIFT)
 #define CCM_CCR_RBC_EN                           (1 << 27) /* Bit  27:    Enable for REG_BYPASS_COUNTER */
                                                            /* Bits 28-31: Reserved */
+
 /*  Status Register  */
 
 #define CCM_CSR_REF_EN_B                         (1 << 0)  /* Bit 0:      Status of the value of CCM_REF_EN_B */
@@ -188,6 +191,7 @@
                                                            /* Bit 4:      Reserved */
 #define CCM_CSR_COSC_READY                       (5 << 0)  /* Bit 5:      Status indication of on board oscillator */
                                                            /* Bits 6-31:  Reserved */
+
 /* Clock Switcher Register */
 
 #define CCM_CCSR_PLL3_SW_CLK_SEL                 (1 << 0)  /* Bit 0: Selects source to generate pll3_sw_clk */
@@ -487,6 +491,7 @@
 #  define CCM_CLPCR_LPM_RUN                      ((uint32_t)(0) << CCM_CLPCR_LPM_SHIFT) /* Remain in run mode */
 #  define CCM_CLPCR_LPM_WAIT                     ((uint32_t)(1) << CCM_CLPCR_LPM_SHIFT) /* Transfer to wait mode */
 #  define CCM_CLPCR_LPM_STOP                     ((uint32_t)(2) << CCM_CLPCR_LPM_SHIFT) /* Transfer to stop mode */
+
                                                            /* Bits 2-4:   Reserved */
 #define CCM_CLPCR_ARM_CLK_DIS_ON_LPM             (1 << 5)  /* Bit 5:      ARM clocks disabled on wait mode */
 #define CCM_CLPCR_SBYOS                          (1 << 6)  /* Bit 6:      Standby clock oscillator bit */
@@ -764,14 +769,23 @@
 #define CCM_CCGR_USDHC1                          IMXRT_CCM_CCGR6, 1
 #define CCM_CCGR_USBOH3                          IMXRT_CCM_CCGR6, 0
 
+#define CCM_CCGR_FLEXIO                          IMXRT_CCM_CCGR7, 6
+#define CCM_CCGR_AIPS                            IMXRT_CCM_CCGR7, 5
+#define CCM_CCGR_CAN3_SERIAL                     IMXRT_CCM_CCGR7, 4
+#define CCM_CCGR_CAN3                            IMXRT_CCM_CCGR7, 3
+#define CCM_CCGR_AXBS                            IMXRT_CCM_CCGR7, 2
+#define CCM_CCGR_FLEXSPI2                        IMXRT_CCM_CCGR7, 1
+#define CCM_CCGR_ENET2                           IMXRT_CCM_CCGR7, 0
+
 /* Module Enable Override Register */
 
                                                            /* Bits 0-4: Reserved */
 #define CCM_CMEOR_MOD_EN_OV_GPT                  (1 << 5)  /* Bit 5:      Override clock enable signal from GPT */
 #define CCM_CMEOR_MOD_EN_OV_PIT                  (1 << 6)  /* Bit 6:      Override clock enable signal from PIT */
 #define CCM_CMEOR_MOD_EN_OV_USDHC                (1 << 7)  /* Bit 7:      Override clock enable signal from USDHC */
 #define CCM_CMEOR_MOD_EN_OV_TRNG                 (1 << 9)  /* Bit 9:      Override clock enable signal from TRNG */
-                                                           /* Bits 10-27: Reserved */
+#define CCM_CMEOR_MOD_EN_OV_CANFD_CPI            (1 << 10) /* Bit 10:     Override clock enable signal from CAN3 */ 
+                                                           /* Bits 11-27: Reserved */
 #define CCM_CMEOR_MOD_EN_OV_CAN2_CPI             (1 << 28) /* Bit 28:     Override clock enable signal from CAN2 */
 #define CCM_CMEOR_MOD_EN_OV_CAN1_CPI             (1 << 30) /* Bit 30:     Override clock enable signal from CAN1 */
                                                            /* Bit 31:     Reserved */
@@ -788,7 +802,8 @@
 #define CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_MASK          (0x3 << CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_SHIFT)
 #  define CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_REF_24M     ((uint32_t)(0) << CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_SHIFT) /* Select 24Mhz Osc as source */
 #  define CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_CLK1        ((uint32_t)(1) << CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_SHIFT) /* Select the CLK1_N / CLK1_P as source */
-#define CCM_ANALOG_PLL_ARM_BYPASS                       (1 << 16) /* Bit 16:     Bypass the PLL */
+#define CCM_ANALOG_PLL_ARM_BYPASS                       (1 << 16)                                                  /* Bit 16:     Bypass the PLL */
+
                                                                   /* Bits 17-18  Reserved */
 #define CCM_ANALOG_PLL_ARM_PLL_SEL                      (1 << 39) /* Bit 19:     ? */
 #define CCM_ANALOG_PLL_ARM_LOCK                         (1 << 31) /* Bit 31:     PLL is currently locked */
@@ -809,7 +824,8 @@
 #  define CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_CLK1       ((uint32_t)(1) << CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_SHIFT) /* Select the CLK1_N / CLK1_P as source */
 #  define CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_GPANAIO    ((uint32_t)(2) << CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_SHIFT) /*  */
 #  define CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_CHRG_DET_B ((uint32_t)(3) << CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_SHIFT) /*  */
-#define CCM_ANALOG_PLL_USB1_BYPASS                      (1 << 16) /* Bit 16:     Bypass the PLL */
+#define CCM_ANALOG_PLL_USB1_BYPASS                      (1 << 16)                                                   /* Bit 16:     Bypass the PLL */
+
                                                                   /* Bits 17-30  Reserved */
 #define CCM_ANALOG_PLL_USB1_LOCK                        (1 << 31) /* Bit 31:     PLL is currently locked */
 
@@ -827,7 +843,8 @@
 #define CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC_MASK         (0x3 << CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC_SHIFT)
 #  define CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC_REF_24M    ((uint32_t)(0) << CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC_SHIFT) /* Select 24Mhz Osc as source */
 #  define CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC_CLK1       ((uint32_t)(1) << CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC_SHIFT) /* Select the CLK1_N / CLK1_P as source */
-#define CCM_ANALOG_PLL_USB2_BYPASS                      (1 << 16) /* Bit 16:     Bypass the PLL */
+#define CCM_ANALOG_PLL_USB2_BYPASS                      (1 << 16)                                                   /* Bit 16:     Bypass the PLL */
+
                                                                   /* Bits 17-30  Reserved */
 #define CCM_ANALOG_PLL_USB2_LOCK                        (1 << 31) /* Bit 31:     PLL is currently locked */
 
@@ -846,9 +863,11 @@
 #  define CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_CLK1        ((uint32_t)(1) << CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_SHIFT) /* Select the CLK1_N / CLK1_P as source */
 #  define CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_GPANAIO     ((uint32_t)(2) << CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_SHIFT) /*  */
 #  define CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_CHRG_DET_B  ((uint32_t)(3) << CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_SHIFT) /*  */
-#define CCM_ANALOG_PLL_SYS_BYPASS                       (1 << 16) /* Bit 16:     Bypass the PLL */
+#define CCM_ANALOG_PLL_SYS_BYPASS                       (1 << 16)                                                  /* Bit 16:     Bypass the PLL */
+
                                                                   /* Bit 17:     Reserved */
 #define CCM_ANALOG_PLL_SYS_PFD_OFFSET_EN                (1 << 18) /* Bit 18:     Enables an offset in the phase frequency detector */
+
                                                                   /* Bits 19-30  Reserved */
 #define CCM_ANALOG_PLL_SYS_LOCK                         (1 << 31) /* Bit 31:     PLL is currently locked */
 
@@ -888,7 +907,8 @@
 #define CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_MASK        (0x3 << CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_SHIFT)
 #  define CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_REF_24M   ((uint32_t)(0) << CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_SHIFT) /* Select 24Mhz Osc as source */
 #  define CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_CLK1      ((uint32_t)(1) << CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_SHIFT) /* Select the CLK1_N / CLK1_P as source */
-#define CCM_ANALOG_PLL_AUDIO_BYPASS                     (1 << 16) /* Bit 16:     Bypass the PLL */
+#define CCM_ANALOG_PLL_AUDIO_BYPASS                     (1 << 16)                                                    /* Bit 16:     Bypass the PLL */
+
                                                                   /* Bit 17:     Reserved */
 #define CCM_ANALOG_PLL_AUDIO_PFD_OFFSET_EN              (1 << 18) /* Bit 18:     Enables an offset in the phase frequency detector */
 #define CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_SHIFT      (19)      /* Bits 19-20: These bits implement a divider after the PLL */
@@ -911,7 +931,8 @@
 #define CCM_ANALOG_PLL_AUDIO_DENOM_B_SHIFT              (0)       /* Bits 0-29:   30 bit numerator (A) */
 #define CCM_ANALOG_PLL_AUDIO_DENOM_B_MASK               (0x3FFFFFFF << CCM_ANALOG_PLL_AUDIO_DENOM_B_SHIFT)
 #define CCM_ANALOG_PLL_AUDIO_DENOM_B(n)                 ((uint32_t)(n) << CCM_ANALOG_PLL_AUDIO_DENOM_B_SHIFT)
-                                                                    /* Bits 30-31:  Reserved */
+                                                                  /* Bits 30-31:  Reserved */
+
 /*  Analog Video PLL control Register */
 
 #define CCM_ANALOG_PLL_VIDEO_DIV_SELECT_SHIFT           (0)       /* Bits 0-6:    This field controls the PLL loop divider: 27-54 */
@@ -924,7 +945,8 @@
 #define CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_MASK        (0x3 << CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_SHIFT)
 #  define CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_REF_24M   ((uint32_t)(0) << CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_SHIFT) /* Select 24Mhz Osc as source */
 #  define CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_CLK1      ((uint32_t)(1) << CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_SHIFT) /* Select the CLK1_N / CLK1_P as source */
-#define CCM_ANALOG_PLL_VIDEO_BYPASS                     (1 << 16) /* Bit 16:     Bypass the PLL */
+#define CCM_ANALOG_PLL_VIDEO_BYPASS                     (1 << 16)                                                    /* Bit 16:     Bypass the PLL */
+
                                                                   /* Bit 17:     Reserved */
 #define CCM_ANALOG_PLL_VIDEO_PFD_OFFSET_EN              (1 << 18) /* Bit 18:     Enables an offset in the phase frequency detector */
 #define CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT_SHIFT      (19)      /* Bits 19-20: These bits implement a divider after the PLL */
@@ -966,11 +988,12 @@
                                                                   /* Bits 4-11:  Reserved */
 #define CCM_ANALOG_PLL_ENET_POWERDOWN                   (1 << 12) /* Bit 12:     Powers down the PLL */
 #define CCM_ANALOG_PLL_ENET_ENET1_125M_EN               (1 << 13) /* Bit 13:     Enable the PLL providing the ENET1 125 MHz reference clock */
-#define CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_SHIFT       (14)      /* Bits 14-15: Determines the bypass source */
+#define CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_SHIFT       (14)       /* Bits 14-15: Determines the bypass source */
 #define CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_MASK        (0x3 << CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_SHIFT)
 #  define CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_REF_24M   ((uint32_t)(0) << CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_SHIFT) /* Select 24Mhz Osc as source */
 #  define CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_CLK1      ((uint32_t)(1) << CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_SHIFT) /* Select the CLK1_N / CLK1_P as source */
-#define CCM_ANALOG_PLL_ENET_BYPASS                     (1 << 16) /* Bit 16:     Bypass the PLL */
+#define CCM_ANALOG_PLL_ENET_BYPASS                     (1 << 16)                                                   /* Bit 16:     Bypass the PLL */
+
                                                                  /* Bit 17:     Reserved */
 #define CCM_ANALOG_PLL_ENET_PFD_OFFSET_EN              (1 << 18) /* Bit 18:     Enables an offset in the phase frequency detector */
 #define CCM_ANALOG_PLL_ENET_ENABLE_125M                (1 << 19) /* Bit 19:     */

arch/arm/src/imxrt/hardware/rt106x/imxrt106x_pinmux.h

@@ -43,6 +43,7 @@
 
 #include <nuttx/config.h>
 #include "imxrt_iomuxc.h"
+#include "imxrt_gpio.h"
 
 /*****************************************************************************
  * Pre-processor Definitions

arch/arm/src/imxrt/imxrt_clockconfig.c

@@ -619,6 +619,25 @@ void imxrt_clockconfig(void)
 
 #endif
 
+#ifdef CONFIG_IMXRT_FLEXCAN
+  /* Set FlexCAN clock source to PLL3 80M */
+
+  reg = getreg32(IMXRT_CCM_CSCMR2);
+  reg &= ~CCM_CSCMR2_CAN_CLK_SEL_MASK;
+  reg |= IMXRT_CAN_CLK_SELECT;
+  putreg32(reg, IMXRT_CCM_CSCMR2);
+
+  /* Set FlexCAN dividet to 1 for 80 MHz */
+
+  reg  = getreg32(IMXRT_CCM_CSCMR2);
+  reg &= ~CCM_CSCMR2_CAN_CLK_PODF_MASK;
+  reg |= CCM_CSCMR2_CAN_CLK_PODF(
+           CCM_PODF_FROM_DIVISOR(IMXRT_CAN_PODF_DIVIDER)
+         );
+  putreg32(reg, IMXRT_CCM_CSCMR2);
+
+#endif
+
 #ifdef CONFIG_IMXRT_LPSPI
   /* Set LPSPI clock source to PLL3 PFD0 */