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Add the optional interrupt stack to the Xtensa architecture #2014
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| Original file line number | Diff line number | Diff line change |
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@@ -68,6 +68,19 @@ | |
| #include "chip_macros.h" | ||
| #include "xtensa_timer.h" | ||
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| #if !defined(CONFIG_SMP) && CONFIG_ARCH_INTERRUPTSTACK > 15 | ||
| .data | ||
| .align 16 | ||
| .global g_intstackalloc | ||
| .global g_intstackbase | ||
| .type g_intstackalloc, @object | ||
| .type g_intstackbase, @object | ||
| g_intstackalloc: | ||
| .skip INTSTACK_SIZE | ||
| g_intstackbase: | ||
| .size g_intstackalloc, .-g_intstackalloc | ||
| #endif | ||
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| /**************************************************************************** | ||
| * Assembly Language Macros | ||
| ****************************************************************************/ | ||
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@@ -91,6 +104,21 @@ | |
| addi \aout, \aout, 1 /* Return aout + 1 */ | ||
| .endm | ||
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| /************************************************************************************ | ||
| * Name: setintstack | ||
| * | ||
| * Description: | ||
| * Set the current stack pointer to the "top" the interrupt stack. Single CPU | ||
| * case. Must be provided by MCU-specific logic in the SMP case. | ||
| * | ||
| ************************************************************************************/ | ||
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| #if !defined(CONFIG_SMP) && CONFIG_ARCH_INTERRUPTSTACK > 15 | ||
| .macro setintstack tmp1 tmp2 | ||
| movi a1, g_intstackbase | ||
| .endm | ||
| #endif | ||
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| /**************************************************************************** | ||
| * Macro dispatch_c_isr level mask | ||
| * | ||
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@@ -112,6 +140,7 @@ | |
| * Entry Conditions/Side Effects: | ||
| * level - interrupt level | ||
| * mask - interrupt bitmask for this level | ||
| * a12 - register save area | ||
| * | ||
| * Exit Conditions: | ||
| * This macro will use registers a0 and a2-a5 and a12. | ||
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@@ -122,12 +151,6 @@ | |
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| .macro dispatch_c_isr level mask | ||
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| /* Initially the register save area is in SP, but that could change as | ||
| * a consequence of context switching. | ||
| */ | ||
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| mov a12, sp /* Address of save area */ | ||
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| #ifdef __XTENSA_CALL0_ABI__ | ||
| /* Get mask of pending, enabled interrupts at this level into a2. */ | ||
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@@ -143,7 +166,7 @@ | |
| */ | ||
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| /* Argument 1: Set of CPU interrupt to dispatch */ | ||
| mov a3, sp /* Argument 2: Top of stack = register save area */ | ||
| mov a3, a12 /* Argument 2: Top of stack = register save area */ | ||
| call0 xtensa_int_decode /* Call xtensa_int_decode */ | ||
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| /* On return from xtensa_int_decode, a2 will contain the address of the new | ||
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@@ -169,7 +192,7 @@ | |
| */ | ||
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| /* Argument 1: Set of CPU interrupt to dispatch */ | ||
| mov a7, sp /* Argument 2: Top of stack = register save area */ | ||
| mov a7, a12 /* Argument 2: Top of stack = register save area */ | ||
| call4 xtensa_int_decode /* Call xtensa_int_decode */ | ||
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| /* On return from xtensa_int_decode, a6 will contain the address of the new | ||
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@@ -263,6 +286,19 @@ _xtensa_level1_handler: | |
| mov a2, sp /* Address of state save on stack */ | ||
| call0 _xtensa_context_save /* Save full register state */ | ||
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| /* Save current SP before (possibly) overwriting it, it's the register save | ||
| * area. This value will be used later by dispatch_c_isr to retrive the | ||
| * register save area. | ||
| */ | ||
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| mov a12, sp | ||
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| /* Switch to an interrupt stack if we have one */ | ||
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| #if CONFIG_ARCH_INTERRUPTSTACK > 15 | ||
| setintstack a13 a14 | ||
| #endif | ||
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Contributor
There was a problem hiding this comment. Choose a reason for hiding this commentThe reason will be displayed to describe this comment to others. Learn more. I think we need to adjust (i.e. subtract 16?) the stack pointer (a1?) to avoid data corruption, because g_cpu_intstack_top does not include offset now.
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Author
There was a problem hiding this comment. Choose a reason for hiding this commentThe reason will be displayed to describe this comment to others. Learn more. I'll run more tests with the adjustment this evening and verify the memories. Thanks for the reminder.
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There was a problem hiding this comment. Choose a reason for hiding this commentThe reason will be displayed to describe this comment to others. Learn more. @masayuki2009 I don't think that's necessary, same as the discussion we were having with ARM, the SP is decremented on procedures entry.
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There was a problem hiding this comment. Choose a reason for hiding this commentThe reason will be displayed to describe this comment to others. Learn more. @Ouss4
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Author
There was a problem hiding this comment. Choose a reason for hiding this commentThe reason will be displayed to describe this comment to others. Learn more. No problem, there was no confusion :) |
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| /* Set up PS for C, enable interrupts above this level and clear EXCM. */ | ||
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| ps_setup 1 a0 | ||
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For Xtensa architecture, does .align 16 mean 16-byte alignment?
For ARM architecture, .align n means 2^n but it confuses me. So I will refactor them for ARM later.
However, we can use .balign instead of .align.
Please see the following URL.
https://developer.arm.com/documentation/dui0742/c/migrating-arm-syntax-assembly-code-to-gnu-syntax/alignment
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Yes, it means 16-byte alignement. (ref. https://sourceware.org/binutils/docs-2.25/as/Align.html)
Here is the relevant text:
There is also a clearer example here.